KR100233537B1 - Run-level symbol decoding method and the apparatus - Google Patents

Abstract

The present disclosure relates to a run-level symbol decoding method and apparatus for decoding [run, level] symbols according to the same scan pattern as used in the encoding process. The apparatus of the present invention receives a [run, level] symbol, and separates the data into run and level data, respectively, and outputs all stored contents according to an initialization signal applied before the start of run-level decoding of each block data. The data storage unit resets to "0" and stores the separated level data in the position designated by the applied address, and outputs it as run-level decoded data in units of blocks. An enable unit which controls the data storage unit not to store the data for a length of a clock period, and prestores each of the scan addresses corresponding to the scanning order of various scan patterns in a table form and initializes the address pointer according to an applied initialization signal. The address pointer of the same scan pattern as the scan pattern used for variable length encoding based on the scan pattern index And an address output section for outputting a scan address corresponding to the clock. Accordingly, the present invention provides an effect of obtaining run-level decoded data by storing only level data without having to store data zeros as much as run length corresponding to run data.

Description

Run-level symbol decoding method and apparatus

The present invention relates to a decoding system for decoding variable length coded data, and more particularly, to a method and apparatus for decoding a variable length coded run-level symbol by using a scan pattern selected from various scan patterns. It is about.

Recently, various methods of encoding video data and / or transmitting the video and audio signals or storing the data in a storage medium, and decoding the encoded digital data to reproduce the video and audio signals, transmit the video and audio signals. And in a system for receiving. However, in order to improve data transmission efficiency in such an encoding and decoding system, a technique for further reducing the amount of transmission data has been required. Examples of methods for encoding digital data to be transmitted or stored include transform coding, differential pulse code modulation (DPCM), vector quantization, and variable length coding. These encoding methods further reduce the total amount of data by eliminating redundant data in the transmitted or stored digital data.

The image data of each frame is divided into blocks of a predetermined size and processed in an encoding and decoding system for storing or transmitting and receiving an image signal. Each block data or difference data between the block data is orthogonal-transformed, and the image data is converted into transform coefficients of a frequency domain. Known block data transformation methods include Discrete Cosine Transform (DCT), Walsh-Hadamard Transform (WHT), Discrete Fourier Transform (DFT) and Discrete Sine Transform. ; DST). The conversion coefficients obtained by these conversion methods are appropriately quantized and variable length coded according to the characteristics of the coefficient data, thereby increasing the compression efficiency. Since human visual perception is more sensitive to low frequencies than high frequencies, high frequency component data is reduced by data processing. Thus, the encoded data amount can be reduced.

An apparatus for variable length coding compresses data based on probabilities of symbols, and has a variable length code table for variable length coding the input symbols. This variable long code table is designed according to the Huffman coding technique. Huffman coding, as is well known, assigns shorter codes to symbols with relatively high occurrence frequency and codes with longer codes to symbols with relatively low occurrence frequency. In the conventional coding system, the symbols input to the variable length encoding apparatus are [run, level] symbols that are usually obtained by run-length encoding. The data divided into blocks of 8x8 pixel size are transformed into a frequency domain and then quantized on the basis of MPEG related to image standardization. The quantized transform coefficients are represented in 8-by-8 size two-dimensional frequency domain, and are encoded into run (run, level) symbols by a well-known zigzag scan that scans from low frequency to high frequency in two-dimensional frequency space. do. Here, run means the number of occurrences of 0 between coefficients that are not "0", and level means the absolute value of the coefficient which is not "0". For an 8x8 frequency domain, a run can have values from "0" to "63", where the quantized transform coefficient is from "-255" to "255" and the sign is It is displayed separately.

The use of the zigzag scan pattern results from the phenomenon that the energy of the image signal is concentrated in the low frequency region centered on the DC component. However, the energy of the video signal may be distributed more intensively or more widely toward the horizontal frequency component or the vertical frequency component according to the pattern of the video signal. Therefore, the existing zigzag scan pattern is not always an optimal scan pattern for variable length encoding of image data. Therefore, scan patterns that can be flexibly concentrated in the horizontal or vertical direction of the two-dimensional frequency domain according to the distribution characteristics of the image data are desired for variable length encoding and decoding. Prior art for this purpose is disclosed in "Variable Coded Encoding and Decoding System" of No. 92-13171 filed by the same applicant.

In the above prior art, the digital data divided into blocks of a predetermined size is variable-length coded according to various scan patterns, and the length of the variable-length coded data is accumulated corresponding to each of the scan patterns, with a minimum accumulation. The scan pattern corresponding to the length is selected. Both the selected scan pattern and the variable length coded data corresponding to the selected scan pattern are transmitted. For decoding, the variable length coded data is variably decoded while being scanned according to the same scan pattern as the scan pattern selected during variable length coding. Therefore, an optimal scan pattern is used for variable length encoding and decoding of block data, thereby improving data compression efficiency. The variable length decoding apparatus described in FIG. 6 of such an application is shown in FIG. 1, and this variable length decoding apparatus will be described.

1 shows an example of a conventional variable length decoding apparatus. Referring to FIG. 1, the variable length coded data D _VLC and the corresponding scan pattern data D _SCAN transmitted from an encoding device (not shown) may be converted into a variable length decoder 11 and a scan pattern selector 12. Enter each). The variable length decoding unit 11 converts the input variable length encoded data D _VLC into [run, level] symbols according to the variable length decoding table. The scan pattern selector 12 stores scan addresses corresponding to various scan patterns 1 to N corresponding to each of the scan patterns, and scan addresses ADDRs corresponding to the input scan pattern data D _SCAN . Select) to print. The run-level decoding unit 13 stores the [run, level] symbols input from the variable length decoding unit 11 according to the scan addresses ADDRs input from the scan pattern selection unit 12. to quantization coefficients expressed in domain). Then, the quantization coefficients are fed to the back quantization unit (not shown).

Accordingly, an object of the present invention is to provide a method for decoding [run, level] symbols in a decoding system for decoding block data according to the same scan pattern used in the encoding process of each block data as described above.

Another object of the present invention is to provide an apparatus for implementing the aforementioned run-level symbol decoding method in hardware.

1 is a block diagram showing an example of a conventional variable length decoding apparatus.

2 is a block diagram showing a run-level symbol decoding apparatus according to a preferred embodiment of the present invention.

3 (a)-(b) are diagrams for explaining the scanning order of a zigzag scan pattern and an alternate scan pattern.

4 is a table for scan addresses corresponding to the scan sequences described in relation to FIGS. 3 (a)-(b).

5 is a timing diagram for explaining the operation of the apparatus of FIG.

* Explanation of symbols for main parts of the drawings

21: symbol separation unit 22: address output unit

23: enable unit 24: data storage unit

The run-level symbol decoding method for achieving the above objects is a method of decoding block data according to the same scan pattern used in the encoding process of data. Resetting the contents to "0", (2) receiving a scan pattern index corresponding to the scan pattern used in the variable length-decoded [run, level] symbol and the encoding process, and (3) the supplied Outputting the [run, level] symbols into run and level data, respectively, and (4) enabling the first level for a clock period corresponding to the run data by receiving the separated run data and the clock; Outputting a signal, and outputting an enable signal of a second level during the other clock periods, and (5) preset scan addresses corresponding to the supplied scan pattern indexes; Outputting according to the separated run data and the clock; and (6) storing the separated level data at a position corresponding to the output scan address while the enable signal of the second level is applied. Outputting the level-decoded data.

A run-level symbol decoding apparatus for achieving another object of the present invention is a device for decoding block data according to the same scan pattern as used in the data encoding process, wherein the variable-length decoded [run, level] symbols are input. A symbol separation unit that receives and outputs each of the run data and the level data and outputs the scan data according to the scanning order of each of the plurality of scan patterns, and receives a scan pattern index corresponding to the used scan pattern and scans the corresponding scan pattern index. The address output unit outputs the stored scan addresses of the pattern according to the separated run data and the clock, and resets all the stored contents to "0" according to the applied initialization signal. The level data output from the symbol separator is reset. The data to be stored in the storage location specified by the scan address from the address output section. A storage unit receives the run data input to the clock and the address output unit, and activates a storage operation of the data storage unit when the number of pulses of the clock has elapsed by the number corresponding to the received run data. It includes an enable unit for generating an enable signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a run-level symbol decoding apparatus according to the present invention. The apparatus shown in FIG. 2 receives [run, level] symbols consisting of pairs of run and level applied from a variable length decoding unit (not shown), and outputs them separately from run data and run level data, respectively. According to the symbol separator 21 and an initialization signal applied before the start of run-level decoding of the symbols of every block, all the contents of the reset are reset to "0", and then, the symbol separator ( And a data storage unit 24 for storing the level data LEVEL separated by 21). The apparatus of FIG. 2 also stores scan addresses corresponding to the scan order of each of the plurality of scan patterns in a table form, and includes a run data and a clock separated from the initialization signal and the scan pattern index Scan_pattern. And an address output unit 22 that receives (CLOCK) and generates a scan address ADDR of a corresponding scan pattern. The separated run data and the clock are also input to the enable unit 23 to output an enable signal as shown in FIG. 5 for controlling the storage operation of the data storage unit 24. It is configured to.

The operation of the run-level symbol decoding apparatus of the present invention having such a configuration will be described in more detail with reference to FIGS. 3 to 5.

3 (a)-(b) are diagrams for explaining the scanning order of a zigzag scan pattern and an alternate scan pattern, and FIG. 4 is a scan pattern described with reference to FIGS. 3 (a)-(b). FIG. 5 is a table for scan addresses corresponding to the above figure, and FIG. 5 is a timing diagram for explaining the operation of the apparatus of FIG.

The initialization signal generated by the controller (not shown) is input to the address output section 22 and the data storage section 24 before run-level decoding is started for each block. Each time an initialization signal is input, the address output section 22 initializes the current address pointer and the data storage section 24 resets all the stored contents to " 0 ". Here, the data storage unit 24 resets all memory cells constituting the data storage unit 24 to “0” at a time or resets the memory cells in a row unit. Since the list technique of memory cells for initialization is common to those skilled in the memory art, the description thereof is omitted.

When the [run, level] symbol is applied from the variable length decoding unit (not shown) while the memory cells of the address pointer and the data storage unit 24 are initialized, the symbol separation unit 21 applies the [run, level ] Separate symbols into RUN and level data. As shown in FIG. 5, the symbol separator 21 separates the run data “3” and the level data “LEVEL” “5” when the [run, level] symbol is [3,5]. (RUN) "3" is output to the address output section 22 and the enable section 23, and the level data LEVEL "5" is output to the data storage section 24. Preferably, the symbol separator 21 outputs the level data with respect to the received individual symbols when the period of time corresponding to the run length of the run data has elapsed. The enable unit 23 receives the run data " 3 " and the clock CLOCK shown in FIG. 5 to control the data storage operation of the data storage unit 24, as shown in FIG. An enable signal, which is likely to be generated, is supplied to the data storage unit 24. More specifically, the enable unit 23 outputs an enable signal having a “L” level during the clock pulse period corresponding to the run length of the run data RUN, and then During one clock pulse period, an enable signal of high level is enabled. Therefore, the enable signal of the "high" level is enabled by the data from the enable unit 23 at the time when the data storage unit 24 stores the level data LEVEL supplied from the symbol separator 21. It is supplied to the storage unit 24. The address output unit 22 receiving the same clock CLOCK as the clock CLOCK input to the enable unit 23 includes two scan patterns shown in FIGS. 3A and 3B. Scan addresses corresponding to the scanning order of each of the plurality of scan patterns are stored in a table form as shown in FIG.

In block data of 8x8 pixel size, FIG. 3 (a) shows the scanning order of the zigzag scan pattern, and FIG. 3 (b) shows the scanning order of the alternate scan pattern. Corresponding to the scanning order of these scan patterns, the table of FIG. 4 shows the scan address offset from the initial address in the inter encoding mode. Referring to FIG. 4, the address offset corresponding to the scanning order “1” of the scan patterns is “0”, and the position at which the first data to be scanned corresponds to the DC component in the DCT component coefficient (that is, (0,0) as the coordinate point). ). However, in the Intra coding mode, the scan sequence starts at "2" at the beginning of each block. In the Intra coding mode, the DC component is transmitted separately and only the AC component is scanned. Is based on the transmission.

Meanwhile, whenever an initialization signal is applied, the address output unit 22 selects one of the plurality of scan patterns according to the scan pattern index Scan_pattern corresponding to the scan pattern used for the run-level encoding in the encoding apparatus. Selects and initializes the address pointer to point to the first scan address among the scan addresses associated with the selected scan pattern. In this state, the address output unit 22 stores each of the scan addresses ADDR associated with the scan pattern corresponding to the scan pattern data Scan_pattern input from the outside in synchronization with each pulse of the input clock CLOCK. Output to (24). The address output unit 22 that receives the run data RUN determines the location of the address pointer of the corresponding level data LEVEL based on the selected scan pattern and the received run data RUN, and has a determined scan address having the determined position. ADDR) is output to the data storage unit 24 in accordance with the clock (CLOCK) of FIG. The data storage unit 24 that receives the level data LEVEL output from the symbol separation unit 21 has an address while the enable signal applied from the enable unit 23 is at the "L" level. Even when the scan address ADDR is applied from the output unit 22, the storage operation for the data supplied from the symbol separation unit 21 is not performed. The data storage unit 24 outputs the level data LEVEL supplied from the symbol separation unit 21 while the enable signal applied from the enable unit 23 is at the “high” level. The data stored in the storage address corresponding to the scan address ADDR output from 22 is stored. Therefore, in the case where the run data RUN is "3" and the level data LEVEL "5", the data storage unit 24 shows the scan address corresponding to the level data LEVEL "5" as shown in FIG. ADDR), i.e., stored in a storage location designated by the hatched scan address ADDR of FIG. The data storage section 24 has 64 memory cells from the storage locations, and the inverse quantization section at the rear end of the data stored in the storage locations including the data stored in association with each block is run-level decoded data. Output to (not shown).

As described above, the run-level symbol decoding method and apparatus according to the present invention reset all the stored contents of the data storage unit to “0” before starting the run-level decoding in units of blocks to zero as much as the run length. Alternatively, it is possible to perform run-level decoding because only the level data is stored in the corresponding location without storing the zeros.

Claims (8)

CLAIMS 1. A method for decoding block data according to the same scan pattern as used in the encoding process of data, the method comprising: (1) resetting all decoded and stored contents to zero each time an initialization signal is applied; (2) receiving a scan pattern index corresponding to the scan pattern used in the variable length-decoded [run, level] symbol and the encoding process; (3) separating the supplied [run, level] symbols into run and level data and outputting the data; (4) receiving the separated run data and the clock and outputting the enable signal of the first level for a clock period corresponding to the run data, and outputting the enable signal of the second level for other clock periods. step; (5) outputting preset scan addresses corresponding to the supplied scan pattern index according to the separated run data and the clock; And (6) storing the separated level data at a position corresponding to the output scan address while the enable signal of the second level is applied, and outputting the separated level data as run-level decoded data. Symbol decoding method. The method of claim 1, wherein the step (5) comprises: (5a) initializing an address pointer each time the initialization signal is applied; (5b) selecting one of a plurality of scan patterns in response to the scan pattern index; And (5c) when the run data is input, outputting scan addresses stored at positions indicated by a current address pointer among scan addresses of the selected scan pattern in order according to the clock. Symbol decoding method. The run-level symbol decoding method according to claim 2, wherein the initialization signal is applied before the decoding processing of block unit data starts. The run-level symbol decoding method of claim 1, wherein the step (5) does not perform a storage operation while the enable signal of the first level is applied. An apparatus for decoding block data according to the same scan pattern as used in the encoding process of data, comprising: a symbol separator for receiving variable length-decoded [run, level] symbols and separating them into run data and level data, respectively; Storing scan addresses according to the scanning order of each of the plurality of scan patterns, receiving a scan pattern index corresponding to the used scan pattern, and outputting the stored scan addresses of the corresponding scan pattern according to the separated run data and clock An address output unit; A data storage unit for resetting all stored contents to “0” according to an applied initialization signal and storing the level data output from the symbol separation unit in a storage location designated by a scan address from the address output unit; And receiving the run data input to the clock and the address output unit, and activating an enable signal for activating a storage operation of the data storage unit at a time point when the number of pulses of the clock corresponds to the received run data. A run-level symbol decoding apparatus including an enable portion that is generated. The run-level symbol decoding apparatus of claim 5, wherein the address output unit stores the scan addresses corresponding to the scan order of each scan pattern in a table form according to the scan order corresponding to each scan pattern. The apparatus of claim 6, wherein the address output unit sequentially outputs the scan addresses stored at positions indicated by the current address pointer among scan addresses of the scan pattern corresponding to the scan pattern index, in order according to the clock, when the run data is input. And initializes to point to a scan address having a first scan order whenever the initialization signal is applied. 8. The run-level symbol decoding apparatus of claim 7, wherein the initialization signal is applied before start of run-level decoding of every block data.

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