KR100232140B1 - Descrambler of digital broadcasting signal - Google Patents

Abstract

An apparatus for descrambling a digital broadcast signal satisfying a DVS data transmission ratio of 40 Mbps or more is proposed. The device descrambles the buffers for outputting the temporarily stored scrambled data, and descrambles the scrambled data into 32 clocks of 8 bytes according to the common clock signal, and alternately stores the result in the B0 and B1 intermediate buffers. The stream decipher receives the start signal from the stream decipher, loads data from the intermediate buffer into its internal register, loads one keyword per clock, and generates descrambled data with 56 clocks of 8 bytes. An exclusive logical sum of the B0 and B1 block deciphers, the key scheduler for providing internal keywords to the B0 and B1 block deciphers, the descrambling data of the BO and B1 intermediate buffers and the descrambling data of the B0 and B1 block deciphers. An exclusive-OR circuit that calculates and outputs the data, and the operation data of the exclusive-OR circuit And a descrambled data buffer that temporarily stores previous scrambled data. Therefore, the descrambling device is very useful for the set top for DVS.

Description

Descrambler of digital broadcasting signal

The present invention relates to an MPEG-2 (Moving Picture Experts Group) system for multiplexing multimedia, which is referred to as an international standard 2 of media integrated video compression, hereinafter referred to as 'MPEG-2' system. The present invention relates to a descrambling apparatus for digital broadcast signals suitable for satisfying a data transmission ratio.

In general, digital satellite broadcasting requires multiplexing of a TV signal. When multiplexing such a TV signal (video / audio signal), each of the video and audio is divided into a string of appropriate length called 'packets'. The video and audio packets are appropriately switched by attaching additional information such as a header and transmitted to the repeater (communication satellite) in a time division transmission method. The packet transmitted through the repeater can be restored to the original signal through the DBS (Direct Broadcasting System) receiver of the subscribers to view the channels transmitted from the broadcasting station.

In other words, the broadcasting station converts the TV signal into a digital TV signal, compresses it, and transmits it to the satellite, and the communication satellite receives and amplifies the TV signal in outer space and retransmits it through the repeater, and the TV signal relayed from the communication satellite is By receiving and demodulating by a receiver or a decoder, a program for a corresponding channel transmitted from a broadcasting station can be viewed.

At this time, the broadcasting station converts the video, audio, and transmission data signals into scrambled digital signals according to the MPEG-2 standard, compresses them, and composes a packet stream to form a TV signal stream. Multiple scrambled digital TV signal streams are multiplexed in a transport multiplexer into transport stream packets and sent to the channel encoder. The transport stream packet has a unit of 188 bytes and an effective data rate Ru is about 40 to 45 Mbps.

On the other hand, EP-DVB (European project-digital video broadcasting) has proposed common scrambling specifications. Referring to the schematic diagram of this specification, the 64-bit strings of control words read from the SAM (Scrambling Authorization Module) corresponding to the smart card are matched by a 64-bit common keyword signal through a matching mechanism, respectively, to the scrambling device and the descrambling. Is applied to the device.

At this time, the scrambling apparatus outputs the scrambled MPEG-2 transport packet according to the common keyword signal. The descrambling apparatus descrambles the scrambled MPEG-2 transport packet according to a common keyword signal.

This scramble operation takes place at the packetized elementary stream (PES) level, which is eliminated by the common key clock and consists of at least 184 bytes carried in the payload. Similarly, the descramble operation is controlled by a common key clock and takes place in order within the payload of the descrambled PES level.

As described above, the common scrambling specification proposed by EP-DVB has been proposed only a hardware conceptual diagram and a software algorithm, and thus no descrambling apparatus suitable for the common scrambling specification has been proposed.

Accordingly, an aspect of the present invention is to provide a device for descrambling a digital broadcast signal having a 64-bit operation that satisfies the above-described common scrambling specification and satisfies a data transmission ratio of DVB of 40 Mbps or more.

Another object of the present invention is to provide an apparatus for descrambling a digital broadcast signal in which elements for descrambling are connected in a pipelined manner.

1 is a block diagram showing an apparatus for descrambling a digital broadcast signal according to the present invention;

2 is an operation timing chart of a stream decipher and a block decipher of FIG. 1;

3 is a diagram illustrating keyword switching scheduling when control word data is input to keyword registers of the key scheduler of FIG. 1;

FIG. 4 is a diagram illustrating 64-bit keywords applied to keyword registers of FIG. 3 in order.

* Description of the symbols for the main parts of the drawings *

10: scrambled data buffer 20: PSI control word buffer

30: stream decipher 40: key scheduler

40-1, 40-2, 40-3, 40-4: switch matrix

Keyword registers: 41, 41-1, 41-2, 41-3, 41-4, 41-5, 41-6

50: B0 intermediate buffer 60: B1 intermediate buffer

70: B0 block decipher 80: B1 block decipher

90: descrambled data buffer XOR: exclusive OR circuit

MUX1, MUX2, MUX3: Multiplexer

An apparatus for descrambling a digital broadcast signal according to the present invention includes a buffer for storing temporarily stored scrambled data and PSI control words; A stream decipher for descrambling the scrambled data into 32 clocks by 8 bytes according to a common clock signal, and alternately storing the result in the B0 and B1 intermediate buffers; The B0 and B1 block decodes which receive the start signal from the stream decipher and load data from the corresponding intermediate buffer into its internal register and load one keyword per clock to generate descrambled data with 56 clocks of 8 bytes. Cyphers; A key scheduler for providing internal keywords related to control words to the B0 and B1 block deciphers; An exclusive OR circuit for calculating and outputting the descrambling data of the BO and B1 intermediate buffers and the descramble data of the B0 and B1 block deciphers with an exclusive OR; It consists of a descrambled data buffer for temporarily storing the operation data of the exclusive OR circuit and the previous scrambled data.

Hereinafter, a preferred embodiment of a descrambling apparatus for digital broadcast signal according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an apparatus for descrambling a digital broadcast signal according to the present invention, and FIG. 2 is an operation timing chart of a stream decipher and a block decipher of FIG. 1.

Referring to FIG. 1, the apparatus for descrambling a digital broadcast signal according to an embodiment of the present invention includes a scrambled data buffer 10 and a PSI control word buffer 20 for outputting temporarily stored scrambled data and a PSI control word, respectively. The stream decipher 30, which alternately stores the result in the B0 and B1 intermediate buffers 50 and 60, descrambling to 32 clocks by 8 bytes according to the clock signal, and the start signal from the stream decipher 30. B0 and B1 block deciphers (70) and (80) which receive data from the intermediate buffer and load data into their internal registers and load one keyword per clock to generate descrambled data with 56 clocks of 8 bytes. And a key scheduler 40 providing internal keywords to the B0 and B1 block deciphers 70 and 80, the descrambling data of the BO and B1 intermediate buffers 50 and 60, and the B0 and B1 block deciphers. An exclusive OR circuit for calculating and outputting the descrambled data of the wipers 70 and 80 as an exclusive OR, and a descramble data buffer for temporarily storing the operation data of the exclusive OR circuit and the previous scrambled data. It consists of 90.

The scrambled data buffer 10 and the PSI control word buffer 20, the stream decipher 30, the B0 and B1 block deciphers 70 and 80, the key scheduler 40, and an exclusive OR circuit. (XOR) and the descramble data buffer 90 are sequentially connected in a pipelined manner.

In addition, the deciphering data of the B0 and B1 block deciphers 70 and 80 and the descrambling data of the B0 and B1 intermediate buffers 50 and 60 are respectively controlled by the first and second multiplexers MUX1 and MUX2. The multiplexing is applied to the exclusive OR circuit XOR, and the output of the exclusive OR circuit XOR is multiplexed through the scrambled data and the third multiplexer MUX3 and output.

The operation of the descrambling apparatus for the digital broadcast signal having the above configuration is as follows.

Referring to FIG. 2A, the stream decipher 30 starts deciphering when all the data arrives in the scrambled data buffer. If the data to be descrambled in one packet is 8 bytes or less, this data is transferred directly to the descramble data buffer 90 and enters the descrambling of the next packet.

However, if the data to be descrambled is 8 bytes or more, the stream decipher 30 descrambles the data by 8 bytes, and the result is alternately stored in the B0 intermediate buffer 50 and the B1 intermediate buffer 60 and simultaneously stored. The operations of the B0 and B1 block deciphers 70 and 80 are executed.

One packet is processed like this by 8 bytes.

If the last remaining data is less than 8 bytes, one packet data processing is completed in the stage of the stream decipher 30 as shown in (b) of FIG. 2 without block deciphering.

Therefore, in this case, first wait for the end of block deciphering of 8-byte data, and they are all rearranged in order of the data processed in the descrambled data buffer. If the end is 8 bytes, the processing is the same as the previous 8 bytes, and this is when the data throughput is the highest (see the timing chart shown in Fig. 2A). Here, 8 bytes of stream deciphering requires 32 x 1 clock (one step).

When the next B0 and B1 block deciphers 70 and 80 receive a start signal from the stream decipher 30, they load data from the corresponding B0 and B1 intermediate buffers 50 and 60 into their internal registers and clock one clock. The descrambling operation is performed by loading one keyword at a time.

When the descrambling data is generated after 56 clocks, this data and the data in the intermediate buffer of the other block decipher are multiplexed through the first and second multiplexers MUX1 and MUX2, and then an exclusive OR circuit (XOR). It is computed by the control unit and if multiplexed again through the third multiplexer (MUX3), finally descrambled data is output.

2 shows the operation timings of a stream decipher and two block deciphers.

2A corresponds to the case where one packet is a multiple of 8 bytes, and the data throughput of the descrambling apparatus is consistent with the data throughput of the stream decipher without data delay.

In FIG. 2B, when the end is less than 8 bytes, a data delay occurs until the start of the next packet.

Meanwhile, the key scheduler 40 receives a control word as shown in FIG. 4 and generates a 56 byte keyword.

The key scheduler 40 includes a plurality of keyword registers 41, 41-1, 41-2, 41-3, 41-4, 41-5, 41-6, and switch matrices 40-1, 40-2, 40-3, 40-4, 40-5, 40-6, and the switch matrices 40-1, 40-2, 40-3, 40-4, 40-5, 40-6 If the keywords of [55:48], [47:40], [39:32], [31:24], [23:16], [15: 8], and [7: 0] are applied, respectively, the PSI control The word is converted into a key word in 6 steps.

The control words change periodically, and a new keyword must be generated at this time. When this time is long, the operation of the block decipher shown in FIG. 1 is delayed.

Therefore, the control words applied to the key scheduler 40 take 512 steps to generate 56 keywords according to the original algorithm. If the algorithm itself for the generation of these keywords is parallelized, as shown in FIG. 4. However, by completing the key scheduling operation in 6 steps, the deciphering can be performed in real time with little effect on the data throughput of the deciphers.

As described above in detail, the apparatus for descrambling the digital broadcast signal according to the present invention has the following effects.

First, the present invention conforms to the above common scrambling specification and has a data throughput rate that satisfies the data transfer rate of DVB of 40 Mbps or more.

Second, in the present invention, since the descrambling elements are connected in a pipelined manner, the logical structure of the hardware is simple and the logical division is well performed so as to be suitable for the descrambling data processing.

Claims (3)

Buffers for outputting temporarily stored scrambled data and a PSI control word; A stream decipher for descrambling the scrambled data according to a common clock signal and alternately storing the scrambled data in an intermediate buffer; A block decipher receiving the start signal from the stream decipher and loading data from the corresponding intermediate buffer into its internal register and loading the keyword by one keyword in one clock to generate descrambled data; A key scheduler for providing an internal keyword associated with a PSI control word to the block decipher; An exclusive OR circuit for calculating and outputting the descrambling data of the intermediate buffer and the descrambling data of the block decipher with an exclusive OR; And a descramble data buffer for temporarily storing the operation data of the exclusive logical sum circuit and the previous scrambled data. The apparatus of claim 1, wherein the buffers, the stream decipher, the block decipher, the key scheduler, and the exclusive OR circuit are connected in a pipelined manner. The method according to claim 1, wherein the key scheduler is composed of a plurality of keyword registers and a switch matrix, wherein [55:48], [47:40], [39:32], [31:24] are respectively assigned to the switch matrices. , [23:16], [15: 8], and [7: 0] are applied, the PSI data descrambling apparatus for digital broadcast signals, characterized in that key scheduling is performed in six steps.

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