KR100226867B1 - Stream cipher system of wireless communication - Google Patents

Abstract

The stream cipher system of wireless communication is to implement the stream cipher system as a plurality of nonlinear combining functions by integrating the conventional block cipher system and the stream cipher system, and outputs a secret key input based on an internal linear function. A first linear feedback register unit, a seed vector generator for generating an encrypted seed vector, a logic operation unit for performing a logic operation on a signal and a seed vector of the first linear feedback register unit, and outputting a resultant signal; And a nonlinear function unit for storing a signal of the logical operation unit and calculating and outputting the stored data according to a nonlinear function, and temporarily dividing the signal of the nonlinear function unit into blocks having a predetermined length and temporarily storing the temporarily stored block. Block encryption unit that outputs key stream by performing (DES) algorithm To have its base.

Description

Stream cipher system of wireless communication

The present invention relates to wireless communications, and more particularly to a stream cipher system for wireless communications.

The block cipher is expressed by Equation 1 below by dividing the plaintext P to be encrypted into block units P1, P2, ... having the same length and encrypting and decoding each Pi with the same key.

Ek (P) = Ek (P1) Ek (P2) ...

The stream cipher is a cipher system using a binary sequence generator using a shift register, and can be divided into a synchronous stream cipher and a self-synchronous stream cipher according to a key stream generation method.

The synchronous stream cipher stream cipher is a cipher in which the key stream is generated independently of the plaintext stream. The self-synchronous stream cipher cipher is a cipher in which the key stream is generated depending on the previous ciphertext stream. That's the way.

Hereinafter, a block cipher system for wireless communication according to the prior art will be described with reference to the accompanying drawings.

1 is a block diagram of a block cipher system for wireless communication according to the prior art, in which a block former unit 1 for dividing a serial input (P) to be encrypted into blocks having the same length and outputting the same; And an encryption unit (2) which encrypts and outputs the block statements (block input: P1, P2, ...) of the block former unit 1 through an encryption algorithm according to a secret key input. ), The block output unit 3 for outputting the cipher text of the encryption unit 2, and the original plain text by decrypting the cipher text output from the block output unit 3 through the reverse process of the encryption process. It consists of the decoding part 4 which extracts: P).

The block cipher system for wireless communication according to the prior art configured as described above will be described in detail with reference to the accompanying drawings.

First, the block former unit 1 divides a serial input (P) to be encrypted into blocks having the same length and outputs a plurality of block inputs (P1, P2, ...). do.

Then, the encryption unit 2 encrypts a plurality of block statements (block input P1, P2, ...) of the block former unit 1 through an encryption algorithm according to a secret key input. Output ciphertext {Ek (P1) (P2) ...}.

In this case, the secret key may be fixed or externally changed.

As a result, the block output section 3 outputs the cipher text {Zk (P1) (P2) ...} of the encryption section 2.

Then, the decryption unit 4 decrypts the ciphertext {Ek (P1) (P2) ...} outputted from the block output unit 3 through the reverse process of the encryption process of the encryption unit 2 and decrypts the original text. Extract the serial input (P).

When the block size of the plaintext and ciphertext of the plaintext and ciphertext is m bits, the number of cipher conversions that correspond to one ciphertext block to the plaintext block is 2 ⁿ ! Cases, so the total number of keys 2 ⁿ ! , The maximum size of a key log2 ⁿ ! Bit.

If the block size is small, a pair of plaintext and ciphertext blocks corresponding to a given secret key can be stored in the storage device.

FIG. 2 is a block diagram of a stream cipher system for wireless communication according to the prior art, and includes a first logic unit for outputting an encryption signal through an encryption algorithm according to a seed vector and a key input. 10), the first mixing unit 20 for outputting the cipher text by calculating the encryption signal and the plain text P of the first logic unit 10, and the channel for transmitting the cipher text of the first mixing unit 20 A second logic unit 40 which outputs a decryption signal through a decryption algorithm according to the seed vector and the seed vector and the secret key, and the decryption of the second logic unit 40. It consists of a second mixing unit 50 for extracting the original plain text (P) by calculating the cipher text transmitted through the signal and the channel unit 30.

The block cipher system for wireless communication according to the prior art configured as described above will be described in detail with reference to the accompanying drawings.

First, the first logic unit 10 outputs an encryption signal through an encryption algorithm according to a seed vector (Seed Vecter) and a secret key (K) input of a binary sequence generator (not shown).

Here, the seed vector (Seed Vecter) and the secret key (K) may be fixed or externally changed.

Then, the first mixing unit 20 calculates the encrypted signal of the first logic unit 10 and the plain text P to output the cipher text C.

That is, the first mixing unit 20 outputs the ciphertext C by exclusively ORing the encrypted signal of the first logic unit 10 and the plain text P.

The cipher text of the first mixing unit 20 is transmitted through the channel unit 30.

Meanwhile, the second logic unit 40 outputs a decryption signal through a decryption algorithm according to the seed vector and the secret key.

Here, the seed vector (Seed Vecter) and the secret key (Key) input to the first and second logic units 10 and 40 are the same.

Accordingly, the second mixing unit 50 extracts the original plain text P by calculating the decrypted signal of the second logic unit 40 and the cipher text transmitted through the channel unit 30.

The stream cipher may be divided into a synchronous (synchromous stream cipher) and a self-synchronous stream cipher according to the key stream generation method.

Here, the key stream in the synchronous manner is generated independently of the stream.

Therefore, the generation algorithm must be determined in advance in order to generate the same key stream at the transmitting side and the receiving side.

In contrast, the self-synchronizing stream cipher system is a cipher system in which the key stream is generated depending on the previous ciphertext stream.

In this method, if one bit of ciphertext is changed or disappeared during transmission, the error is propagated to the next one bit, and then the correct ciphertext is automatically synchronized and the correct decryption is performed when the correct ciphertext arrives by one bit.

This one bit transmission error is called self-synchronous because it affects only one next bit.

However, the block cipher according to the related art has excellent spreading effect because the information of the plaintext P is distributed among several symbols of the ciphertext, but there is a problem that the insertion or removal of the symbol is impossible because the length of the block is determined.

In addition, since the linguistic characteristics of the plain text are likely to be represented by the frequency of appearance of the character, which is a statistical feature of the ciphertext block, there is a risk of being deciphered by the analysis by the frequency of occurrence of the character.

On the other hand, if a bit of a ciphertext disappears during transmission, the stream cipher is out of sync with all ciphertexts after that bit and an error propagates.

Therefore, in order to synchronize, there is a problem in that the sender and the receiver must generate a key stream from the new initial value again in accordance with the protocol of the encryption communication start.

Accordingly, the present invention has been made to solve the above problems, and provides a stream encryption system for wireless communication to integrate the conventional block cipher system and the stream cipher system to implement the stream cipher system as a plurality of nonlinear combining functions. The purpose is.

1-block diagram of a wireless communication block encryption system according to the prior art

2-block diagram of a wireless communication stream encryption system according to the prior art

3 is a block diagram of a wireless communication stream encryption system according to the present invention.

4-3 is a detailed block diagram of the block encryption unit of FIG.

Explanation of symbols for main parts of the drawings

110: first linear feedback register section 120: seed vector generator

130: logical operation unit 140: nonlinear function unit

150: block encryption unit 151: temporary storage unit

151: DES algorithm unit 153: second linear feedback register unit

153a: Linear Feedback Register 153b: Mixer

A feature of the stream encryption system for wireless communication according to the present invention for achieving the above object is a first linear feedback register unit for calculating and outputting a secret key (Key) input according to a linear function, and an encrypted seed vector ( A seed vector generator for generating a Seed Vecter, a logic operator for performing a logic operation on the signal and the seed vector of the first linear feedback register, and outputting a result signal, and storing the signal of the logic operator and non-linearly storing the stored data. A non-linear function unit for calculating and outputting a function according to a function, and dividing the signal of the non-linear function unit into blocks having a predetermined length to temporarily store the block, and outputting a key stream by performing a data sign standard (DES) algorithm. It consists of including wealth.

Hereinafter, a stream cipher system for wireless communication according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of a stream cipher system for wireless communication according to the present invention, including a first linear feedback register unit 110 for calculating a secret key input according to a linear function and outputting the encrypted seed vector. A seed vector generator 120 for generating a seed vect, a logic operator 130 for performing a logic operation on the signal and the seed vector of the first linear feedback register unit 110, and outputting a resultant signal; The nonlinear function unit 140 stores the signal of the operation unit 130 and calculates and outputs the stored data according to the nonlinear function, and temporarily stores the signal of the nonlinear function unit 140 by dividing the signal of the nonlinear function unit into blocks having a predetermined length. The block encryption unit 150 outputs a key stream by performing a data sign standard (DES) algorithm on the temporarily stored block.

4 is a detailed block diagram of the block encryption unit of FIG. 3, wherein the block encryption unit 150 divides the signal of the nonlinear function unit 140 into a predetermined unit and temporarily stores the temporary storage unit 151. A data sign standard (DES) algorithm unit 152 which performs a data sign standard (DES) algorithm on the signal of the storage unit 151 according to a secret key input, and outputs a signal as a result, and the data sign standard ( DES) second linear feedback register section 153 which shifts and outputs the signal of the algorithm section 152 and feeds back the output signal.

The second linear feedback register unit 153 shifts a signal of the data code standard (DES) algorithm unit 152 to output a key stream and receives a logically calculated data, and the linear feedback register 153a. And a mixer 153b which feeds back the signal output from the feedback register 153a and performs a logical operation to input the resultant data into the linear feedback register 153a.

The operation of the stream encryption system for wireless communication according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the first linear feedback register unit 110 calculates and outputs a secret key input according to an internal linear function.

The seed vector generator 120 generates an encrypted seed vector.

The secret key is an initial value of the linear feedback register unit 110 and the seed vector generator 120.

In addition, the plurality of linear feedback registers 110a to 110n in the linear feedback register unit 110 are configured with an M-sequence having a maximum period.

If the length of the plurality of linear feedback registers 110a to 110n in the linear feedback register section 110 is L, the period T is 2 ^L −1.

In addition, the linear feedback register unit 110 has a small order of primitive polynomials constituting a plurality of linear feedback registers 110a to 110n so as to maximize the period of the output sequence output from the nonlinear function unit 140. To be.

For example, if the plurality of linear feedback registers 110a to 110n is six, the primitive polynomials of the linear feedback registers 110a to 110f are represented by Equations 2 to 7, respectively.

X ⁴³ + X ⁶ + X ⁵ + X + 1

X ⁴⁶ + X ⁸ + X ⁵ + X ³ + X ² + X + 1

X ⁵³ + X ¹⁶ + X ¹⁵ + X + 1

X ⁵⁷ + X ⁵ + X ³ + X ² +1

X ⁵⁹ + X ⁶ + X ⁵ + X ⁴ + X ³ + X + 1

X ⁶¹ + X ¹⁶ + X ¹⁵ +1

The number of stages of the seed vector generator 120 is equal to the number of linear feedback registers 110a to 110n in the linear feedback register unit 110.

Accordingly, the logic operation unit 130 performs a logic operation on the signal and the seed vector of the first linear feedback register unit 110 and outputs the resultant signal.

In other words, the plurality of exclusive OR gates 130a to 130n in the logic operation unit 130 may generate signals from the linear feedback registers 110a to 110n in the linear feedback register unit 110 and the seed vectors of the seed vector generator 120. Outputs the result of an exclusive OR.

For example, the exclusive OR gate 130i in the logic operator 130 outputs an exclusive OR by one bit with the signals of the i-th bit and the i-th linear feedback register 110i of the seed vector generator 120. do.

Then, the nonlinear function unit 140 stores the signal of the logical operation unit 130 and calculates and outputs the stored data according to the nonlinear function.

Accordingly, the block encryption unit 150 divides the signal of the nonlinear function unit 140 into blocks of a predetermined length and temporarily stores the signal. The block encryption unit 150 outputs a key stream by performing a data sign standard (DES) algorithm.

That is, the temporary storage unit 151 in the block encryption unit 150 divides the signal of the nonlinear function unit 140 into a predetermined unit and temporarily stores the signal.

Then, the data sign standard (DES) algorithm unit 152 performs the data sign standard (DES) algorithm on the signal of the temporary storage unit 151 according to a secret key input, and outputs the result signal.

That is, the DES algorithm 152 divides the 64-bit signal of the temporary storage unit 151 into left and right (L, R) bits by 32 bits, and L-bit of 32 bits is an encryption function and modulo made of the first key value. -2 operation is stored in R of the next step, 32-bit R is stored in the next L after the encryption function and mldulo-2 operation, and this iteration process is repeated 16 times.

The encryption function used every time in the DES algorithm unit 152 is a 32-bit R is extended to 48 bits by the expansion box, L is also extended to 48 bits by the expansion box in the key value consisting of 64-bit supplied from the outside 56 bits minus 8-bit parity bits perform a simple shift and bit selection to perform a 48-bit key and modulo-2 operation, resulting in 32 bits by substitution.

After the encryption of one block is finished, the data sign standard (DES) algorithm unit 152 outputs the output as the initial values of 64 shift registers, and also stores the value of the second key. Used as the value of the second key.

Accordingly, the second linear feedback register unit 153 shifts and outputs the signal of the data code standard (DES) algorithm unit 152, feeds back the output signal, and performs a logical operation to output a key stream.

Here, the second linear feedback register section 153 is composed of 64 memories and stores the signal of the data sign standard (DES) algorithm section 152 as an initial value and generates a stream until the next output.

That is, the linear feedback register 153a in the second linear feedback register section 153 shifts the signal of the data sign standard (DES) algorithm section 152 to output a key stream.

Then, the mixer 153b feeds back the logic output from the linear feedback register 153a to perform a logical operation, and inputs the resultant signal to the linear feedback register 153a.

That is, the mixer 153b feeds back the signal output from the linear feedback register 153a and performs exclusive OR on the signal of the linear feedback register 153a and inputs it to the linear feedback register 153a.

As described above, the stream cipher system of the wireless communication according to the present invention integrates the block cipher system and the stream cipher system according to the prior art and implements the stream cipher system as a plurality of nonlinear combining functions, thereby preventing individuals from illegal intruders in the mobile communication system. There is an effect that can protect the information of and to protect the information transmitted on the wireless channel.

In addition, the present invention has the advantage of increasing the strength of the stream cipher generator using a data coding standard (DES) algorithm.

Claims (6)

A first linear feedback register unit for calculating and outputting a secret key input according to a linear function; A seed vector generator for generating an encrypted seed vector; A logic operation unit configured to perform a logic operation on the signal and the seed vector of the first linear feedback register unit, and output a resultant signal; A nonlinear function unit which stores a signal of the logical operation unit and calculates and outputs the stored data according to a nonlinear function; And a block encryption unit for dividing the signal of the nonlinear function unit into a block of a predetermined length for temporary storage and outputting a key stream by performing a data coding standard (DES) algorithm. Password system. The method of claim 1, And the order of the primitive polynomials of each of the first linear feedback registers is small with each other. The method of claim 1, And the logical operation unit comprises a plurality of exclusive OR gates. The method of claim 1, The block encryption unit temporarily stores the non-linear function unit by dividing the signal by a predetermined unit; A DES algorithm for outputting a signal by performing a data code standard (DES) algorithm on the signal of the temporary storage unit according to a secret key input; And a second linear feedback register unit for shifting and outputting the signal of the DES algorithm unit and feeding back and outputting the output signal. The method of claim 4, wherein And the temporary storage unit is a plurality of 64-bit buffers. The method of claim 4, wherein The second linear feedback register unit includes a linear feedback register configured to shift a signal of the DES algorithm unit, output a key stream, and receive a logically calculated signal; And a mixer for feeding back a signal output from the linear feedback register and performing a logical operation to input the result signal into the linear feedback register.

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