KR100220244B1 - 솔더 범프를 이용한 스택 패키지 - Google Patents
솔더 범프를 이용한 스택 패키지 Download PDFInfo
- Publication number
- KR100220244B1 KR100220244B1 KR1019960077726A KR19960077726A KR100220244B1 KR 100220244 B1 KR100220244 B1 KR 100220244B1 KR 1019960077726 A KR1019960077726 A KR 1019960077726A KR 19960077726 A KR19960077726 A KR 19960077726A KR 100220244 B1 KR100220244 B1 KR 100220244B1
- Authority
- KR
- South Korea
- Prior art keywords
- lead frame
- solder bumps
- stack package
- lead
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (7)
- 각각의 본드 패드가 형성된 면이 서로 마주하도록 배열된 제1 및 제2반도체 칩과, 상기 각각의 본드 패드에 형성된 솔더 범프와, 상기 각각의 본드 패드에 형성된 솔더 범프의 측면에 접속되어 상기 칩의 외부와의 전기적 신호 경로를 이루는 제1 및 제2리드 프레임, 상기 제1반도체 칩과 제1리드 프레임, 제2반도체 칩과 제2리드 프레임 및 제1리드 프레임과 제2리드 프레임을 접착시키기 위한 접착 테이프, 상기 제1 및 제2반도체 칩과 제1 및 제2리드 프레임을 포함하는 일정면적을 밀봉하도록 성형된 패키지 몸체를 포함하는 것을 특징으로 하는 솔더 범프를 이용한 스택 패키지.
- 제1항에 있어서, 상기 리드 프레임은 그의 인너 리드의 끝단부가 솔더 범프와의 접촉면적이 증대되도록 라운드형으로 되어 있는 것을 특징으로 하는 솔더 범프를 이용한 스택 패키지.
- 제2항에 있어서, 상기 인너 리드의 라운드형의 끝단부에는 솔더 범프와의 전기적 접속을 위해 솔더가 플래팅되어 있는 것을 특징으로 하는 솔더 범프를 이용한 스택 패키지.
- 제1항에 있어서, 상기 접착 테이프는 제1 및 제2 LOC 테이프로 이루어진 것을 특징으로 하는 솔더 범프를 이용한 스택 패키지.
- 제4항에 있어서, 상기 제1 및 제2 LOC 테이프는 약 50㎛이하의 두께로 하는 것을 특징으로 하는 솔더 범프를 이용한 스택 패키지.
- 제4항에 있어서, 상기 제1 LOC 테이프는 제1칩과 제1리드 프레임 및 제2칩과 제2리드 프레임을 부착시키기 위하여 사용하는 것을 특징으로 하는 솔더 범프를 이용한 스택 패키지.
- 제6항에 있어서, 상기 제2 LOC 테이프는 제1 및 제2리드 프레임을 접착시키기 위하여 사용하는 것을 특징으로 하는 솔더 범프를 이용한 스택 패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960077726A KR100220244B1 (ko) | 1996-12-30 | 1996-12-30 | 솔더 범프를 이용한 스택 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960077726A KR100220244B1 (ko) | 1996-12-30 | 1996-12-30 | 솔더 범프를 이용한 스택 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR19980058402A KR19980058402A (ko) | 1998-10-07 |
KR100220244B1 true KR100220244B1 (ko) | 1999-09-15 |
Family
ID=19492668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960077726A Expired - Fee Related KR100220244B1 (ko) | 1996-12-30 | 1996-12-30 | 솔더 범프를 이용한 스택 패키지 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100220244B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101013545B1 (ko) * | 2007-07-26 | 2011-02-14 | 주식회사 하이닉스반도체 | 스택 패키지 및 그의 제조방법 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100587024B1 (ko) * | 1998-12-24 | 2007-12-12 | 주식회사 하이닉스반도체 | 3차원 적층형 마이크로 비지에이 패키지 |
KR100778912B1 (ko) * | 2001-03-28 | 2007-11-22 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그의 제조방법 |
CN113823606A (zh) * | 2021-08-12 | 2021-12-21 | 紫光宏茂微电子(上海)有限公司 | 芯片堆叠封装结构及其制作方法 |
-
1996
- 1996-12-30 KR KR1019960077726A patent/KR100220244B1/ko not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101013545B1 (ko) * | 2007-07-26 | 2011-02-14 | 주식회사 하이닉스반도체 | 스택 패키지 및 그의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR19980058402A (ko) | 1998-10-07 |
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