KR100219565B1 - Method for fabricating capacitor of semiconductor device - Google Patents
Method for fabricating capacitor of semiconductor device Download PDFInfo
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- KR100219565B1 KR100219565B1 KR1019960052177A KR19960052177A KR100219565B1 KR 100219565 B1 KR100219565 B1 KR 100219565B1 KR 1019960052177 A KR1019960052177 A KR 1019960052177A KR 19960052177 A KR19960052177 A KR 19960052177A KR 100219565 B1 KR100219565 B1 KR 100219565B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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Abstract
반도체소자의 커패시터 제조방법이 개시되어 있다. 이 방법은 반도체기판 상에 층간절연막을 형성하는 단계와, 층간절연막을 패터닝하여 반도체기판의 소정영역을 노출시키는 콘택홀을 형성하는 단계와, 콘택홀 내부를 채우는 플러그 패턴을 형성하는 단계와, 플러그 패턴 상에 순차적으로 적층된 장벽금속막 패턴, 산소 확산방지막 패턴, 내산화성 금속막 패턴을 형성함으로써, 플러그 패턴, 장벽금속막 패턴, 산소 확산방지막 패턴, 및 내산화성 금속막 패턴으로 구성된 스토리지 전극을 형성하는 단계와, 스토리지 전극이 형성된 결과물 전면에 절연막을 제1 두께로 형성하는 단계와, 내산화성 금속막 패턴 상의 두께가 제1 두께보다 얇은 제2 두께가 되도록 제1 두께의 절연막을 CMP 공정으로 연마하여 표면단차가 완화된 절연막을 형성하는 단계와, 내산화성 금속막 패턴이 노출될 때까지 표면단차가 완화된 절연막을 전면 에치 백 함으로써, 스토리지 전극 사이에 장벽금속막 패턴의 측벽을 완전히 덮는 절연막 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다. 이에 따라, 고유전막을 형성하는 후속공정시 장벽금속막 패턴이 산화되는 현상을 방지할 수 있으므로 고집적 반도체소자에 적합한 커패시터를 구현할 수 있다.Disclosed is a method of manufacturing a capacitor of a semiconductor device. The method comprises the steps of forming an interlayer insulating film on a semiconductor substrate, patterning the interlayer insulating film to form a contact hole exposing a predetermined region of the semiconductor substrate, forming a plug pattern filling the inside of the contact hole, and By forming a barrier metal layer pattern, an oxygen diffusion barrier layer, and an oxidation resistant metal layer pattern sequentially stacked on the pattern, a storage electrode including a plug pattern, a barrier metal layer pattern, an oxygen diffusion barrier layer pattern, and an oxidation resistant metal layer pattern is formed. Forming an insulating film on the entire surface of the resultant on which the storage electrode is formed; Polishing to form an insulating film having a reduced surface step, and the surface step is completed until the oxide resistant metal film pattern is exposed. Etching the entire insulating film to form an insulating film pattern completely covering sidewalls of the barrier metal film pattern between the storage electrodes. As a result, the oxidation of the barrier metal layer pattern may be prevented in a subsequent process of forming the high dielectric layer, thereby implementing a capacitor suitable for a highly integrated semiconductor device.
Description
본 발명은 반도체소자의 커패시터 제조방법에 관한 것으로, 특히 스토리지 전극에 장벽금속막을 사용하는 커패시터 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor using a barrier metal film for a storage electrode.
반도체소자 중에 정보를 기억시키거나 기억된 정보를 읽어낼 수 있는 반도체 기억소자는 컴퓨터 등에 널리 사용된다. 이와 같은 반도체 기억소자에는 여러 가지의 종류가 있으며, 그들 중에 대표적인 것으로 DRAM 소자를 들 수 있다. 이러한 DRAM 소자는 하나의 기억 셀이 하나의 커패시터와 하나의 트랜지스터로 구성된다. 여기서, 상기 커패시터는 정보를 저장시키는 수단으로 사용되므로 DRAM 소자에 있어서 매우 중요한 역할을 한다. 이는, 커패시터의 특성, 즉 커패시턴스가 셀 특성과 직접적으로 관련이 있기 때문이다. 다시 말해서, DRAM 소자의 저전압 특성 및 ??-입자에 의한 소프트 에러 현상은 커패시턴스가 작을수록 악화되기 때문이다.BACKGROUND OF THE INVENTION A semiconductor memory device capable of storing information or reading stored information in a semiconductor device is widely used in a computer and the like. There are various kinds of such semiconductor memory devices, and a DRAM device is a representative one of them. In such a DRAM device, one memory cell is composed of one capacitor and one transistor. Here, the capacitor plays a very important role in the DRAM device because it is used as a means for storing information. This is because the characteristics of the capacitor, that is, the capacitance, are directly related to the cell characteristics. In other words, the low voltage characteristics of the DRAM element and the soft error due to ??-particles are worse because the smaller the capacitance.
한편, DRAM 소자의 집적도가 증가할수록 커패시터가 차지하는 면적은 점점 감소하므로 커패시턴스 또한 감소하는 경향이 있다. 따라서, 고성능 DRAM 소자를 제작하기 위해서는 제한된 면적 내에 커패시턴스가 큰 커패시터를 제작하여야 한다. 이와 같이 고집적 DRAM 소자에 적합하도록 제한된 면적 내에 고용량의 커패시터를 제작하는 방법으로는 1)하부전극(스토리지 전극)이 3차원적인 구조를 갖도록 형성하여 그 표면적을 증가시키는 방법과, 2)유전상수가 큰 고유전막을 사용하는 방법을 들 수 있다. 여기서, 고유전막으로는 유전상수가 수 백 정도의 값을 갖는 BST(BaStTiO3)막 또는 PZT(PbZrTiO3)막 등이 널리 사용되고 있다. 그러나, 이러한 고유전막은 수 백 ℃의 고온 및 산소 분위기에서 형성되므로 하부전극의 표면층으로 내산화성 물질막, 예컨대 백금막이 널리 사용된다. 또한, 백금막은 그레인 경계를 통하여 산소원자를 통과시키기 때문에 백금막 및 도우핑된 폴리실리콘막 사이에 산소 확산방지막을 형성하여야 하고, 상기 산소 확산방지막 및 도우핑된 폴리실리콘막 사이에는 상기 내산화성 금속막의 금속 원자가 확산하는 것을 방지하기 위한 장벽금속막을 형성하여야 한다. 이러한 산소 확산방지막으로는 이리디움산화막 및 이리디움막이 적층된 2중막이 널리 사용되며, 장벽금속막으로는 타이타늄질화막이 널리 사용된다.On the other hand, as the integration of DRAM devices increases, the area occupied by the capacitor gradually decreases, so the capacitance also tends to decrease. Therefore, in order to manufacture a high performance DRAM device, a capacitor having a large capacitance within a limited area must be manufactured. As such a method of manufacturing a high-capacity capacitor in a limited area to be suitable for high-density DRAM devices, 1) forming a lower electrode (storage electrode) to have a three-dimensional structure to increase its surface area, and 2) dielectric constant The method of using a large high dielectric film is mentioned. Here, as the high dielectric film, a BST (BaStTiO 3) film or a PZT (PbZrTiO 3) film having a dielectric constant of about several hundreds is widely used. However, since the high dielectric film is formed at a high temperature and oxygen atmosphere of several hundred degrees Celsius, an oxidizing material film such as a platinum film is widely used as the surface layer of the lower electrode. In addition, since the platinum film passes oxygen atoms through the grain boundary, an oxygen diffusion barrier must be formed between the platinum film and the doped polysilicon layer, and the oxide resistant metal is interposed between the oxygen diffusion barrier layer and the doped polysilicon layer. A barrier metal film should be formed to prevent the metal atoms of the film from diffusing. As the oxygen diffusion preventing film, a double film in which an iridium oxide film and an iridium film are laminated is widely used, and a titanium nitride film is widely used as a barrier metal film.
도 1 내지 도 3은 종래의 커패시터 제조방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a conventional capacitor manufacturing method.
도 1을 참조하면, 활성영역이 형성된 반도체기판(1) 상에 층간절연막을 형성하고, 상기 층간절연막을 패터닝하여 활성영역의 소정영역을 노출시키는 콘택홀을 구비하는 층간절연막 패턴(3)을 형성한다. 이어서, 상기 콘택홀 내에 도우핑된 폴리실리콘막으로 활성영역과 접촉하는 플러그 패턴(5)을 형성한다.Referring to FIG. 1, an interlayer insulating film is formed on a semiconductor substrate 1 on which an active region is formed, and an interlayer insulating layer pattern 3 having contact holes exposing a predetermined region of the active region is formed by patterning the interlayer insulating layer. do. Subsequently, a plug pattern 5 is formed in contact with the active region with a polysilicon layer doped in the contact hole.
도 2는 스토리지 전극 및 절연막(15)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로 설명하면, 상기 플러그 패턴(5)이 형성된 결과물 전면에 장벽금속막인 타이타늄질화막, 이리디움막 및 이리디움 산화막이 차례로 적층된 산소확산 방지막, 및 백금막을 순차적으로 형성한다. 이어서, 상기 백금막, 산소확산 방지막, 및 타이타늄 질화막을 연속적으로 패터닝하여 상기 플러그 패턴(5)을 덮으면서 차례로 적층된 타이타늄 질화막 패턴(7), 이리디움막 패턴(9), 이리디움 산화막 패턴(11), 및 백금막 패턴(13)을 형성한다. 여기서, 상기 플러그 패턴(5), 타이타늄 질화막 패턴(7), 이리디움막 패턴(9), 이리디움 산화막 패턴(11), 및 백금막 패턴(13)은 스토리지 전극을 구성한다. 다음에, 상기 결과물 전면에 소정의 두께를 갖는 절연막(15), 예컨대 CVD 산화막을 형성한다. 이때, 도시된 바와 같이 상기 절연막(15)의 표면은 상기 스토리지 전극 사이의 요부로 인하여 참조부호 H로 표시한 표면단차를 갖는다. 여기서, 상기 절연막(15)을 형성하는 이유는 후속공정에서 상기 스토리지 전극을 구성하는 장벽금속막 패턴의 측벽, 즉 타이타늄 질화막 패턴(7)의 측벽이 노출되는 것을 방지하기 위한 스페이서를 형성하기 위함이다.2 is a cross-sectional view for describing a step of forming the storage electrode and the insulating layer 15. Specifically, an oxygen diffusion prevention film in which a titanium nitride film, an iridium film, and an iridium oxide film, which are barrier metal films, are sequentially formed on the entire surface of the resultant product on which the plug pattern 5 is formed, and a platinum film are sequentially formed. Subsequently, the platinum film, the oxygen diffusion prevention film, and the titanium nitride film are successively patterned to cover the plug pattern 5, and the titanium nitride film pattern 7, the iridium film pattern 9, and the iridium oxide film pattern (sequentially stacked) 11) and the platinum film pattern 13 are formed. The plug pattern 5, the titanium nitride layer pattern 7, the iridium layer pattern 9, the iridium oxide layer pattern 11, and the platinum layer pattern 13 constitute a storage electrode. Next, an insulating film 15 having a predetermined thickness, for example, a CVD oxide film, is formed on the entire surface of the resultant product. At this time, as shown in the drawing, the surface of the insulating film 15 has a surface step indicated by reference numeral H due to the recessed portion between the storage electrodes. The reason for forming the insulating film 15 is to form a spacer for preventing the sidewall of the barrier metal film pattern constituting the storage electrode, that is, the sidewall of the titanium nitride film pattern 7, from being exposed in a subsequent process. .
도 3은 절연막 패턴(15a), 즉 스페이서를 형성하는 단계를 설명하기 위한 단면도이다. 상세히 설명하면, 상기 백금막 패턴(13)이 노출될 때까지 상기 절연막(15)을 전면 에치백하여 상기 스토리지 전극 사이에 절연막 패턴(15a)을 형성한다. 이때, 도시된 바와 같이 절연막 패턴(15a)은 타이타늄 질화막 패턴(7)의 측벽을 완전히 덮지 못하는 형태를 가지며, 이에 따라 타이타늄 질화막 패턴(15a)의 측벽 상부가 노출된다. 이는, 상기 전면 에치백 공정시 절연막(15)의 표면단차(H)에 의해 스토리지 전극 사이의 절연막(15)이 과도하게 식각되어 절연막 패턴(15a)이 매우 작은 형태로 잔존하기 때문이다.3 is a cross-sectional view for explaining a step of forming an insulating film pattern 15a, that is, a spacer. In detail, the insulating layer pattern 15 is entirely etched back until the platinum layer pattern 13 is exposed to form an insulating layer pattern 15a between the storage electrodes. In this case, as illustrated, the insulating layer pattern 15a does not completely cover the sidewalls of the titanium nitride layer pattern 7, and thus the upper portion of the sidewall of the titanium nitride layer pattern 15a is exposed. This is because the insulating film 15 between the storage electrodes is excessively etched by the surface step H of the insulating film 15 during the front etch back process, so that the insulating film pattern 15a remains in a very small form.
이어서 도시하지는 않았지만, 상기 절연막 패턴(15a)이 형성된 결과물 전면에 고유전막인 BST막 또는 PZT막을 형성하고 그 위에 플레이트 전극으로 사용되는 도전막을 형성한다. 이때, 상기 고유전막은 수 백 ℃의 고온 및 산소 분위기에서 형성하므로, 측벽의 일부가 노출된 상기 타이타늄 질화막 패턴(7)이 산화되어 타이타늄 산화막이 형성된다. 이러한 타이타늄 산화막은 타이타늄 질화막 패턴(7)의 저항을 증가시키며, 이에 따라 스토리지 전극의 저항을 증가시킴과 동시에 타이타늄 질화막 패턴(7)의 본래의 기능인 실리콘 확산방지 기능을 상실시킨다.Subsequently, although not shown, a BST film or PZT film, which is a high dielectric film, is formed on the entire surface of the resultant in which the insulating film pattern 15a is formed, and a conductive film used as a plate electrode is formed thereon. In this case, since the high dielectric film is formed at a high temperature and oxygen atmosphere of several hundred degrees Celsius, the titanium nitride film pattern 7 having a portion of the sidewall exposed is oxidized to form a titanium oxide film. Such a titanium oxide film increases the resistance of the titanium nitride film pattern 7, thereby increasing the resistance of the storage electrode and at the same time losing the silicon diffusion preventing function, which is an original function of the titanium nitride film pattern 7.
상술한 바와 같이 종래의 커패시터 제조방법은 고유전막 형성 직전에 장벽금속막인 타이타늄 질화막 패턴의 측벽이 노출된 상태이므로 고유전막 형성 후에 장벽금속막이 산화되어 타이타늄 산화막이 형성된다. 따라서, 스토리지 전극의 저항이 증가하여 커패시터의 특성을 저하시킨다. 또한, 장벽금속막의 기능이 상실되어 스토리지 전극과 연결된 활성영역의 접합면에 금속 원자가 침투하여 스토리지 전극과 반도체기판 사이에 누설전류를 발생시킨다.As described above, in the conventional capacitor manufacturing method, since the sidewall of the titanium nitride film pattern, which is the barrier metal film, is exposed immediately before the high dielectric film is formed, the barrier metal film is oxidized to form a titanium oxide film after the high dielectric film is formed. Thus, the resistance of the storage electrode is increased to degrade the characteristics of the capacitor. In addition, the function of the barrier metal film is lost, and metal atoms penetrate the junction surface of the active region connected to the storage electrode to generate a leakage current between the storage electrode and the semiconductor substrate.
본 발명이 이루고자 하는 기술적 과제는 스토리지 전극 사이에 장벽금속막의 측벽을 완전히 덮는 절연막 패턴을 형성하여 고유전막 형성시 장벽금속막이 산화되는 현상을 방지할 수 있는 반도체소자의 커패시터 제조방법을 제공하는 데 있다.An object of the present invention is to provide a capacitor manufacturing method of a semiconductor device that can prevent the phenomenon of the barrier metal film is oxidized when forming a high dielectric film by forming an insulating film pattern covering the sidewall of the barrier metal film completely between the storage electrodes. .
도 1 내지 도 3은 종래의 커패시터 제조방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a conventional capacitor manufacturing method.
도 4 내지 도 7은 본 발명의 커패시터 제조방법을 설명하기 위한 단면도들이다.4 to 7 are cross-sectional views illustrating a method of manufacturing a capacitor of the present invention.
상기 과제를 이루기 위하여 본 발명에 의한 반도체소자의 커패시터 제조방법은 반도체기판 상에 층간절연막을 형성하는 단계와, 상기 층간절연막을 패터닝하여 상기 반도체기판의 소정영역을 노출시키는 콘택홀을 형성하는 단계와, 상기 콘택홀 내부를 채우는 플러그 패턴을 형성하는 단계와, 상기 플러그 패턴 상에 순차적으로 적층된 장벽금속막 패턴, 산소 확산방지막 패턴, 내산화성 금속막 패턴을 형성함으로써, 상기 플러그 패턴, 상기 장벽금속막 패턴, 상기 산소 확산방지막 패턴, 및 상기 내산화성 금속막 패턴으로 구성된 스토리지 전극을 형성하는 단계와, 상기 스토리지 전극이 형성된 결과물 전면에 절연막을 제1 두께로 형성하는 단계와, 상기 내산화성 금속막 패턴 상의 두께가 상기 제1 두께보다 얇은 제2 두께가 되도록 상기 제1 두께의 절연막을 CMP(Chemical Mechanical Polishing) 공정으로 연마하여 표면단차가 완화된 절연막을 형성하는 단계와, 상기 내산화성 금속막 패턴이 노출될 때까지 상기 표면단차가 완화된 절연막을 전면 에치 백 함으로써, 상기 스토리지 전극 사이에 상기 장벽금속막 패턴의 측벽을 완전히 덮는 절연막 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming an interlayer insulating film on a semiconductor substrate, and forming a contact hole exposing a predetermined region of the semiconductor substrate by patterning the interlayer insulating film; Forming a plug pattern filling the contact hole, and forming a barrier metal layer pattern, an oxygen diffusion barrier layer, and an oxidation resistant metal layer pattern sequentially stacked on the plug pattern, thereby forming the plug pattern and the barrier metal layer. Forming a storage electrode including a film pattern, the oxygen diffusion barrier pattern, and the oxidation resistant metal film pattern, forming an insulating film on the entire surface of the resultant product on which the storage electrode is formed, to a first thickness; The thickness of the first thickness such that the thickness on the pattern is a second thickness thinner than the first thickness Polishing the smoke film by a chemical mechanical polishing (CMP) process to form an insulating film having a reduced surface step, and etching back the insulating film having the reduced surface step until the oxide-resistant metal film pattern is exposed; And forming an insulating film pattern completely covering sidewalls of the barrier metal film pattern between electrodes.
본 발명에 의하면, 스토리지 전극의 구성요소인 장벽금속막 패턴의 측벽을 완전히 덮는 절연막 패턴을 형성할 수 있다. 이에 따라 고유전막을 형성하는 후속공정시 장벽금속막 패턴이 산화되는 현상을 방지할 수 있으므로 고집적 반도체소자에 적합한 고용량의 커패시터를 구현할 수 있다.According to the present invention, it is possible to form an insulating film pattern that completely covers the sidewall of the barrier metal film pattern that is a component of the storage electrode. As a result, the oxidation of the barrier metal film pattern may be prevented in a subsequent process of forming a high dielectric film, thereby enabling a capacitor having a high capacitance suitable for a highly integrated semiconductor device.
이하 첨부한 도면을 참조하여 본 발명에 따른 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 4는 층간절연막 패턴(23) 및 플러그 패턴(25)을 형성하는 단계를 설명하기 위한 단면도이다. 먼저, 불순물로 도우핑된 활성영역이 형성된 반도체기판(21) 상에 층간절연막, 예컨대 BPSG막을 형성한다. 이어서, 상기 층간절연막을 패터닝하여 상기 활성영역의 소정영역을 노출시키는 콘택홀을 구비하는 층간절연막 패턴(23)을 형성한다. 다음에, 상기 층간절연막 패턴(23)이 형성된 결과물 전면에 상기 콘택홀을 채우는 도전막, 예컨대 도우핑된 폴리실리콘막을 형성하고, 상기 층간절연막 패턴(23)이 노출될 때까지 도전막을 에치백 하거나 CMP 공정을 적용함으로써, 콘택홀 내부에 플러그 패턴(25)을 형성한다.4 is a cross-sectional view for describing a step of forming the interlayer insulating film pattern 23 and the plug pattern 25. First, an interlayer insulating film, such as a BPSG film, is formed on a semiconductor substrate 21 on which an active region doped with impurities is formed. Subsequently, the interlayer insulating layer is patterned to form an interlayer insulating layer pattern 23 having a contact hole exposing a predetermined region of the active region. Next, a conductive film filling the contact hole, for example, a doped polysilicon film, is formed on the entire surface of the resultant layer on which the interlayer insulating film pattern 23 is formed, and the conductive film is etched back until the interlayer insulating film pattern 23 is exposed. By applying the CMP process, the plug pattern 25 is formed in the contact hole.
도 5는 스토리지 전극을 완성하고 그 결과물 전면에 절연막(35)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로 설명하면, 상기 플러그 패턴(25)이 형성된 결과물 전면에 장벽금속막, 산소 확산방지막, 및 내산화성 금속막을 차례로 형성한다. 여기서, 상기 장벽금속막 및 내산화성 금속막으로는 각각 타이타늄 질화막 및 백금막을 사용하는 것이 바람직하며, 상기 산소 확산방지막으로는 이리디움막 및 이리디움 산화막이 차례로 적층된 2중 물질막을 사용하는 것이 바람직하다. 다음에, 상기 내산화성 금속막, 산소 확산방지막, 및 장벽금속막을 연속적으로 패터닝하여 상기 플러그 패턴(25) 상에 순차적으로 적층된 장벽금속막 패턴(27), 이리디움막 패턴(29) 및 이리디움 산화막 패턴(31)이 차례로 적층된 산소 확산방지막 패턴, 및 내산화성 금속막 패턴(33)을 형성한다. 이와 같이 형성된 장벽금속막 패턴(27), 산소 확산방지막 패턴, 및 내산화성 금속막 패턴(33)은 상기 플러그 패턴(25)과 함께 스토리지 전극을 구성한다. 계속해서, 상기 스토리지 전극이 완성된 결과물 전면에 절연막(35), 예컨대 CVD 산화막을 제1 두께로 형성한다. 이때, 상기 절연막(35)은 스토리지 전극의 단차에 의해 참조부호 H로 표시한 크기만큼의 표면단차를 갖는다.5 is a cross-sectional view for explaining a step of completing the storage electrode and forming the insulating film 35 over the resultant. Specifically, a barrier metal film, an oxygen diffusion barrier, and an oxidation resistant metal film are sequentially formed on the entire surface of the resultant product in which the plug pattern 25 is formed. Here, it is preferable to use a titanium nitride film and a platinum film as the barrier metal film and the oxidation resistant metal film, respectively, and as the oxygen diffusion prevention film, it is preferable to use a double material film in which an iridium film and an iridium oxide film are sequentially stacked. Do. Next, the barrier metal film pattern 27, the iridium film pattern 29, and the free layer stacked on the plug pattern 25 by successively patterning the oxidation resistant metal film, the oxygen diffusion barrier film, and the barrier metal film. An oxygen diffusion barrier pattern and an oxidation resistant metal layer pattern 33 in which the oxide oxide layer pattern 31 is sequentially stacked are formed. The barrier metal layer pattern 27, the oxygen diffusion barrier layer pattern, and the oxidation resistant metal layer pattern 33 formed as described above together with the plug pattern 25 form a storage electrode. Subsequently, an insulating film 35, for example, a CVD oxide film, is formed on the entire surface of the resultant product in which the storage electrode is completed. In this case, the insulating layer 35 has a surface step by the size indicated by the reference H by the step of the storage electrode.
도 6은 본 발명의 특징요소인 표면단차가 완화된 절연막(35a)을 형성하는 단계를 설명하기 위한 단면도이다. 보다 상세히 설명하면, 상기 절연막(35)을 CMP(chemical mechanical polishing) 공정으로 상기 제1 두께보다 작은 소정의 두께만큼 연마한다. 이와 같이 CMP 공정으로 상기 절연막(35)을 연마하고 나면, 상기 내산화성 금속막 패턴(33) 상의 절연막(35)만이 식각되어 내산화성 금속막 패턴(33) 상에 상기 제1 두께보다 얇은 제2 두께를 가지면서 참조부호 H1으로 표시한 바와 같이 표면단차가 완화된 절연막(35a)이 형성된다.FIG. 6 is a cross-sectional view for explaining a step of forming an insulating film 35a having a reduced surface step, which is a feature of the present invention. In more detail, the insulating film 35 is polished by a predetermined thickness smaller than the first thickness by a chemical mechanical polishing (CMP) process. After the insulating film 35 is polished by the CMP process as described above, only the insulating film 35 on the oxidized metal film pattern 33 is etched to form a second thinner than the first thickness on the oxidized metal film pattern 33. An insulating film 35a having a thickness and having a reduced surface step as shown by reference numeral H1 is formed.
도 7은 절연막 패턴(35b), 고유전막(37) 및 플레이트 전극(39)을 형성하는 단계를 설명하기 위한 단면도이다. 먼저, 상기 내산화성 금속막 패턴(33)이 노출될 때까지 표면단차가 완화된 절연막(35a)을 전면 에치 백(etch-back)한다. 이와 같이 표면단차가 완화된 절연막(35a)을 전면 에치 백 하고 나면, 상기 스토리지 전극 사이에 적어도 장벽금속막 패턴(27)의 측벽을 완전히 덮는 절연막 패턴(35b)이 형성된다. 이는, 상기 에치 백 공정시 스토리지 전극 사이에 존재하는 표면단차가 완화된 절연막(35a)이 식각되는 양이 종래의 기술에 비하여 적기 때문이다. 이어서, 상기 결과물 전면에 고유전막(37), 예컨대 수십 내지 수백 정도의 유전상수를 갖는 BST(BaSrTiO3)막, 탄탈륨 산화막, 또는 PZT(PbZrTiO3)막을 형성하고, 그 위에 백금막으로 플레이트 전극(39)을 형성한다.FIG. 7 is a cross-sectional view for describing a step of forming the insulating film pattern 35b, the high dielectric film 37, and the plate electrode 39. First, the entire surface of the insulating layer 35a with the reduced surface step is etched back until the oxidation resistant metal layer pattern 33 is exposed. After the entire surface is etched back to the insulating layer 35a having the reduced surface step, an insulating layer pattern 35b is formed between the storage electrodes to completely cover the sidewall of the barrier metal layer pattern 27. This is because the amount of etching of the insulating film 35a with the reduced surface step existing between the storage electrodes during the etch back process is smaller than that of the related art. Subsequently, a high dielectric film 37, for example, a BST (BaSrTiO3) film, a tantalum oxide film, or a PZT (PbZrTiO3) film having a dielectric constant of several tens to several hundreds is formed on the entire surface of the resultant, and the plate electrode 39 is formed thereon with a platinum film. To form.
본 발명은 상기 실시예에 한정되지 않고 당업자의 수준에서 그 변형 및 개량이 가능하다.The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.
상술한 바와 같이 본 발명의 실시예에 의하면, 스토리지 전극의 구성요소인 장벽금속막 패턴의 측벽을 완전히 덮는 절연막 패턴을 형성함으로써, 고유전막 형성시 장벽금속막 패턴이 산화되는 현상을 방지할 수 있다. 따라서, 스토리지 전극의 저항이 증가하는 것을 방지하면서 고용량의 커패시터를 제조할 수 있으므로 고집적 반도체소자에 적합한 커패시터를 구현할 수 있다.As described above, according to the embodiment of the present invention, by forming an insulating film pattern that completely covers the sidewall of the barrier metal film pattern, which is a component of the storage electrode, it is possible to prevent the phenomenon of the barrier metal film pattern being oxidized when forming the high dielectric film. . Therefore, a capacitor having a high capacitance can be manufactured while preventing the resistance of the storage electrode from increasing, thereby enabling a capacitor suitable for a highly integrated semiconductor device.
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| JPH0530416A (en) * | 1991-07-18 | 1993-02-05 | Matsushita Electric Ind Co Ltd | Video camera exposure controller |
| JPH0846150A (en) * | 1994-07-27 | 1996-02-16 | Oki Electric Ind Co Ltd | Semiconductor memory and fabrication thereof |
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