KR100218742B1 - Circuit arrangement method of sub word line driver stage - Google Patents

Abstract

According to the present invention, the circuit layout of the sub word line driver stage is improved in the sub word line driver region where the metal layer design loop is the tightest so that the width of the metal layer space is improved compared to the conventional layout so that mass production can be easily secured in devices of 64M or more. The present invention relates to a first process of securing a space for increasing the width of a metal layer space by using a metal contact and a metal two contact at each connection portion of the word line boosting signal node. In order to secure the width of the metal layer space between the word line boosting signal node and the ground voltage node, the positions of the metal 1,2 contacts of the word line boosting signal node are moved to the right of the metal 2 line of the word line boosting signal node, so that A second process of reducing contact space is implemented.

Description

Circuit arrangement method of sub word line driver stage

The present invention relates to a circuit arrangement method of a sub word line driver stage, and in particular, to reduce the metal 1 contact to be processed on the NISO layer from 2 to 1, the metal 1 contact and the metal 2 contact space A method of arranging a circuit of a sub word line driver stage that improves process margin by reducing space and moving metal 1 contacts symmetrically processed about metal 2 to one side to increase the space and width of the metal layer. .

A row decoder is used to control word lines in a semiconductor memory device. However, due to the high integration of memory devices, there is not enough space to lay out one decoder per word line. Therefore, at present, a plurality of hierarchical word line driving circuits are shared at one output of a single row decoder, and a hierarchical word line driving circuit is used so that it is distinguished by a sub-loo decoder (pxi generator).

In general, a hierarchical word line structure is used to mitigate the strict metal design rules that occur in metal strapping of word lines. Metal strapping is a method of arranging metal lines on top of a cell array with a word line pitch and connecting them to a poly-silicon word line to reduce the resistance of word lines made of poly-silicon. This reduces the resistance of the word line, resulting in faster drive times. (Pitch here refers to the sum of Line Width + Space in regularly arranged lines.) This metal strapping method decreases the word line pitch as the density of memory elements increases. Therefore, the yield ratio of the metal process is increased and yield is reduced. Therefore, the hierarchical word line structure has been applied to 64M DRAM products.

The present invention can be applied to all memory products using a sub-loo decoder circuit for driving a lower word line in a hierarchical word line structure applied to a memory product.

The conventional lower word line driving circuit used in the hierarchical word line structure is generally composed of three NMOS transistors, and the voltage boosted to the lower word line through a double bootstrapping process. Drive at high level (Vpp).

FIG. 1A shows a general row decoder circuit diagram for driving word lines Word_Line0: 3.

Referring to the figure, the pull-up transistor MN2, which is the second NMOS transistor, pulls up the word line WL to Vpp level, and the pull-down transistor MN3, which is the third NMOS transistor, is '0V' (ground). ) To pull down. The bootstrap transistor MN1, which is a first NMOS transistor, serves as a switch to maintain the potential after precharging and bootstrapping the second node N2. That is, in most cases, the potential signal Vxg becomes the power supply potential Vcc, and after precharging the second node N2 to Vx-Vt (Vt is a threshold voltage), the word line boosting after a predetermined time Td is delayed. As the signal pxi_out0: 3 is activated at the high potential Vpp, the second node N2 is bootstraped to a voltage of Vpp + Vt or higher, and thus the voltage 'Vpp' of the word line boosting signal px. Is transferred to the word line WL0 as it is through the pull-up transistor MN1.

FIG. 1B illustrates a word line strapping method, and makes contact between a poly layer used as a cell transistor gate electrode and connects a metal and a poly layer to each other. . However, in this method, the space between adjacent word lines is narrow and the width of the metal layer is narrowed over 64M DRAM of high density, resulting in bridge phenomenon or breakage of metal lines during the metal process. Loss has occurred frequently, which has been an obstacle to ensuring mass productivity. In order to solve this problem, a conventional sub wordline driver circuit is used.

FIG. 2A shows a conventional row decoder circuit, and FIG. 2B shows a conventional sub wordline driver circuit diagram.

The outputs of the row decoders pu and pd are the main word lines, which drive the entire area to drive 1024 cells, and input the main word lines to several cell areas. A sub word line driver stage was formed and connected to Poly 1 used as a cell transistor gate electrode. The poly-layer wordline drives 1024 cells.

3A and 3B show schematic and layout diagrams of a conventional sub wordline driver circuit.

This approach allows the metal fill width and space to be larger in most areas than the wordline strapping method, but the metal layer still has less process margin in the sub wordline driver region. In area a of FIG. 3b, the pxi-out1 node, which is the word line boosting signal shown in FIG. 3a, is shown as a layout. The metal line width and space are used because two metal 1 contacts are used. There was a problem in that the space between the metal 1 and 2 contacts in the b region could not be increased and the width of pd0, pd1, and space could not be increased.

Therefore, in the present invention, the metal 1 contacts processed on the MISO layer are reduced from two to one, the metal 1 contacts and the metal 2 contact spaces are reduced, and the metal 1 contacts symmetrically processed around the metal 2 to one side. It is an object of the present invention to provide a circuit arrangement method of a sub word line driver stage in which a process margin is improved by moving and increasing a space and width of a metal layer.

In order to achieve the above object, in the circuit arrangement method of a sub word line driver stage according to the present invention, a bootstrap transistor connected between a fall-up signal input node and a bootstrap node and a potential signal is applied to a gate, and word line boosting A pull-up transistor connected between a signal node and a sub word line and having a gate connected to the bootstrap node, and a pull-down transistor connected between the sub word line and a ground voltage node and to which a pull-down signal is applied to the gate; A circuit arrangement method of a sub word line driver stage according to claim 1, wherein each of a metal contact and a metal 2 contact is used at a connection portion of the word line boosting signal node to secure a space for increasing a metal layer space and a width thereof. And a metal layer between the word line boosting signal node and a ground voltage node. A second process of moving the second metal contacts positioned drilling to the word line boosting signal node to the right two metal lines of the word line boosting signal node to reduce the contact space of the ground voltage node, and implemented in order to secure the device and width.

Figure 1a is a general row decoder circuit diagram.

1B is a diagram illustrating a word line strapping scheme.

Figure 2a is a conventional row decoder circuit diagram.

2B is a conventional sub wordline driver circuit diagram.

3A and 3B are a schematic diagram and layout diagram of a conventional sub wordline driver circuit.

4A and 4B are a schematic and layout diagram of a sub wordline driver circuit according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

MN1: Bootstrap Transistor MN2: Pull-Up Transistor

MN3: pull-down transistor

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A and 4B show a schematic diagram and a layout diagram of a sub word line driver circuit according to an embodiment of the present invention.

The structure of the sub word line driver circuit shown in FIG. 4A is the same as the conventional one, and is a bootstrap transistor connected between a pull-up signal pu input node and a bootstrap node and to which a potential signal Vxg is applied to a gate. A pull-up transistor MN2 connected between the MN1, a word line boosting signal pxi_out1 node, and a sub word line sub_w1, and a gate connected to the bootstrap node, and the subword line sub_w1; It is composed of a pull-down transistor MN3 connected between a ground voltage Vtss node and a pull-down signal pd applied to a gate. 4B is a layout diagram of a circuit arrangement method of a sub word line driver stage of the present invention.

Briefly referring to the operation by the above configuration, the pull-up signal and the pull-down signal (pu, pd) nodes are used as the main word line as the output of the row decoder in the sub word line driver circuit of FIG. area) When the low decoder unit is enabled, the pull-up signal pu node becomes 'logic high', and the pull-down signal pd indicates a 'logic low' state. This level is transferred to the bootstrapping node between transistors MN1 and MN2 through transistor MN1. Then, when the Vpp (Vcc = 5V to 5V) level is input to the pxi-outl node, which is a wordline boosting signal, bootstrapping occurs and the voltage level of pxi_out1 is loaded on the sub wordline without voltage loss. .

As can be seen in Figure 3, it shows the layout of the schematic diagram of the sub word line driver stage. The lines running vertically are 6 lines Vtss, pxi, Vxg (= Vtcc) processed with metal 2, and the layer running horizontally is pu, pd. As a node used as a process, it is processed into metal 1. However, in the area A of FIG. 3, the schematic diagram pxi-out1 node is shown as a layout. Since two metal 1 contacts are used, the width and space of the metal line cannot be increased, and the metal 1,2 contact of the B area is also shown. Since the space between them is large, pd <0> and pd <1> width space cannot be enlarged. If the metal 1,2 contacts are moved to the right side of the pxi-out as in the areas A and B of FIG. 4b, and the metal contact spacing is reduced, the space where the width and width of pu <0>, pd <0> metal can be increased is increased. Secured. That is, by using a metal contact and a metal 2 contact, respectively, at the connection portion of the word line boosting signal (pxi-out1) node to secure a space for increasing the metal layer space and width, the word line boosting signal node and the ground In order to secure the metal layer space and width between the voltage nodes, the metal 1,2 contact positions of the word line boosting signal nodes are moved to the right side of the metal line 2 of the word line boosting signal node to reduce the contact space of the ground voltage node.

As described above, in the circuit arrangement method of the sub word line driver stage according to the present invention, the space and width of the metal layer in the sub word line driver region where the metal layer design rule is the tightest. Since it is possible to increase the size, it is easy to secure mass productivity in a 64M or higher device than the conventional layout method.

In addition, preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (1)

A bootstrap transistor connected between the pull-up signal input node and the bootstrap node and a potential signal applied to the gate, and a pull-up connected between the wordline boosting signal node and the sub wordline and whose gate is connected to the bootstrap node. 8. A circuit arrangement method of a sub word line driver stage having a transistor and a pull-down transistor connected between the sub word line and a ground voltage node, and having a fall-down signal applied to a gate, the circuit arrangement method of the word line boosting signal node. The first step of securing a space to increase the metal layer space and width by using a metal contact and a metal 2 contact each one at the connection portion, and to secure the metal layer space and width between the word line boosting signal node and the ground voltage node To position the metal 1,2 contact points connected to the word line boosting signal node in order to Drive of the boosting signal line next to the second node metal to move the circuit arrangement of how sub-word line driver stage comprises a second process of reducing the contact space of the ground potential of the node.