KR100218739B1 - Method of forming a device isolation film of semiconductor device - Google Patents
Method of forming a device isolation film of semiconductor device Download PDFInfo
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- KR100218739B1 KR100218739B1 KR1019960068909A KR19960068909A KR100218739B1 KR 100218739 B1 KR100218739 B1 KR 100218739B1 KR 1019960068909 A KR1019960068909 A KR 1019960068909A KR 19960068909 A KR19960068909 A KR 19960068909A KR 100218739 B1 KR100218739 B1 KR 100218739B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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Abstract
본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 반도체기판을 일정두께 식각하여 소폭과 광폭의 트렌치를 형성하고 이를 매립하는 트렌치형 소자 분리 절연막 형성방법에 있어서, 상기 반도체기판 상부에 제 1절연막과 제 2절연막을 각각 일정두께 형성하고 상기 반도체기판에 트렌치를 형성한 다음, 상기 트렌치를 매립하는 제 3절연막을 형성하고 상기 제 3절연막을 이방성식각하여 제 3절연막 스페이서를 형성한 다음, 상기 광폭의 트렌치 저부를 열 산화시켜 열산화막을 형성하는 동시에 소폭의 트렌치에 버즈빅을 형성하고 상기 제 2,1절연막을 습식방법으로 제거하는 동시에 반도체기판 상부로 형성된 제 3절연막을 평탄화시키는 공정으로 소자분리 절연막을 형성하여 후속공정을 용이하게 하는 동시에 누설 전류의 발생을 억제하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, comprising: forming a trench of a narrow width and a wide width by etching a semiconductor substrate to a predetermined thickness and filling the trench; After forming an insulating film and a second insulating film, and forming a trench in the semiconductor substrate, and forming a third insulating film filling the trench, and anisotropically etching the third insulating film to form a third insulating film spacer, Thermal oxidation of a wide trench bottom to form a thermal oxide film, a buzz big in a narrow trench, a wet method of removing the second and first insulating films, and a planarization of the third insulating film formed on the upper portion of the semiconductor substrate. The isolation insulating film is formed to facilitate the subsequent process and to suppress the occurrence of leakage current It is a technique that can improve the characteristics and reliability of semiconductor elements over.
Description
본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 특히 트렌치를 매립하는 소자분리절연막의 손상을 방지하여 후속공정을 용이하게 실시할 수 있도록 함으로써 반도체소자의 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, and more particularly, to a technique for improving characteristics and reliability of a semiconductor device by preventing damage to a device isolation insulating film filling a trench so that subsequent steps can be easily performed. will be.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼(dimension)을 축소하는 것과 , 소자간의 존재하는 분리 영역(isolation region)의 폭과 면적을 축소하는 것이 필요하며, 이 축소 정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the density of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. In terms of size, the device isolation technology is a technology for determining memory cell size.
소자 분리 절연막을 제조하는 종래기술로는 절연물 분리방식의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS라 함)방법, 실리콘기판 상부에 산화막, 다결정실리콘층, 질화막순으로 적층한 구조의 피,비.엘(poly - Buffed LOCOS, 이하에서 PBL 이라 함)방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치(trench)방법 등이 있다.Conventional techniques for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method of insulating material isolation method, an oxide film, a polysilicon layer, and a nitride film stacked on top of a silicon substrate. And B.L (poly-Buffed LOCOS, hereinafter referred to as PBL) method, and a trench method of forming a groove in a substrate and then filling it with an insulating material.
그러나, 상기 LOCOS 방법으로 소자분리 산화막을 미세화할 때 공정상 또는 전기적인 문제가 발생한다. 그 중의 하나는, 소자분리절연막만으로는 전기적으로 소자를 완전히 분리할 수 없다는 것이다.However, when the device isolation oxide film is miniaturized by the LOCOS method, process or electrical problems occur. One of them is that the device isolation insulating film alone cannot completely separate the devices.
그래서, 소자분리 산화막을 형성하는 산화공정 직전 또는 이후에 고농도의 B 또는 BF2이온을 소자분리절연막의 하부에 이온주입시켜 격리효과를 보상해 주는데, 이 공정을 N채널 필드 임플란트(N-channel field implant)공정 즉, 채널스토퍼(channel stopper) 형성 공정이라 한다.Therefore, a high concentration of B or BF 2 ions are implanted into the lower portion of the device isolation insulating film immediately before or after the oxidation process to form the device isolation oxide film, thereby compensating the isolation effect, which is an N-channel field implant. This is called an implant process, that is, a channel stopper forming process.
이때, 채널스토퍼로 사용되는 B 또는 BF2는 소자분리 산화공정중에 또는 기타 열처리공정시에 활성영역으로 측면확산하여 활성영역이 좁아지면서, 활성트랜지스터의 문턱전압(threshold voltage)을 높이는 내로우(narrow) 채널 효과를 일으키고, 소오스/드레인을 향해 측면확산하여 n+접합과 중첩되면서 일어나는 n+접합 브레이크다운 전압(breakdown voltage)의 감소나 접합누출의 증대 등의 문제를 일으키며, 소자분리절연막이 형성후에 채널스톱 불순물을 주입할 경우에는 고에너지의 이온주입을 하기 때문에 소자분리 절연막의 끝부분이 손상되어 게이트 산화막의 열화를 가져올 수 있다. 그리고, 소자 분리절연막의 상층부는 기판과 단차를 형성하여 후속공정의 진행시 어려움이 있다.In this case, B or BF 2, which is used as a channel stopper, is narrowed by lateral diffusion into the active region during the device isolation oxidation process or other heat treatment process, and increases the threshold voltage of the active transistor. ) causing the channel effect, causes problems such as increase in the reduction or junction leakage while overlapping the n + junction with the side diffusion toward the source / drain that occurs n + junction breakdown voltage (breakdown voltage), the device isolation insulation film after the formation In the case of implanting channel stop impurities, ion implantation of high energy is performed, and thus the tip of the device isolation insulating layer may be damaged, resulting in deterioration of the gate oxide layer. In addition, the upper portion of the device isolation insulating layer may form a step with the substrate, which may cause difficulty in the subsequent process.
그리고, 상기 PBL을 사용하는 경우, 필드산화시에 산소의 측면확산에 의하여 버즈빅이 발생한다. 즉, 활성영역이 작아져 활성영역을 효과적으로 활용하지 못하며, 필드산화막의 두께가 두껍기 때문에 단차가 형성되어 후속공정에 어려움을 준다. 그리고, 기판상부의 다결정실리콘층으로 인하여 필드산화시 기판내부로 형성되는 소자분리절연막이 타기법에 비하여 상대적으로 작기 때문에 타기법에 비해 신뢰성을 약화시킬 수 있다.In the case of using the above-described PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. Further, due to the polysilicon layer on the substrate, the device isolation insulating film formed inside the substrate during field oxidation is relatively smaller than that of the hitting method, thereby reducing the reliability of the hitting method.
이상에서 설명한 LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 되므로써 후속공정을 어렵게 하는 단점이 있다.The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.
이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고 후속공정을 평탄화시킴으로써 후속공정을 용이하게 실시할 수 있도록 하였다.In order to solve this disadvantage, the semiconductor substrate is etched to form a trench, and the trench is buried, and then the CMP method is used to planarize the top surface and to planarize the subsequent process so that the subsequent process can be easily performed.
도 1a 내지 도1c는 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 것이다.1A to 1C illustrate a method of forming a device isolation insulating film of a semiconductor device according to the prior art.
먼저, 반도체기판(41) 상부에 패드산화막(43)을 형성하고, 상기 패드산화막(43) 상부에 질화막(45)을 형성한다.First, a pad oxide film 43 is formed on the semiconductor substrate 41, and a nitride film 45 is formed on the pad oxide film 43.
그리고, 소자분리마스크(도시안됨)을 이용한 식각공정에서 상기 질화막(45)과 패드산화막(43) 및 일정두께의 반도체기판(41)을 식각하여 상기 반도체기판(41)에 트렌치(37)를 형성한다.In the etching process using a device isolation mask (not shown), the nitride layer 45, the pad oxide layer 43, and the semiconductor substrate 41 having a predetermined thickness are etched to form the trench 37 in the semiconductor substrate 41. do.
그 다음에, 상기 트렌치(47)를 매립하는 산화막(49)을 형성하고, 상기 산화막(49)을 CMP하여 상부면을 평탄하게 형성한다.(도 1a)Next, an oxide film 49 filling the trench 47 is formed, and the oxide film 49 is CMP to form a flat top surface (FIG. 1A).
그리고, 상기 질화막(45)을 제거한다. 이때, 상기 질화막(45)은 인산용액을 이용한 습식방법으로 제거한다(도 1b)Then, the nitride film 45 is removed. At this time, the nitride film 45 is removed by a wet method using a phosphoric acid solution (FIG. 1B).
그 다음에, 상기 패드산화막(43)을 제거하는 습식세정공정을 실시하고, 상기 패드산화막(43)이 제거된 반도체기판(41)상부에 게이트산화막(도시안됨)을 형성하기 위하여 습식세정공정을 실시한다.Then, a wet cleaning process is performed to remove the pad oxide film 43, and a wet cleaning process is performed to form a gate oxide film (not shown) on the semiconductor substrate 41 from which the pad oxide film 43 is removed. Conduct.
이때, 상기 산화막(49)과 반도체기판(41)의 경계부에 위치한 상기 산화막(49)에 상기 트랜치 (47)안쪽으로 ⓑ와 같이 식각되는 턱짐현상이 발생하여 후속공정을 어렵게 할 뿐만 아니라 반도체기판의 누설전류를 유발시켜 반도체소자의 특성 및 신뢰성을 저하시킴으로써 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.(도 1c)At this time, the etch phenomenon such as ⓑ is etched into the trench 47 in the oxide film 49 located at the boundary between the oxide film 49 and the semiconductor substrate 41, thereby making the subsequent process difficult and the process of the semiconductor substrate. There is a problem in that it is difficult to increase the integration of the semiconductor device by reducing the characteristics and reliability of the semiconductor device by causing a leakage current.
따라서, 본 발명의 상기한 종래기술의 문제점을 해결하기 위하여, 트렌치를 완전히 매립할 수 있는 소자분리절연막을 형성하여 후속공정을 용이하게 하고 반도체기판의 누설전류를 감소시켜 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems of the prior art of the present invention, by forming a device isolation insulating film that can completely fill the trench to facilitate the subsequent process and to reduce the leakage current of the semiconductor substrate to improve the characteristics and reliability of the semiconductor device. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a device isolation insulating film of a semiconductor device that can be improved and thereby high integration of the semiconductor device.
제 1a 내 지 제 1c는 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.
제2a도 내지 제 2g는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.2A to 2G are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,41 : 반도체기판 13,43 : 패드산화막11,41: semiconductor substrate 13,43: pad oxide film
15,45 : 질화막 17 : 감광막패턴15,45: nitride film 17: photoresist pattern
19 : 소폭의 트랜치 21 : 광폭의 트렌치19: narrow trench 21: wide trench
23,49 : 산화막 25 : 산화막 스페이서23,49 oxide film 25 oxide film spacer
23 : 열산화막 29,31 : 소자분리 절연막23: thermal oxide film 29, 31: device isolation insulating film
33 : 게이트 산화막 47 : 트렌치33: gate oxide film 47: trench
ⓐ : 버즈빅Ⓐ: Buzz Big
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리 절연막 형성방법은 반도체기판을 일정두께 식각하여 소폭과 광폭의 트렌치를 형성하고 이를 매립하는 트렌치형 소자분리절연막 형성방법에 있어서, 상기 반도체기판 상부에 제 1절연막과 제 2절연막을 각각 일정두께 형성하는 공정과, 상기 반도체기판에 트렌치를 형성하는 공정과, 상기 트렌치를 매립하는 제 3절연막을 형성하는 공정과, 상기 제 3절연막을 이방성식각하여 제 3절연막 스페이서를 형성하는 공정과, 상기 광폭의 트렌치 저부를 열산화시켜 열산화막을 형성하는 동시에 소폭의 트렌치에 버즈빅을 형성하는 공정과, 상기 제 2,1절연막을 습식방법으로 제거하는 동시에 반도체기판 상부로 형성된 제 3절연막을 평탄화시키는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a device isolation insulating film of a semiconductor device according to the present invention is a method of forming a trench type device isolation insulating film for etching a semiconductor substrate by a predetermined thickness to form a trench having a narrow width and a wide width, and filling the trench. Forming a first insulating film and a second insulating film on the semiconductor substrate, forming a trench in the semiconductor substrate, forming a third insulating film to fill the trench, and anisotropically etching the third insulating film. Forming a third insulating film spacer, thermally oxidizing the bottom of the wide trench to form a thermal oxide film, and forming a buzz beak in the narrow trench, and removing the second and first insulating films by a wet method. At the same time, the step of planarizing the third insulating film formed on the upper surface of the semiconductor substrate.
한편, 상기한 목적을 달성하기 위한 본 발명의 원리는, 마스크를 이용하여 소폭과 광폭의 트렌치를 형성하고 상기 광폭의 트렌치에 스페이서를 형성하되, 반도체기판 상부에 형성된 패드산화막과, 질화막과 같은 구조물 및 상기 트렌치의 측벽에 형성하는 동시에 소폭의 트렌치를 매립하는 절연막이 버즈빅(bird's beak)을 갖도록 하여 후속공정인 세정공정시 소자분리절연막의 손상을 방지함으로써 후속공정을 용이하게 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있도록 하는 것이다.On the other hand, the principle of the present invention for achieving the above object, by forming a narrow and wide trench using a mask and forming a spacer in the wide trench, a structure such as a pad oxide film formed on the semiconductor substrate, the nitride film And an insulating film forming a trench on the sidewall of the trench and having a small trench to have a bird's beak, thereby preventing damage to the device isolation insulating film during a subsequent cleaning process, thereby facilitating subsequent processes. And to improve the reliability.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 본 발명이 실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도이다.2A to 2G are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(11)상부에 패드산화막(13) 및 질화막(15)을 각각 일정두께 형성한다. 그리고 상기 질화막(15)상부에 감광막패턴(17)을 형성한다.First, a pad oxide film 13 and a nitride film 15 are formed on the semiconductor substrate 11 at a predetermined thickness, respectively. The photoresist pattern 17 is formed on the nitride film 15.
이때, 상기 감광막패턴(17)은 소자분리마스크(도시안됨)를 이용한 노광 및 현상공정을 형성한다.(도 2a)In this case, the photoresist pattern 17 forms an exposure and development process using an element isolation mask (not shown).
그 다음에, 상기 감광막패턴(17)을 마스크로 하여 상기 질화막(15), 패드산화막(13) 및 일정두께의 반도체기판(11)을 식각하여 소폭과 광폭의 트렌치(19,21)를 형성한다.Next, the nitride film 15, the pad oxide film 13, and the semiconductor substrate 11 having a predetermined thickness are etched using the photoresist pattern 17 as a mask to form narrow and wide trenches 19 and 21. .
그리고, 상기 감광막패턴(17)을 제거한다.(도 2b)Then, the photoresist pattern 17 is removed (FIG. 2B).
그 다음에, 상기 트렌치(19,21)를 매립하는 산화막(23)을 형성한다. 이때, 상기 산화막(23)은 화학기상증착(Chemical Vapor Deposition, 이하에서 CVD라 함) 산화막이나 고밀도 플라즈마 산화막으로 형성한다.(도 2c)Next, an oxide film 23 filling the trenches 19 and 21 is formed. At this time, the oxide film 23 is formed of a chemical vapor deposition (hereinafter referred to as CVD) oxide film or a high density plasma oxide film (FIG. 2C).
그리고, 상기 산화막(23)을 이방성식각하여 상기 소폭의 트렌치(19)를 매립하는 동시에 상기 광폭의 트렌치(21)에 산화막 스페이서(25)를 형성한다.(도 2d)Then, the oxide film 23 is anisotropically etched to fill the narrow trench 19, and an oxide spacer 25 is formed in the wide trench 21 (FIG. 2D).
그 다음에, 열산화공정으로 상기 광폭의 트렌치(21) 저부를 산화시켜 열산화막(27)을 500∼1000Å 정도의 두께로 형성한다. 이때, 상기 소폭의 트렌치(19)가 형성된 부분은 버즈빅이 ⓐ와 같이 형성된다.Then, the bottom of the wide trench 21 is oxidized by a thermal oxidation process to form a thermal oxide film 27 having a thickness of about 500 to 1000 GPa. At this time, the portion where the narrow trench 19 is formed, the buzz big is formed as ⓐ.
여기서, 상기 버즈빅ⓐ는 500∼2500Å 정도의 길이로 형성된다.(도 2e)Here, the buzz big ⓐ is formed to a length of about 500 ~ 2500Å (Fig. 2e).
그 다음에, 인산용액을 이용하는 습식방법으로 상기 질화막(15)을 제거하고 세정공정을 실시한다.(도 2f)Next, the nitride film 15 is removed by a wet method using a phosphoric acid solution and a cleaning process is performed (FIG. 2F).
그리고, 상기 패드산화막(13)을 제거하는 세정공정을 실시한다. 그리고 상기 패드산화막(13)이 제거된 반도체기판(11)상부에 게이트산화막(도시안됨)을 형성하기 위하여 습식 세정공정을 실시한다.Then, a cleaning step of removing the pad oxide film 13 is performed. In addition, a wet cleaning process is performed to form a gate oxide film (not shown) on the semiconductor substrate 11 from which the pad oxide film 13 is removed.
여기서, 상기 반도체기판(11) 표면으로 돌출된 산화막(23)과 산화막 스페이서(25)는 상기 도2f부터의 습식방법으로 각각 일정부분씩 식각되어 상기 반도체기판(11)의 표면이 평탄화된다.In this case, the oxide film 23 and the oxide film spacer 25 protruding from the surface of the semiconductor substrate 11 are etched by a predetermined portion by the wet method of FIG. 2F to planarize the surface of the semiconductor substrate 11.
그 다음에, 상기 반도체기판(11) 표면을 열산화시켜 게이트산화막(33)을 형성하는 동시에 상기 소폭과 광폭의 트렌치(19,21)에 소자분리절연막(29,31)을 형성한다.(도 2g)Then, the surface of the semiconductor substrate 11 is thermally oxidized to form a gate oxide film 33, and at the same time, device isolation insulating films 29 and 31 are formed in the narrow and wide trenches 19 and 21. 2g)
본 발명의 다른 실시예는 상기 트렌치를 매립하는 소자분리절연막 형성방법을 PBL 구조에 적용하여 사용하는 것이다.Another embodiment of the present invention is to use a method of forming a device isolation insulating film to fill the trench in a PBL structure.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은, 종래기술에서 습식세정공정시 손상되는 부분을 보상해줄 수 있는 절연막 스페이서 및 버즈빅을 형성하여 상부면이 평탄화된 소자분리절연막을 형성할 수 있도록 함으로써 후속공정을 용이하게 하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, in the method of forming a device isolation insulating film of a semiconductor device according to the present invention, a device isolation insulating film having an upper surface planarized by forming an insulating film spacer and a buzz bee that can compensate for a damaged part during a wet cleaning process in the prior art. By making it possible to facilitate the subsequent process to improve the characteristics and reliability of the semiconductor device, there is an advantage to enable high integration of the semiconductor device accordingly.
Claims (6)
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