KR100216544B1 - Method of manufacturing planar antifuse device - Google Patents
Method of manufacturing planar antifuse device Download PDFInfo
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- KR100216544B1 KR100216544B1 KR1019950049253A KR19950049253A KR100216544B1 KR 100216544 B1 KR100216544 B1 KR 100216544B1 KR 1019950049253 A KR1019950049253 A KR 1019950049253A KR 19950049253 A KR19950049253 A KR 19950049253A KR 100216544 B1 KR100216544 B1 KR 100216544B1
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- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 46
- 238000000206 photolithography Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 238000009826 distribution Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 229910006990 Si1-xGex Inorganic materials 0.000 description 1
- 229910007020 Si1−xGex Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 안트퓨즈 소자의 제조방법에 관한 것으로, 특히 활성층형성용 금속의 전기적 특성을 향상시켜 저 전압에서도 프로그래밍이 가능하도록 하는데 적합하도록 한 안티퓨즈 소자의 제조방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a method of manufacturing an anthuse device, and more particularly, to a method of manufacturing an antifuse device suitable for improving electrical characteristics of an active layer forming metal so that programming at low voltage is possible.
상술한 본 발명은 활성층(23)으로서 Si1-xGex을 형성하고 접촉창(30, 31)에 의해 토출된 활성층(23) 표면에 TEOS 막을 형성하며, 이 TEOS 막의 표면에 전극을 형성한 구조로 제조하여 균일한 절연파괴전압과 낮은 절연파괴전압을 실현함으로써 프로그래밍의 신뢰성이 증대된다.In the above-described present invention, the active layer 23 forms Si1- x Ge x and the TEOS film is formed on the surface of the active layer 23 discharged by the contact windows 30 and 31, and the electrode is formed on the surface of the TEOS film. The reliability of programming is increased by realizing uniform dielectric breakdown voltage and low dielectric breakdown voltage.
Description
제1도는 종래 기술에 따른 평면형 안티퓨즈 소자의 제조방법을 나타낸 공정 단면도.1 is a cross-sectional view showing a method of manufacturing a planar antifuse device according to the prior art.
제2도는 본 발명에 따른 평면형 안티퓨즈 소자의 제조방법을 나타낸 공정 단면도.2 is a cross-sectional view showing a method of manufacturing a planar antifuse device according to the present invention.
제3도는 본 발명과 종래 기술의 평면형 안티퓨즈 소자의 배선전극양단에 전압을 인가하였을 때 활성층에 흐르는 전류분포를 나타낸 그래프.3 is a graph showing the current distribution flowing in the active layer when a voltage is applied across the wiring electrode of the planar antifuse device of the present invention and the prior art.
제4도는 본 발명에 따른 평면형 안티퓨즈 소자가 프로그래밍된 후 소자의 저항분포를 나타낸 그래프.4 is a graph showing the resistance distribution of a device after the planar antifuse device according to the present invention has been programmed.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 제1절연막21 semiconductor substrate 22 first insulating film
23 : 활성층 24 : 제2절연막23: active layer 24: second insulating film
25, 26 : 제3절연막 27, 28 : 전극25, 26: third insulating film 27, 28: electrode
본 발명은 평면형 안티 퓨즈 소자에 관한 것으로 특히, 활성층 형성용 금속의 전기적 특성을 향상시켜 저 전압에서도 프로그래밍이 가능하도록 하는데 적합하도록한 안티 퓨즈 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to planar antifuse devices, and more particularly, to a method of manufacturing an antifuse device suitable for improving electrical characteristics of an active layer forming metal and enabling programming at low voltages.
현장가공형 게이트어레이(Field Programming Gate Array : FRGA)의 응용을 위한 평면형 안티 퓨즈 소자는 정 전압펄스를 소자에 인가함으로써 활성층위에 형성되어 있는 절연막을 절연파괴시킨 후, 활성층 영역에서 알루미늄의 도선을 형성하여 프로그래밍한다.The planar anti-fuse device for application of field-programmable gate array (FRGA) insulates the insulating film formed on the active layer by applying a constant voltage pulse to the device, and then forms an aluminum conductor in the active layer region. To program.
일반적으로 반도체소자의 프로그래밍은 트랜지스터에 전압을 인가하는 신호라인 사이에 형성되어 있는 안티퓨즈를 도통상태로 만든 후 트랜지스터에 전압을 인가하여 동작하도록 하는 방법과, 배선의 소정영역을 단선하여 트랜지스터에 인가되는 전압(신호)를 차단하는 방법이 이용되고 있다.In general, programming of a semiconductor device is performed by applying a voltage to a transistor after making an antifuse formed between signal lines for applying a voltage to a transistor and applying a voltage to the transistor, and disconnecting a predetermined region of the wiring to apply to the transistor. A method of blocking a voltage (signal) to be used is used.
안티퓨즈 소자는 상기 프로그래밍 방법중에서 전자와 같이 전압이 인가되고 있지 않은 트랜지스터에 신호전압이 인가되도록 하여 프로그래밍할 때, 사용되며, 프로그래밍되기 전에는 높은 저항값을 가져야 하고, 프로그래밍된 후에는 낮은 저항값을 가져야 하며, 가능한한 짧은 프로그래밍 시간 및 적절한 프로그래밍 전압을 갖는 것 등이 바람직하다는 특성이 있다.The anti-fuse device is used when programming a signal voltage applied to a transistor to which no voltage is applied, such as the former, in the programming method. The anti-fuse device must have a high resistance value before programming and a low resistance value after programming. It is desirable to have a programming time as short as possible and to have an appropriate programming voltage.
특히, 상기 안티퓨즈 소자에 인가된 전압은 절연막의 절연파괴와 밀접한 관계가 있으며 또한 소자 양단의 전극에 흐르는 전류는 프로그래밍후의 활성층과 전극과의 접촉저항과 밀접함 관계가 있다.In particular, the voltage applied to the antifuse device is closely related to the dielectric breakdown of the insulating film, and the current flowing through the electrodes across the device is closely related to the contact resistance between the active layer and the electrode after programming.
예컨대, 안티퓨즈 소자는 일정 전압이하에서는 구동되지 않아야 하고, 활성층과 배선전극사이에 개재된 절연막의 절연파괴후 활설층과 배선금속의 접촉저항이 낮아야 하며, 설정된 전압에서 빠르게 절연막이 파괴가 일어나 소자가 구동(온 상태)되어야 한다.For example, the anti-fuse device should not be driven below a certain voltage, the contact resistance between the active layer and the wiring metal should be low after insulation breakdown of the insulating film interposed between the active layer and the wiring electrode. Should be driven (on).
상술한 안티퓨즈 소자의 일예로서 제1도의 공정 단면도를 참조하여 종래의 기술에 따른 안티퓨즈 소자를 제조하는 방법을 설명하면 다름과 같다.As an example of the anti-fuse device described above, a method of manufacturing the anti-fuse device according to the related art will be described with reference to the process cross-sectional view of FIG. 1.
먼저, 제1a도를 참조하면, 반도체 기판 (11)상에 후속증착되는 활성층과 기판의 절연을 위한 절연막으로서 열산화막(12)을 형성한다.First, referring to FIG. 1A, a thermal oxide film 12 is formed as an insulating film for insulating the substrate and the active layer subsequently deposited on the semiconductor substrate 11.
그다음, 제1b도에 도시한 바와 같이, 상기 열산화막(12)의 전면에 활성층 형성용 금속으로서 폴리실리콘(13a)을 형성한 후 이 폴리실리콘(13a)의 전도도를 향상시키기 위하여 전면에 이온 주입장치를 이용하여 불순물을 주입하고 이를 열처리하여 주입된 불순물울 활성화시킨다.Next, as shown in FIG. 1B, polysilicon 13a is formed as an active layer forming metal on the front surface of the thermal oxide film 12, and ion implantation is then performed on the front surface to improve the conductivity of the polysilicon 13a. Impurities are implanted using a device and heat treated to activate the implanted impurities.
이어서, 제1c 도에 도시한 바와 같이, 상기 폴리실리콘(13a)을 사진식각법으로 식각하여 소정의 폭을 갖는 활성층(13)을 형성한다.Subsequently, as shown in FIG. 1C, the polysilicon 13a is etched by photolithography to form an active layer 13 having a predetermined width.
이어서, 제1d 도에 도시한 바와 같이, 기판의 전면에 절연물질로서 층간 절연막(14)을 형성후 이를 사진식각법으로 패터닝 하여 상기 활성층(13)의 양단을 각각 소정의 폭으로 노출되도록 접촉창(15a, 15b)을 형성한다.Subsequently, as shown in FIG. 1D, an interlayer insulating film 14 is formed as an insulating material on the entire surface of the substrate and then patterned by photolithography to expose both ends of the active layer 13 to a predetermined width, respectively. (15a, 15b) are formed.
이어서 제1e도에 도시한 바와 같이, 상기 접촉창(15a, 15b)을 통해 노출된 활성층(13)의 표면을 열산화하여 활성층(13)의 표면에 열산화막(16a, 16b)을 형성한다.Subsequently, as illustrated in FIG. 1E, the surfaces of the active layer 13 exposed through the contact windows 15a and 15b are thermally oxidized to form thermal oxide films 16a and 16b on the surface of the active layer 13.
이어서, 제1f도에 도시한 바와 같이, 기판의 전면에 전극형성용 금속으로서 알루미늄을 증착하고 이를 사진식각 법으로 패터닝하여 상기 열산화막(16a, 16b) 표면과 층간절연막(14)의 표면상에 접촉되는 소정의 폭을 갖는 배선전극(17, 18)을 형성하여 안티퓨즈 소자를 제조한다.Subsequently, as shown in FIG. 1F, aluminum is deposited on the entire surface of the substrate as an electrode forming metal and patterned by photolithography on the surface of the thermal oxide films 16a and 16b and the surface of the interlayer insulating film 14. The wiring electrodes 17 and 18 having predetermined widths in contact with each other are formed to manufacture an antifuse device.
상술한 종래 기술에서는 활성층(13)과 알루미늄으로 형성된 전극(17, 18) 사이에 열적으로 성장시킨 열산화막(16a, 16b)을 형성시킴으로서 다음과 같은 문제점이 발생한다.In the above-described prior art, thermally grown thermal oxide films 16a and 16b are formed between the active layer 13 and the electrodes 17 and 18 formed of aluminum, and the following problems occur.
즉, 활성층(13)으로 형성된 다결정 실리콘은 그 자체의 저항을 낮추기 위해 고농도의 불순물이 도핑되어 있으므로 다결정 실리콘 위에 실리콘 산화막을 성장시킬 때 다결정 실리콘의 거친 표면상태에 의해 그 두께 조정이 매우 어려우며 형성된 실리콘의 거친 표면상태에 의해 그 두께 조정이 매우 어려우며 형성된 실리콘 산화막의 표면 평탄도가 불량하여 설계된 프로그래밍 전압에 따라 안티퓨즈 소자가 구동되지 않을 수도 있다.That is, since the polycrystalline silicon formed of the active layer 13 is doped with a high concentration of impurities in order to lower its resistance, it is very difficult to adjust the thickness due to the rough surface state of the polycrystalline silicon when growing the silicon oxide film on the polycrystalline silicon. It is very difficult to adjust the thickness due to the rough surface condition of, and the surface flatness of the formed silicon oxide film is poor, so the antifuse device may not be driven depending on the designed programming voltage.
또한, 알루미늄 전극(채널)이 형성될 활성층(13)을 다결정실리콘을 이용하여 소자를 제조하였으므로 결정화 및 활성화를 위해 높은 열처리온도를 요하는 단점이 있다.In addition, since the device is manufactured using polycrystalline silicon, the active layer 13 on which the aluminum electrode (channel) is to be formed has a disadvantage of requiring a high heat treatment temperature for crystallization and activation.
따라서, 상술한 종래 기술의 문제점을 해결하기 위한 본 발명은 활성층의 금속을 열처리온도가 낮은 물질로 활성층을 형성하며, 낮고 균일한 절연파괴전압을 갖는 절연막을 활성층과 전극사이에 형성하여 안티퓨즈소자의 구동을 위한 입력 에너지의 손실을 줄일수 있는 안티퓨즈 소자를 제조하는 방법을 제공함에 있다.Accordingly, the present invention for solving the above-described problems of the prior art forms an active layer of a material having a low heat treatment temperature of a metal of the active layer, and forms an insulating film having a low and uniform dielectric breakdown voltage between the active layer and the electrode to form an antifuse device. It is to provide a method for manufacturing an anti-fuse device that can reduce the loss of input energy for driving of.
상술한 종래 기술의 문제점을 해결하기 위한 본 발명은 반도체 기판상에 제1절연막과 Si1-xGex을 차례로 형성하는 공정과, 상기 Si1-xGex을 사진식각법으로 패터닝하여 소정의 폭을 갖는 활성층을 형성하는 공정과, 상기 제1절연막과 활성층의 전면에 층간절연막으로서 제2절연막을 형성한 후 이를 사진식각법으로 패터닝하여 상기 활성층의 양단을 소정의 폭으로 노출시키는 접촉창을 형성하는 공정과, 상기 접촉창에 의해 노출된 활성층의 표면에 제3절연막을 형성하는 공정과, 상기 제3절연막과 제3절연막의 전면에 도전승금속을 증착한 후 이를 사진식각법으로 패터닝하여 소정의 폭을 갖는 배선전극을 형성하는 공정을 포함하는 것을 특징으로 한다.The present invention for solving the above-described problems of the prior art is a step of sequentially forming a first insulating film and Si1- x Gex on a semiconductor substrate, and patterning the Si1- x Gex by photolithography to an active layer having a predetermined width Forming a second insulating film as an interlayer insulating film on the front surface of the first insulating film and the active layer, and then patterning the second insulating film by photolithography to form contact windows exposing both ends of the active layer to a predetermined width; Forming a third insulating film on the surface of the active layer exposed by the contact window; depositing a conductive metal on the entire surface of the third insulating film and the third insulating film, and then patterning the conductive insulating metal by photolithography to form a predetermined width. It is characterized by including the process of forming the wiring electrode which has.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
제2a도 내지 제2f도는 본 발명에 다른 안티퓨즈 소자 제조방법을 나타낸 공정단면도이다.2A to 2F are process cross-sectional views showing a method for manufacturing an antifuse device according to the present invention.
제2a도 내지 제2f도를 참조하여 본 발명의 실시예를 설명하면 다음과 같다.An embodiment of the present invention will be described with reference to FIGS. 2A through 2F.
제2a도를 참조하면, 실리콘기판(21) 상에 후속 형성되는 도전성금속과 기판의 절연을 위해 560nm 의 두께로 열산화막인 제1절열막(22)을 형성한다. 단, 상기 열산화막을 CVD 법에 의해 형성되는 CVD 산화막으로 대체될 수도 있다.Referring to FIG. 2A, a first thermal insulation film 22, which is a thermal oxide film, is formed to a thickness of 560 nm to insulate the substrate and the conductive metal subsequently formed on the silicon substrate 21. However, the thermal oxide film may be replaced with a CVD oxide film formed by the CVD method.
이어서, 제2b 도에 도시한 바와 같이, MBE 장치를 이용하여 580℃ 의 온도에서 1A°/sec 의 성장속도로 250nm 의 두께를 갖는 Si1-xGex 막(23a), 바람직하게는 Si0.75Ge0.25막을 형성한 후 상기 Si1-xGex막에 60 KeV의 에너지로 1×1015cm-2의 농도를 갖는 BF₂를 이온주입한다.Subsequently, as shown in FIG. 2B, a Si1-xGex film 23a, preferably a Si 0.75 Ge 0.25 film, having a thickness of 250 nm at a growth rate of 1 A ° / sec at a temperature of 580 ° C. was used using an MBE apparatus. After the formation, the Si 1-x Ge x film was implanted with BF 2 having a concentration of 1 × 10 15 cm −2 at an energy of 60 KeV.
이어서, 제2c도에 도시한 바와 같이, 상기 Si1-xGex막(23a)을 사진식각법으로 소정의 폭을 갖도록 건식식각하여 활성층(23)을 형성한다.Subsequently, as shown in FIG. 2C, the Si 1-x Ge x film 23a is dry-etched to have a predetermined width by a photolithography method to form the active layer 23.
이어서, 제2d도에 도시한 바와 같이, CVD 장치를 이용하여 상기 제1절연막(22)과 활성층(23)의 전면에 600nm의 두께를 갖는 TEOS 와 BPSG를 차례로 증착하여 층간절연막으로서 제2절연막(24)을 형성하고 상기 제2절연막(24)을 사진식각법으로 패터닝하여 상기 활성층(23)의 양단면 부분이 소정의 폭으로 각각 노출되도록 접촉창(30, 31)을 형성한다.Subsequently, as shown in FIG. 2D, TEOS and BPSG having a thickness of 600 nm are sequentially deposited on the front surfaces of the first insulating film 22 and the active layer 23 using a CVD apparatus, thereby forming a second insulating film as an interlayer insulating film ( 24 is formed and the second insulating layer 24 is patterned by photolithography to form contact windows 30 and 31 such that both end portions of the active layer 23 are exposed to predetermined widths, respectively.
이어서, 제2e도를 참조하면, 상기 제2d도의 구조체상에 680℃ 의 온도에서 100 nm 의 두께를 갖는 TEOS 막을 형성한 후 이를 900℃의 N₂개스 분위기에서 열처리하고 이를 사진식각법으로 패터닝하여 접촉창(30, 31)에 의해 노출된 활성층(23) 상에 제3절연막(25, 26)을 형성한다.Subsequently, referring to FIG. 2e, a TEOS film having a thickness of 100 nm is formed on the structure of FIG. 2d at a temperature of 680 ° C., and then heat-treated in an N 2 gas atmosphere at 900 ° C. and patterned by a photolithography method. Third insulating layers 25 and 26 are formed on the active layer 23 exposed by the windows 30 and 31.
그 다음, 제2f도에 도시한 바와 같이, 상기 제2절연막(24)과 제3절연막(25)의 전면에 알루미늄을 증착한후 이를 사진식각법으로 패터닝하여 상기 제3절연막(25)과 상기 제2절연막(24)상에 접촉되며 소정의 폭을 갖는 전극(27, 28)을 형성하여 안티퓨즈 소자를 제조한다.Next, as shown in FIG. 2F, aluminum is deposited on the entire surface of the second insulating layer 24 and the third insulating layer 25, and then patterned by photolithography to form the third insulating layer 25 and the third insulating layer 25. The anti-fuse device is manufactured by forming electrodes 27 and 28 in contact with the second insulating film 24 and having a predetermined width.
이와 같이 제조된 본 발명의 평면형 안티퓨즈 소자는, 전극 양단에 인가된 에너지로 전극물질인 알루미늄이 용해되어 상기 제3절연막(TEOS 막), (25, 26)을 통과하여 SiSe 활성층(23)의 걸정 경계를 따라서 확산되어 활성영역에 얇은 알루미늄 필라멘트가 형성됨으로써 안티퓨즈 소자가 프러그래밍(ON 상태)이 되어 많은 전류가 흐르게 된다.In the planar antifuse device of the present invention, aluminum, which is an electrode material, is dissolved by energy applied at both ends of the electrode to pass through the third insulating film (TEOS film) and (25, 26) to form the SiSe active layer 23. As the aluminum filaments are diffused along the edges to form a thin aluminum filament in the active region, the anti-fuse device is programmed (ON state) and a large amount of current flows.
이와 같은 본 발명의 안티퓨즈 소자는 제3도 및 제4도와 같은 특성을 갖는다.Such an antifuse device of the present invention has the characteristics as shown in FIGS. 3 and 4.
제3도는 종래의 기술과 본원 발명의 안티퓨즈 소자의 전극에 전압을 인가했을 때 각각 활성층인 폴리실리콘(a)과 Si1-xGex막에 흐르는 전류의 분포를 나타낸 그래프이다.3 is a graph showing the distribution of currents flowing in the polysilicon (a) and the Si 1-x Ge x film as active layers, respectively, when voltage is applied to the electrodes of the prior art and the antifuse device of the present invention.
제3도에서 알 수 있는 바와 같이, 종래기술과 본원 발명의 안티퓨즈 소자모두에 5.5 V에서 누설전류는 0.1 pA 이하로 양호하며 절연막의 파괴전압은 대략 10V 전후였지만 다결정실리콘을 사용한 종래의 안티퓨즈 소자의 절연파괴전압이 약간 높았다.As can be seen in FIG. 3, both the prior art and the antifuse device of the present invention have a leakage current of less than 0.1 pA at 5.5 V, and the breakdown voltage of the insulating film was about 10 V, but the conventional antifuse using polycrystalline silicon The breakdown voltage of the device was slightly higher.
이는 활성층인 Si0.75Ge0.25층위에 성장시킨 제3절연막(25, 26) 내에 분포된 결함밀도가 높기 대문이며 이러한 현상을 두 절연막의 Fowler-Nordheim 터널링영역에서도 관찰되었다.This is because the defect density distributed in the third insulating films 25 and 26 grown on the Si 0.75 Ge 0.25 layer, which is an active layer, is high. This phenomenon was also observed in the Fowler-Nordheim tunneling region of the two insulating films.
즉, 다결정 실리콘 위에 제3절연막으로서 증착된 TEOS 막내에서는 F-N 터널링 형상이 나타나지만 Si0.75Ge0.25막위에 증착된 제3절연막(25, 26)인 TEOS 막에서는 제3도에서 처럼 TEOS 막내의 결함으로 인한 전류가 발행한다.That is, in the TEOS film deposited as the third insulating film on the polycrystalline silicon, the FN tunneling shape appears, but in the TEOS film, which is the third insulating films 25 and 26 deposited on the Si 0.75 Ge 0.25 film, due to defects in the TEOS film as shown in FIG. Current is issued.
제4도는 본 발명에 의해 제조된 소자에 정 전압펄스를 인가하여 프로그래밍 시킨 후 측정된 소자의 저항분포를 나타낸 것이다.Figure 4 shows the resistance distribution of the device measured after programming by applying a constant voltage pulse to the device manufactured by the present invention.
이때 인가된 전압 및 전류는 15V와 15mA로서 1ms 동안 지속되도록 하였으며, 소자 양단을 흐르는 전류는 외부저항을 측정회로에 연결시켜 조정하였다.At this time, the applied voltage and current were 15V and 15mA so as to last for 1ms, and the current flowing through the device was adjusted by connecting an external resistance to the measurement circuit.
이때 측정된 저항값을 대략 16-18Ω 정도로 낮게 나타났다.At this time, the measured resistance value was as low as about 16-18Ω.
이상의 실험결과로부터 알수 있는 바와 같이 Si0.75Ge0.25막을 이용하고 절연막으로 TEOS 막을 이용하여 제조된 안티퓨즈 소자는 종래의 열적으로 성장시킨 실리콘 산화막과 매우 높게 도핑된 다결정 실리콘을 이용하여 제조된 안티퓨즈 소자와 비교할 때 절연막의 두께 조절이 용이하고 저전류에서 프로그래밍이 가능하며 결과적으로 프로그래밍후의 낮은 저항값을 얻을 수 있는 장점이 있다.As can be seen from the above experimental results, an anti-fuse device manufactured using a Si 0.75 Ge 0.25 film and a TEOS film as an insulating film is an anti-fuse device manufactured using a conventionally grown silicon oxide film and a very highly doped polycrystalline silicon. Compared with, it is easy to adjust the thickness of the insulating film, it is possible to program at low current, and as a result, it is possible to obtain a low resistance value after programming.
또한 알루미늄 채널이 형성될 활성층영역으로 기존의 다결정 실리콘층 대신에 Si1-xGex막을 사용함으로써 종래 기술의 다결정실리콘층의 열 처리온도(활성화 에너지, 재결정화, 용융온도) 보다 낮은 온도에서 열처리가 가능하여 결과적으로 프로그래밍 전압을 낮출 수 있다.In addition, the Si 1-x Ge x film is used instead of the existing polycrystalline silicon layer as the active layer region where the aluminum channel is to be formed. It is possible to lower the programming voltage as a result.
따라서, 본 발명의 안티퓨즈 소자는 활성층위에 형성되는 절연막의 평탄도 및 두께 조절이 용이하므로 프로그래밍 전압을 낮출 수 있다.Therefore, the antifuse device of the present invention can easily control the flatness and thickness of the insulating film formed on the active layer, thereby lowering the programming voltage.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950049253A KR100216544B1 (en) | 1995-12-13 | 1995-12-13 | Method of manufacturing planar antifuse device |
| JP8333983A JP2863767B2 (en) | 1995-12-13 | 1996-12-13 | Manufacturing method of planar antifuse element |
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| KR1019950049253A KR100216544B1 (en) | 1995-12-13 | 1995-12-13 | Method of manufacturing planar antifuse device |
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| KR100954417B1 (en) | 2002-12-23 | 2010-04-26 | 매그나칩 반도체 유한회사 | Fuse formation method of semiconductor device |
| KR102749319B1 (en) | 2023-01-04 | 2025-01-03 | (주)스페이스엔지니어링 | All-season moving belt system |
| KR102802011B1 (en) | 2023-01-04 | 2025-05-02 | (주)스페이스엔지니어링 | Sledding range tube transfer device |
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