KR100213199B1 - Fabrication method of a non-volatile semiconductor memory device - Google Patents

Abstract

Provided are a method of manufacturing a nonvolatile semiconductor memory device which is easy to manufacture and can prevent an increase in contamination. An aspect of the present invention is to form a device isolation region defining an active region in a semiconductor substrate, and to form a tunnel oxide film in the active region. A first conductive film is formed on the entire surface of the semiconductor substrate including the tunnel oxide film, and the first conductive film is photo-etched to isolate each other in each string unit in the cell array region, and to expose the peripheral circuit region and the portion where the selection transistor is to be formed. A conductive film pattern is formed. An insulating film is formed on the entire surface of the semiconductor substrate including the first conductive film pattern, an insulating film pattern surrounding the first conductive film pattern is formed by a photolithography process, and peripheral regions and active regions of the selection transistors are formed. Expose A first gate oxide layer is formed on the exposed active region, and the first gate oxide layer is etched in a portion of the peripheral circuit region to expose the active region in the portion of the peripheral circuit region. A second gate oxide film is formed on the exposed active region and the first gate oxide film, and a second conductive film is formed on the entire surface of the semiconductor substrate including the second gate oxide film. A control gate electrode and a floating gate electrode are formed on a portion where the first conductive film pattern is formed by using a photolithography process, and a gate electrode of a peripheral circuit region and a selection transistor is formed from the second conductive film.

Description

Nonvolatile Semiconductor Memory Manufacturing Method

1 is a layout diagram used for manufacturing a conventional nonvolatile semiconductor memory device.

2 and 3 are cross-sectional views of the nonvolatile semiconductor memory device cut along the AA 'line and the BB' line in FIG. 1, respectively.

4 is a cross-sectional view showing a nonvolatile semiconductor memory device having a structure that can be easily manufactured according to the present invention.

5 to 10 are diagrams sequentially showing a method of manufacturing the nonvolatile semiconductor memory device of the present invention.

11 through 16 are diagrams sequentially showing another method of manufacturing the nonvolatile semiconductor memory device of the present invention.

* Explanation of symbols for main parts of the drawings

31 semiconductor substrate 35 floating gate electrode

37 control gate electrode 39 insulating film

41 tunnel oxide layer 51 device isolation region

55: active area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly, to a method of manufacturing a nonvolatile semiconductor memory device which is easy to manufacture and which can prevent an increase in contamination.

BACKGROUND OF THE INVENTION Nonvolatile semiconductor memory devices capable of reading or programming memory information are well known. In particular, the flash EEPROM that can erase all the information of the memory array cell in a short time by using an electrical signal is actively researched.

A cell of such a nonvolatile semiconductor memory device has a memory transistor including a floating gate electrode electrically floating and a control gate electrode applied as a word line, and the storage information is stored in the floating gate electrode. It depends on the state of charge.

Hereinafter, a conventional nonvolatile semiconductor memory device will be described in detail.

FIG. 1 is a layout diagram used to manufacture a conventional nonvolatile semiconductor memory device, and FIGS. 2 and 3 are cross-sectional views of the nonvolatile semiconductor memory device taken along the AA 'and BB' lines of FIG. 1, respectively. admit.

In detail, the active region on the semiconductor substrate 1 is defined by the field oxide film 3, and the memory cells and the selection transistors in the cell array region are insulated over the floating gate electrode 5 and the floating gate electrode 5. It has the two-layer structure of the control gate electrode 7 formed through (9). In this case, the floating gate electrode 5 and the control gate electrode 7 of the selection transistor are electrically connected through a butting contact window 11.

In addition, the floating gate electrode 7 of the memory cell is formed in the active region through the tunnel oxide film 15, and the floating gate electrode 7 of the selection transistor is formed through the first gate oxide film 13. It is formed over the active area.

In the peripheral circuit region (not shown), a control circuit operating at a high voltage and a control circuit operating at a low voltage are fabricated. For this purpose, a transistor formed of a gate oxide film having a different thickness is formed.

A method of manufacturing a conventional nonvolatile semiconductor memory device will be described in detail with reference to FIGS. 1 to 3 above.

A well region is formed in the cell array region and the peripheral circuit region of the semiconductor substrate 1 by using an ion implantation process and a diffusion process, and a field oxide film 3 defining an active region for device isolation is formed. Subsequently, the first gate oxide layer 13 is formed on the entire surface of the resultant to have a thickness of, for example, about 300 GPa for use as a gate oxide layer of a selection transistor that operates when the cell array region is selected in block or string units. .

In addition, the first gate oxide layer of the portion of the first gate oxide pattern 21 formed in the cell array region by a photolithography process to form a tunnel oxide layer 15 to be used as a path for tunneling charges during the operation of the cell array region. (13) is etched to clean the semiconductor substrate 1 with its surface exposed. A tunnel oxide film 15 is grown on the surface of the semiconductor substrate 1, and a first polycrystalline silicon film for successively forming the floating gate electrode 5 is deposited on the tunnel oxide film 15.

In addition, in order to separate the floating gate electrodes from each other in the cell array region, the first polycrystalline silicon layer of the separation pattern 23 is etched by a photolithography process.

An insulating film 9 is formed on the entire surface of the resultant, and the insulating film 9 and the first polycrystalline silicon film of the peripheral circuit region are etched using a photolithography process. At this time, the insulating film is formed in a three-layer structure of oxide film / nitride film / oxide film.

Subsequently, an impurity is ion implanted for the transistor to be formed in the peripheral circuit region, and the first gate oxide layer 13 remaining in the peripheral circuit region is etched.

For the transistor to be used for the control circuit operating at high voltage in the peripheral circuit region, a second gate oxide film is grown on the front surface of the semiconductor substrate, for example, about 250 kV thick, and operated at a low voltage in the peripheral circuit region. The second gate oxide layer of the control circuit portion is etched by the photolithography process. Subsequently, a third gate oxide film for use as a gate oxide film of a control circuit operating at a low voltage is formed on the entire surface of the resultant, for example, at a thickness of about 180 kPa. At this time, the thickness of the portion where the second gate oxide film is formed is about 350 kPa as a result.

Subsequently, a second polycrystalline silicon film to be used as a control gate is formed on the entire surface of the resultant, and a control gate electrode 7 and a floating gate electrode 5 are formed according to the gate pattern 25 using a photolithography process.

In the above, the manufacturing method of the nonvolatile semiconductor memory device by the conventional method was demonstrated.

However, the silicon oxide film used as the gate oxide film of the transistor in the conventional method has a disadvantage in the process complexity when forming the three types of the first gate oxide film, the second gate oxide film, and the third gate oxide film, respectively. In particular, the nonvolatile semiconductor memory device includes a tunnel oxide film, which eventually grows four gate oxide films, which makes the process more complicated, thereby reducing productivity and yield.

In addition, contamination of the nonvolatile semiconductor memory device may increase due to the repetition of the photolithography process for partially etching the first selection gate oxide film and the second gate oxide film, and thus, the reliability of the device may be degraded.

Accordingly, an object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device which is easy to manufacture and can prevent an increase in contamination in order to solve the above problems.

In order to achieve the above object, an aspect of the present invention, forming a device isolation region defining an active region in the semiconductor substrate; Forming a tunnel oxide layer in the active region; Forming a first conductive film on an entire surface of the semiconductor substrate including the tunnel oxide film; Photo-etching the first conductive film to form a first conductive film pattern separated from each other in each cell unit in the cell array region and exposing a portion in which a peripheral circuit region and a selection transistor are to be formed; Forming an insulating film on an entire surface of the semiconductor substrate including the first conductive film pattern; Forming an insulating layer pattern surrounding the first conductive layer pattern by a photolithography process, exposing the peripheral circuit region and an active region of a portion where the selection transistor is to be formed; Forming a first gate oxide layer on the entire surface of the resultant exposed portion of the active region; Etching the first gate oxide layer in a portion of the peripheral circuit region to expose an active region in the portion of the peripheral circuit region; Forming a second gate oxide layer on the entire surface of the exposed active region and the resultant first gate oxide layer; Forming a second conductive film on an entire surface of the semiconductor substrate including the second gate oxide film; Forming a control gate electrode and a floating gate electrode on a portion where the first conductive film pattern is formed by using a photolithography process; And forming a gate electrode of a peripheral circuit region and a selection transistor in the second conductive layer by using a photolithography process.

Preferably, the first conductive film includes a polycrystalline silicon film, and the insulating film is formed in a multilayer including a silicon oxide film and a silicon nitride film. The second conductive film is formed in a multilayer including a silicide film and a polycrystalline silicon film.

In addition, another aspect of the invention, forming a device isolation region defining an active region in the semiconductor substrate; Forming a tunnel oxide layer in the active region; Forming a first conductive film on an entire surface of the semiconductor substrate including the tunnel oxide film; Photo-etching the first conductive film to form a first conductive film pattern covering a portion in which a peripheral circuit region and a selection transistor are formed and separating the first conductive film from each other in a string unit in the device isolation region; Forming an insulating film on an entire surface of the semiconductor substrate including the first conductive film pattern; Photo-etching the first conductive layer pattern and the insulating layer to form a first conductive layer pattern separated from each other in each cell unit in the cell array region, and exposing an active region of the peripheral circuit region and a portion where the selection transistor is formed. Doing; Forming a first gate oxide layer on the entire surface of the resultant exposed portion of the active region; Etching the first gate oxide layer in a portion of the peripheral circuit region to expose the active region in the portion of the peripheral circuit region; Forming a second gate oxide layer on the entire surface of the exposed active region and the resultant first gate oxide layer; Forming a second conductive film on an entire surface of the semiconductor substrate including the second gate oxide film; Forming a control gate electrode and a floating gate electrode on a portion where the first conductive film pattern is formed by using a photolithography process; And forming a gate electrode of a peripheral circuit region and a selection transistor in the second conductive layer by using a photolithography process.

The nonvolatile semiconductor memory device of the present invention has the advantage that the gate electrode of the selection transistor is formed of a single layer of the control gate electrode, thereby reducing the area required for forming a butting contact window. Therefore, the degree of integration can be improved.

In addition, the manufacturing method of the nonvolatile semiconductor memory device according to the present invention is carried out simultaneously with the formation of the gate oxide film for the peripheral circuits, omitting the process of separately forming the gate oxide film of the selection transistor. That is, the same effect can be achieved by forming the gate oxide film that has been conventionally performed three times by forming the two gate oxide films of the first gate oxide film and the second gate oxide film. Therefore, it has the effect of simplifying a process. Therefore, the effect of improving productivity is brought.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view showing a nonvolatile semiconductor memory device having a structure that can be easily manufactured by the present invention.

In detail, the active region on the semiconductor substrate 31 is defined by a field oxide film, and in the cell array region, the memory cell is interposed between the floating gate electrode 35 and the floating gate electrode 35 via an insulating film 39. Since the gate electrode of the selected transistor has a two-layer structure of the formed control gate electrode 37, the conventional butting contact window is not necessary because the gate electrode of the selection transistor is formed only of the control gate electrode 37.

In addition, the floating gate electrode 35 of the memory cell is formed in the active region via the tunnel oxide film 41, and the selection gate electrode 44 of the selection transistor is active through the first gate oxide film 43. It is formed over the area.

In the peripheral circuit region (not shown), a control circuit operating at a high voltage and a control circuit operating at a low voltage are fabricated. For this purpose, a transistor formed of a gate oxide film having a different thickness is formed.

The nonvolatile semiconductor memory device of the present invention has the advantage that the gate electrode of the selection transistor is formed of a single layer of the control gate electrode, thereby reducing the area required for forming a butting contact window. Therefore, the degree of integration can be improved.

In addition, since the first gate oxide film is formed at the same time as the gate oxide film of the transistor operating at a high voltage in the peripheral circuit region, the process is easy.

Next, the manufacturing method of the nonvolatile semiconductor memory device according to the present invention will be described in detail.

[First Embodiment]

5 to 10 are diagrams sequentially showing a method of manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 5 is a layout diagram showing the arrangement of the first conductive film pattern and the insulating film pattern in the cell array region, and FIG. 6 is a cross-sectional view taken along the line A1A1 'of FIG.

In detail, a well region is formed in the cell array region and the peripheral circuit region of the semiconductor substrate 31 by using an ion implantation process and a diffusion process, and a field oxide film (not shown) is formed in the device isolation region 51. To define the active region 55. Subsequently, a tunnel oxide film 41 is grown on the entire surface of the resultant product, and a first conductive film to be used later as a floating gate electrode is formed on the tunnel oxide film 41. At this time, the first conductive film is formed of, for example, a polycrystalline silicon film containing impurities.

By using a photolithography process, the first conductive layer is formed to etch the remainder while leaving only a portion of the memory cell, and to form a first conductive layer pattern 57 for separating the floating gate electrodes to be formed in the cell array region from each string. do. Accordingly, the first conductive layer pattern 57 exposes a peripheral circuit region (not shown) and a portion where the selection transistor is to be formed.

An insulating film is formed on the entire surface of the resultant product, and an insulating film pattern 59 is formed to surround the first conductive film pattern 57 by using a photolithography process. In this case, the insulating film is formed in a three-layer structure of an oxide film, a nitride film, and an oxide film, and the tunnel oxide film 41 exposed to portions except the insulating film pattern 59 is also etched. Accordingly, the peripheral circuit region and the active region of the portion where the selection transistor is to be formed are exposed.

FIG. 7 is a layout diagram illustrating a first gate pattern for forming a floating gate electrode and a control gate electrode in the cell array region, and FIG. 8 is a cross-sectional view taken along the line A2A21 'of FIG.

Impurities are implanted into the peripheral circuit region (not shown in the figure), and a first gate oxide film is formed on the front surface of the semiconductor substrate for the transistor to be used in the control circuit operating at high voltage in the peripheral circuit region. For example, it grows to a thickness of about 250Å.

In addition, the first gate oxide layer of the control circuit portion to be operated at the low voltage in the peripheral circuit region is etched by a photolithography process. Subsequently, a second gate oxide film for use as a gate oxide film of a control circuit operating at a low voltage is grown to a thickness of, for example, about 180 kPa on the entire surface of the resultant product. At this time, the thickness of the portion where the first gate oxide film is formed is about 350 kPa as a result.

In this case, the first gate oxide film and the second gate oxide film overlap with the gate oxide film 43 of the selection transistor in the cell array region and are formed together.

A second conductive film to be used as a gate electrode is formed on the entire surface of the resultant product. In this case, the second conductive film is formed of, for example, a two-layer structure of a polycrystalline silicon film and a silicide film.

Subsequently, the second conductive layer is etched according to the first gate pattern 63 by a photolithography process to form a control gate electrode serving as a word line in the memory cell portion, and at the same time, the first conductive layer pattern is also etched. The control gate electrode 37 and the floating gate electrode 35 are formed.

FIG. 9 is a layout diagram illustrating a second gate pattern for forming a gate electrode of a selection transistor and a peripheral circuit region, and FIG. 10 is a cross-sectional view taken along the line A3A3 'of FIG.

In detail, the second conductive layer is etched according to the second gate pattern 65 to form the gate electrode of the peripheral circuit region and the gate electrode of the selection transistor of the cell array region. Is formed on the gate oxide film 43 of the select transistor. At this time, the gate electrode of the transistor of the peripheral circuit is also formed at the same time to complete the nonvolatile semiconductor memory device of the present invention.

Second Embodiment

11 through 16 are diagrams sequentially showing another method of manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 11 is a layout diagram illustrating an arrangement of separation patterns for separating floating gate electrodes in a cell array region, and FIGS. 12 and 13 are cross-sectional views taken along lines C1C1 'and D1D1', respectively, in FIG.

In detail, the well region is formed in the cell array region and the peripheral circuit region of the semiconductor substrate 31 by using an ion implantation process and a diffusion process, and the field oxide film 53 is formed in the device isolation region 51 to form an active region. Area 55 is defined. Subsequently, a tunnel oxide film 41 is grown on the entire surface of the resultant product, and a first conductive film to be used later as a floating gate electrode is formed on the tunnel oxide film 41. At this time, the first conductive film 67 is formed of, for example, a polycrystalline silicon film containing impurities.

By using a photolithography process, the first conductive layer 67 may be formed by separating the floating gate electrodes to be formed in the cell array region with each string. Etch some. At this time, the first dozer film remains in the peripheral circuit region and the portion where the selection transistor is to be formed.

FIG. 14 is a layout diagram showing an arrangement of a first dozer film pattern leaving a portion where a floating gate electrode is to be formed in a cell array region, and FIGS. 15 and 16 are taken along lines C2C2 'and D2D2', respectively, in FIG. These are the cut sections.

An insulating film is formed on the entire surface of the resultant product, and a first conductive film is etched by etching the insulating film and the first conductive film 67 formed in the region of the peripheral circuit region except the memory cell portion and the region where the selection transistor is to be formed by using a photolithography process. The film pattern 73 is formed. In this case, the insulating film is formed in a three-layer structure of an oxide film, a nitride film, and an oxide film, and the tunnel oxide film 41 exposed to portions except the first conductive film pattern 73 is also etched.

Subsequent processes proceed in the same manner as those in FIG. 7 and subsequent to the first embodiment to complete the nonvolatile semiconductor memory device of the present invention.

As described above, the manufacturing method of the nonvolatile semiconductor memory device according to the present invention is performed simultaneously with the formation of the gate oxide film for the peripheral circuits, omitting the step of separately forming the gate oxide film of the selection transistor. That is, the same effect can be achieved by forming the gate oxide film that has been conventionally performed three times by forming the two gate oxide films of the first gate oxide film and the second gate oxide film. Therefore, it has the effect of simplifying a process. Therefore, the effect of improving productivity is brought.

In addition, this eliminates the photolithography process performed before the tunnel oxide film is formed, and has the effect of increasing the reliability of the tunnel oxide film since the process of forming the tunnel oxide film is performed in a state of low contamination.

In the conventional case, a process of forming a butting contact window is added by using a two-layer conductive film as the gate electrode of the selection transistor. However, in the present invention, the process is performed because the gate electrode of the selection transistor is formed of one conductive film. It is easy. In addition, it brings about the effect of increasing the degree of integration.

As mentioned above, the present invention has been described in detail by way of examples, but the present invention is not limited thereto, and modifications and improvements of the present invention may be made with ordinary knowledge within the technical spirit of the present invention.

Claims (3)

Forming a device isolation region defining an active region in the semiconductor substrate; Forming a tunnel oxide layer in the active region; Forming a first conductive film on an entire surface of the semiconductor substrate including the tunnel oxide film; Photo-etching the first conductive film to form a first conductive film pattern separated from each other in each cell unit in the cell array region and exposing a portion in which a peripheral circuit region and a selection transistor are to be formed; Forming an insulating film on an entire surface of the semiconductor substrate including the first conductive film pattern; Forming an insulating film pattern surrounding the first conductive film pattern by a photolithography process, exposing a peripheral circuit region and a portion where a selection transistor is formed; Forming a first gate oxide layer on the exposed peripheral circuit region and the active region of the portion where the selection transistor is to be formed; Etching the first gate oxide layer in a portion of a peripheral circuit region; Forming a second gate oxide film on the entire surface of the resultant product; Forming a second conductive film on an entire surface of the semiconductor substrate including the second gate oxide film; Forming a control gate electrode and a floating gate electrode on the first conductive film pattern portion using a photolithography process; And forming a gate electrode of a peripheral circuit region and a selection transistor in the second conductive film by using a photolithography process. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the insulating film is formed in a multilayer including a silicon oxide film and a silicon nitride film. Forming a device isolation region defining an active region in the semiconductor substrate; Forming a tunnel oxide layer in the active region; Forming a first conductive film on an entire surface of the semiconductor substrate including the tunnel oxide film; Photo-etching the first conductive film to form a first conductive film covering a portion in which a peripheral circuit region and a selection transistor are formed and separating each other in each string unit in the device isolation region; Forming an insulating film on an entire surface of the semiconductor substrate including the first conductive film; Photo-etching the first conductive layer and the insulating layer to form a first conductive layer pattern separated from each other in each cell unit in the cell array region, and exposing portions of the peripheral circuit region and the selection transistor to be formed; Forming a first gate oxide layer on the exposed peripheral circuit region and the active region of the portion where the selection transistor is to be formed; Etching the first gate oxide layer in a portion of a peripheral circuit region; Forming a second gate oxide layer on the entire surface of the resultant product; Forming a second conductive film on an entire surface of the semiconductor substrate including the second gate oxide film; Forming a control gate electrode and a floating gate electrode on the first conductive film pattern portion using a photolithography process; And forming a gate electrode of a peripheral circuit region and a selection transistor in the second conductive film by using a photolithography process.