KR100213056B1 - Receiver having analog and digital video mode and receiving method thereof - Google Patents

Abstract

The present invention is a receiver having an analog video mode and a digital video mode, according to the mode selection signal indicating the TV channel of the analog video mode or the TV channel of the digital video mode, the Y / C separation in the analog video mode, for improving the image quality By sharing the frame memory required for processing with the large memory required for digital video decoding, the efficiency of the memory can be increased and the system cost can be reduced.

Description

Receiver having analog and digital video mode and receiving method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver having analog and digital video modes and a method of receiving the same, and more particularly to a receiver sharing a memory for processing digital television (hereinafter referred to as a TV) signal in analog video mode and a method of receiving the same.

Digital video mode refers to the reception of TV signals digitally processed by the Moving Picture Experts Group (MPEG) standard from a transmitter (e.g. broadcasting station). Analog video mode refers to conventional broadcasting methods such as NTSC, PAL, or SECAM. According to this means receiving an analog processed signal.

Although set-top boxes (STBs) or digital TVs with built-in top-boxes that decode bitstreams encoded by MPEG-2 are being developed, existing analog video services are also expected to be implemented for some time.

To deal with this situation, TV receivers have adopted both analog and digital video modes. TV receivers with analog and digital video modes require 8-32 Mbits of memory to decode digital TV signals. In analog video mode, 8-32 Mbits of large capacity memory for digital video decoding is not used. Do not.

Meanwhile, as shown in FIG. 1, a receiver having an existing analog video mode selects a signal of a TV channel desired by a user from among signals of analog TV channels transmitted from a transmitter (not shown) in the tuner 11. Output as frequency (hereinafter referred to as IF) signal.

The channel demodulator 12 amplifies the IF signal of the channel selected by the tuner 11. (Here, the video signal and the sound signal are separated from the amplified signal, but for the sake of simplicity of the drawings and the specification, only the video signal processing will be shown and mentioned.)

The luminance / color (Y / C) separator 13 separates the Y signal and the C signal from the video signal output from the channel demodulator 12. In this case, Y / C separation uses a correlation between a previous frame and a current frame stored in the frame memory 14 and / or a correlation between a current line and an adjacent line. The separated signal is stored in the frame memory 14 and input to the display connection unit 15.

The display connection unit 15 converts the Y and C signals output from the Y / C separator 13 into analog R, G, and B signals and outputs them to the display 16. In this case, the display is, for example, a receiving tube.

The tuner 11, the channel demodulator 12, and the Y / C separator 13 correspond to the analog TV signal processing unit 100. In addition, in order that the output of the channel demodulator 12 is stored as digital data in the frame memory 14, an analog / digital (A / D) converter for converting the output of the channel demodulator 12 into a digital signal form is further configured. In order for the output of the display connection unit 15 to be displayed on the display 16 as an analog signal, a D / A converter for converting the output of the display connection unit 15 into an analog signal form may be further configured.

On the other hand, when Y / C separation is performed using a comb filter in a conventional analog TV, Y / C separation may not be sufficient, resulting in problems such as cross color or cross luminance. In order to improve the image quality, the frame memory 14 is provided as described above in FIG. 1 to perform three-dimensional Y / C separation, which is often known as frame comb filtering.

In addition, the frame memory can also be used in the case of performing post-processing after Y / C separation in order to obtain better image quality. That is, the edge memory is emphasized by determining whether the edge component is determined by the correlation between the current frame and the previous frame using the frame memory.

As described above, many methods for effectively improving image quality require a considerable amount of memory, which increases the cost due to memory usage.

2 is a schematic block diagram of a digital TV receiving a conventional MPEG-2 encoded TV signal.

2, the tuner 21 selects a signal of a desired channel from a TV signal transmitted through an antenna. At this time, the TV signal transmitted through the antenna is input in the packet structure of MPEG-2.

In other words, in the MPEG-2 format, data on a transmission path includes packets of 188 bytes in a system layer. In addition, the packet structure includes video data, audio data, user data, and the like in other areas except header information and header information including sink and side information. Here, the video data is compressed by inter picture coding or intra picture coding.

Here, according to the inter picture coding, the predicted picture following the intra picture and the bidirectional predicted picture among 1 GOP (usually composed of 15 pictures) units encode only the difference between the picture to be encoded and the other picture to be encoded.

In one GOP, an intra (I) picture data that can be independently coded without any other picture data, and a predicated code that can be coded by using motion compensation between adjacent intra picture data from preceding intra picture data or predicated picture data (P). ) Bidirectional predicated (B) picture data which can be coded by using motion compensation from picture data, preceding intra picture data or predicated picture data and subsequent intra picture data or predicated picture data.

The channel demodulator 22 includes a QPSK demodulator, a Reed-Solomon decoder, a Viterbi decoder, and the like to convert a signal of a desired digital TV channel transmitted through the tuner 21 into an MPEG-2 bitstream.

The system decoder 23 splits the MPEG-2 bitstream back into audio and video data streams. Here, an audio decoder for decoding an audio signal output from the audio data stream and an audio signal processor for signal processing the decoded audio signal are preferably included, but are shown and mentioned only for video signal processing as shown in FIG. 1.

The video decoder 24 performs a variable length decoder for variable length decoding on a video data stream output from the system decoder 23, an inverse quantizer for inverse quantizing variable length decoded data, and performs an Inverse Discrete Cosine Transform (IDCT) operation. The compressed data including the IDCT actuator and the motion compensator for calculating the motion-prediction data are restored to the original video data and displayed on the display 27. Here, the display connection unit 26 performs a process of converting the restored video data into analog R, G, and B signals before being displayed on the display 27.

The memory 25 is used for video decoding (also called source-decoding) of digital video data performed in the video decoder 24.

In other words, since the video data stream output from the system decoder 23 has a constant bit rate, the memory 25 has a fixed bit rate (VBV) for converting it to a variable bit rate before variable length decoding. Buffering Verifier) (a so-called channel buffer) and a DCT block of a predetermined size corresponding to a motion vector is read from previous frame data, and the read block data and the inverse DCT data are added to compensate for motion to obtain P and B pictures. Include framebuffers to recover.

Thus, for decoding the video data stream, the memory 25 requires about 8-32 Mbits of memory for frame buffers and VBV buffers.

Here, the tuner 21, the channel demodulator 22, the system decoder 23, and the video decoder 24 correspond to the digital TV signal processor 200. In addition, the digital TV signal processing unit 200 and the memory 25 are referred to as STBs.

For quite some time, analog TV services such as NTSC and PAL will continue to exist, and consumer television systems must be able to display both analog and digital video services. There are two ways to anticipate:

As shown in Fig. 3, after all processing for the digital video service is performed in the STB 210, the restored video signal is also connected to the video input terminal of the existing analog TV 110, and also in the analog TV 110. It is being developed to receive digital video service.

As shown in FIG. 4, the TV has a digital TV signal processing unit 200 and a memory 25 that is developed to receive both an analog video service and a digital video service.

Therefore, as shown in Figs. 3 and 4, even in analog TV signal processing, frame memory is used for Y / C separation or post-processing for a predetermined image quality improvement, and when the television receives analog video service only. The massive memory of 8-32M bits for digital video decoding is not used.

There is always a certain amount of memory (8-32 Mbits) in a TV with a built-in digital video decoding function. When receiving an analog video service without receiving a digital video service, a large memory for this digital video decoding function is not used. There was a problem that inefficiency of using resources that already exist in the TV system occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a receiver having both analog and digital modes, in which the memory for digital video decoding in analog video mode is shared for analog television signal processing.

Another object of the present invention is to provide a receiving method for sharing a memory for digital video decoding in analog video mode for analog television signal processing.

The apparatus of the present invention for achieving the above object has an analog video mode for receiving an analog processed TV signal according to a predetermined analog broadcasting method and a digital video mode for receiving a digital signal processed by a predetermined digital signal format. A receiver having: first signal processing means for signal processing an analog TV signal received; Second signal processing means for decoding the received digital TV signal; A memory for storing data for decoding the digital TV signal in the second signal processing means and for processing the analog TV signal digitized in the first signal processing means; Generating means for generating a mode selection signal indicating an analog video mode or a digital video mode; And the memory to be used for writing and reading out a signal processed by the first signal processing means into the memory in analog video mode according to the mode selection signal and for writing / reading a digital TV signal in digital video mode. It characterized in that it comprises a memory control means for controlling the.

A method of the present invention for achieving the above another object is a method for receiving a TV signal digitally processed according to a predetermined digital signal format and an analog processed TV signal according to a predetermined analog broadcasting method: (a) to the user Generating a mode selection signal by determining whether the selected channel is a TV channel of an analog video mode or a TV channel of a digital video mode; And (b) storing the received digital TV signal in a digital video decoding memory in a digital video decoding memory according to the mode selection signal and decoding the data using the data stored in the memory. In the analog video mode, the received analog TV signal is received. Storing the data stored in the digital video decoding memory and reading and processing the data stored in the memory.

1 is a block diagram of a conventional analog TV.

2 is a block diagram of a conventional digital TV.

3 is a schematic diagram of a conventional analog TV with STB.

4 is a schematic diagram of a digital TV having a conventional analog video mode.

5 is a conceptual block diagram according to a first embodiment and a second embodiment of a receiver having analog and digital video modes according to the present invention.

6 is a detailed view of a memory controller according to a first embodiment of a receiver having analog and digital video modes according to the present invention.

7 is a block diagram according to a second embodiment of a receiver having analog and digital video modes according to the present invention.

8 is a block diagram according to a third embodiment of a receiver having analog and digital video modes according to the present invention.

9A to 9C are modifications of the third embodiment shown in FIG. 8.

10 is a block diagram according to a fourth embodiment of a receiver having analog and digital video modes according to the present invention.

FIG. 11 is a detailed block diagram of the analog processor shown in FIG. 10.

12A to 12C are modifications of the fourth embodiment shown in FIG.

FIG. 5 is a conceptual block diagram of a receiver having an analog and digital video mode according to the first and second embodiments of the present invention, as shown in FIGS. 6 and 7. The first and second embodiments are divided according to this.

In FIG. 5, since the configuration and operation of the analog TV signal processing unit 100 and the digital TV signal processing unit 200 are the same as those of FIGS. 1 and 2, the descriptions thereof will not be described herein.

The controller 310 determines whether the input channel key is a TV channel (hereinafter referred to as an analog TV channel) signal processed by a conventional analog broadcasting method or a TV channel digitally encoded with MPEG-2 (hereinafter referred to as a digital TV channel). Judgment outputs a mode selection signal indicating an analog video mode or a digital video mode.

The memory controller 320 selects one of the outputs processed by the analog TV signal processor 100 and the digital TV signal processor 200 according to the mode selection signal and writes it to the memory 330 or stores the memory 330 in the memory 330. The data is read and supplied to the analog TV signal processing unit 100 or the digital TV signal processing unit 200.

In the analog video mode, the signal processed by the analog TV signal processor 100 is displayed on the display 360 through the multiplexer 340 and the display connecting unit 350, and the digital TV signal processor 200 is processed in the digital video mode. The signal is displayed on the display 360 through the multiplexer 340 and the display connection unit 350.

Here, the multiplexer 340 supplies the image signal selected according to the mode selection signal output from the controller 310 to the display connection unit 350.

The memory 330 is used as a frame memory (or field memory) for Y / C separation and post-processing as described in FIG. 1 in the analog video mode, and fixed as described in FIG. 2 in the digital video mode. It is used as a VBV buffer for converting bit rate and frame buffer for motion compensation.

FIG. 6 is a detailed view of the memory controller shown in FIG. 5.

In FIG. 6, the memory input / output lines are shown as one for convenience, but the actual implementation may be configured for each input / output line. Here, the input / output line collectively refers to a data line, an address line, and a memory control line such as an enable, used to read or write data in the memory 330.

The memory controller 320 may be composed of a plurality of multiplexers 320.1-320.n serving as a switching role, and the first input terminals a ₁ -a _n of each multiplexer are analog TV signal processing units shown in FIG. 100 is connected to the input / output line, and the second input terminals b _{1 to} b _n are connected to the input / output line of the digital TV signal processing unit 200 shown in FIG. _1- c _n ) is connected to an input / output line of the memory 330 shown in FIG. 5.

Therefore, each multiplexer 320.1-320.n is used as a frame buffer for Y / C separation and post-processing when the mode selection signal output from the controller 310 shown in FIG. 5 indicates the analog video mode. In order to connect the input / output line of the memory 330 with the input / output line of the analog TV signal processing unit 100. On the contrary, each of the multiplexers 320.1-320.n uses the memory 330 as a VBV buffer for converting a fixed bit rate and a frame buffer for motion compensation when the mode selection signal indicates a digital video mode. ) Is connected to the input / output line of the digital TV signal processing unit 200.

Meanwhile, a receiver sharing a memory using a bus control scheme in analog and digital video modes is shown in FIG. 7.

In the bus control method, the function control units are connected to the control unit 410 through two common bus lines including a data line and a clock line capable of two-way data transmission connected to the data output terminals of the controller (microcomputer) and the clock output terminal. The control unit transmits an address and data through two common bus lines, and the transmitted address corresponds to a unique address of a given functional unit, and the function control unit refers to a method of performing a function according to the transmitted data. The introduction of the scheme into the television reduces the control wall of the control unit and shortens the signal processing time.

In FIG. 7, the controller 410 determines whether the input channel key is an analog TV channel or a digital TV channel. If the selected channel is an analog TV channel, the control unit 410 transmits mode selection data for the analog video mode to the analog TV signal processing unit 100 and the memory 420 through the data line to transmit the analog TV signal processing unit 100 and the memory ( 420 is operated.

In addition, if the selected channel is a digital TV channel, the control unit 410 transmits the mode selection data for the digital video mode to the digital TV signal processing unit 200 and the memory 420 through the data line, and the digital TV signal processing unit 200 and Operate the memory 420.

This memory 420 is used as a frame memory for Y / C separation and post-processing when the analog video mode is selected, and the current frame data processed by the analog TV signal processing unit 100 is transmitted through the data line (s). The previous frame data stored in the memory 420 and stored in the memory 420 are transmitted to the analog TV signal processor 100 through the data line (s). In addition, when the digital video mode is selected, the data processed by the digital TV signal processor 200 is used as a VBV buffer for converting a fixed bit rate into a variable bit rate and a frame buffer for motion compensation when the digital video mode is selected. Previous data written to the memory 420 via the line (s) and stored in the memory 420 is transmitted to the digital TV signal processor 200 via the data line (s).

The signals processed by the analog TV signal processing unit 100 and the digital TV signal processing unit 200 according to the mode selection signal output from the control unit 410 are switched by the multiplexer 430 and then displayed on the display through the display connection unit 440 ( 450).

8 is a block diagram of a receiver having analog and digital video modes according to a third embodiment of the present invention.

In FIG. 5, a function of a memory controller configured in hardware, that is, a function of selecting the analog TV signal processor 100 or the digital TV signal processor 200 according to the mode selection signal is programmed, and the memory 519 is programmed. It is used alternately for digital video decoding and analog TV signal processing such as Y / C separation and post processing.

Further, the memory 519 can be shared by performing the Y / C and post-processing in the analog video mode in the microprocessor 518 that performs the digital video decoding function.

In FIG. 8, the first tuner 511 selects only a signal of a channel desired by a user from an analog TV channel signal transmitted through an analog TV channel receiving antenna and outputs the IF signal.

The first channel demodulator 512 amplifies the IF signal of the channel selected by the first tuner 511 and outputs a video signal.

The A / D converter 513 converts the video signal output from the first channel demodulator 512 into a digital signal form.

On the other hand, the second tuner 514 selects a signal of a desired channel from the MPEG-2 encoded digital TV signal transmitted through the digital TV channel receiving antenna.

The second channel demodulator 515 outputs a signal of a desired digital TV channel output through the second tuner 514 as an MPEG-2 bitstream.

The system decoder 516 extracts only the video data stream again from the MPGE-2 bitstream.

The controller 517 determines whether the input channel key is an analog TV channel or a digital TV channel, and outputs a mode selection signal indicating an analog video mode or a digital video mode.

The microprocessor 518 receives the mode selection signal to select the output of the A / D converter 513 connected to the first input port or the output of the system decoder 516 connected to the second input port. That is, in the analog video mode, the microprocessor 518 selects a digitized analog TV channel signal output from the A / D converter 513 and selects predetermined program commands (for example, read from address XXXX, write to). Adrress XXX) is used to write to or read from the memory 519 to perform Y / C separation and post-processing. At this time, the memory 519 is used as a frame memory for Y / C separation and post processing.

In addition, the microprocessor 518 uses the program data (for example, read from address YYYY and write to adrress YYY) to output the video data stream output from the system decoder 516 in the digital video mode. The data is decoded by writing to or reading from the memory 519. This video decoding includes variable length decoding, inverse quantization, inverse DCT conversion, and the like. At this time, the memory 519 is used as a VBV buffer for converting a fixed bit rate, a frame buffer for motion compensation, and a display buffer.

As shown in FIG. 8, in order to use only one input port of the microprocessor 518 in addition to receiving signals using the first and second input ports of the microprocessor 518, a multiplexer may be connected in front of the input port. It can also be implemented to perform switching between two inputs. Such modifications may be similarly applied to the embodiments of FIGS. 9A to 9C, 10, and 12A to 12C.

On the other hand, the display connection unit 520 converts the digital data output from the microprocessor 518 into an analog signal form and displays it on the display 521 as analog R, G and B signals.

Here, even if a kind of microprocessor 518 which is very fast in operation is used, only a specific function may be implemented in hardware, such as inverse DCT conversion requiring high speed.

9A, 9B, and 9C are modifications of the third exemplary embodiment shown in FIG. 8, and the same components as in FIG. 8 are denoted by the same reference numerals, and detailed operation description thereof will be omitted.

The microprocessor 522 illustrated in FIG. 9A receives a digitized analog TV channel signal output from the A / D converter 513 in the analog video mode and uses the memory 519 as described in FIG. / C Perform separation and post-processing.

In addition, the microprocessor 522 receives the MPEG-2 bit stream from the second channel demodulator 515 in the digital video mode, selects and extracts the video data stream from the MEEG-2 bit stream under the control of the controller 517, and then decodes the video decoder. Output to (523). The video decoder 523 restores video data from the extracted video data stream.

In this case, the microprocessor 522 provides a memory access path so that the memory 519 can be used as a VBV buffer, a frame buffer, and a display buffer required by the video decoder 523.

The multiplexer 524 selects a signal processed digitized analog signal output from the microprocessor 522 or video data reconstructed by the video decoder 523 according to the mode selection signal from the controller 517 to display the selected signal. It supplies to the connection part 520.

The microprocessor 525 illustrated in FIG. 9B performs Y / C separation and post-processing as described in FIG. 9A in analog video mode, and performs MPEG-2 system decoding and video decoding in digital video mode. That is, in the digital video mode, the second channel demodulator 515 receives the MPEG-2 bit stream, extracts the video data stream, and then supplies the microprocessor 525 to recover the video data from the extracted video data stream. Performed by

The microprocessor 527 shown in FIG. 9C has a memory control function for sharing the memory 519 in each case in the analog mode and the digital video mode, and in the analog mode, as described with reference to FIGS. 9A and 9B. / C Perform separation and post-processing.

Meanwhile, in the digital video mode, the MPEG-2 system decoding and the video decoding are performed by the system video decoder 526. The multiplexer 528 then selects the signal-processed digitized analog signal output from the microprocessor 527 or the reconstructed video data output from the system video decoder 526 according to the mode selection signal from the controller 517. The selected signal is supplied to the display connection unit 520.

FIG. 10 is a block diagram of a receiver having an analog and digital video mode according to a fourth embodiment of the present invention. The first tuner 611, the first channel demodulator 612, and the second tuner having the same configuration as those of FIG. 614, detailed operations of the second channel demodulator 615, the system decoder 616, the display connection unit 620, and the display 621 will be omitted.

In the third embodiment shown in FIG. 8, the memory control function is programmed into the microprocessor 618, while in the fourth embodiment, analog processing such as 3-D (dimensional) Y / C separation or post-processing is performed. The analog processor 613 is external to the microprocessor 618. The detailed configuration of the analog processor 613 includes an A / D converter 701, an analog TV signal processor 702, and a D / A converter 703 as shown in FIG.

The A / D converter 701 converts the channel demodulated signal output from the first channel demodulator 612 of FIG. 10 into digital data. This digital data is input to the analog TV signal processor 702 and stored in the memory 619 via a microprocessor 618 that acts as a memory controller. The analog TV signal stored in the memory 619 is used by the analog TV signal processor 702 for Y / C separation or post processing. The output processed by the analog TV signal processor 702 is temporarily stored in the memory 619 before being read out and converted into an analog signal by the D / A converter 703.

On the other hand, in the case of a digital video service, the MPEG-2 bitstream is decoded into a video data stream at the system decoder 616, and the video data stream is restored to the video data by the microprocessor 618. The recovered data is converted into an analog signal by the D / A converter 623.

In response to the mode selection signal output from the controller 617 which recognizes the mode according to the channel key input, the multiplexer 622 outputs the analog TV signal processed by the analog processor 613 or the analog video output from the D / A converter 623. Select the signal.

In this case, the display connection unit 620 of FIG. 10 receives the data converted into an analog signal, converts the data into R, G, and B signals, and outputs the same to the display 621. As a variant of this, the display connection unit 620 may be internally implemented in an integrated form of the digital-to-analog converter 703 and the digital-to-analog converter 623, which are one of the components of the analog processor 613, wherein The multiplexer 622 receives a digital signal, converts the analog signal into an analog signal, and outputs the analog R, G, and B signals to the display 621. This variant also applies to FIGS. 12A, 12B and 12C as well.

On the other hand, the embodiment of FIG. 10 may be somewhat modified depending on the extent to which MPEG decoding is implemented by software using microprocessor 618.

12A to 12C are modifications of the fourth embodiment shown in FIG. 10, and the same components as in FIG. 10 are denoted by the same reference numerals and detailed descriptions of the operations will be omitted.

The microprocessor 618 shown in FIG. 12A performs only control of the memory 619. MPEG-2 bitstream decoding and video data stream decoding are performed by a system video decoder 802 external to the microprocessor 801.

The microprocessor 803 shown in FIG. 12B performs both MPEG-2 bit stream decoding and video data stream decoding.

The microprocessor 804 shown in FIG. 12C performs MPEG-2 bitstream decoding while the video data stream decoding is performed by the video decoder 805 external to the microprocessor 804.

The present invention provides a digital video decoding memory by using a large memory having a frame memory for digital video decoding, which is required for analog video signal processing when receiving an analog TV channel in a receiver for receiving both an analog video service and a digital video service. It can increase the efficiency of the system and lower the cost of the system.

Claims (37)

A receiver having an analog video mode for receiving an analog TV signal according to a predetermined analog broadcasting method and a digital video mode for receiving a TV signal digitally processed according to a predetermined digital signal format: First signal processing means for signal processing a received analog TV signal; Second signal processing means for decoding the received digital TV signal; A memory for storing data for decoding the digital TV signal in the second signal processing means and for processing the analog TV signal digitized in the first signal processing means; Generating means for generating a mode selection signal indicating an analog video mode or a digital video mode; The memory is adapted to be used for writing and reading out a signal processed by the first signal processing means into the memory in analog video mode according to the mode selection signal and for writing / reading a digital TV signal in digital video mode. Memory control means for controlling; Switching means for switching one of an output signal of the first signal processing means and an output signal of the second signal processing means in accordance with the mode selection signal; And And display control means for controlling a signal switched by said switching means to be displayed on a display. A receiver having an analog video mode for receiving an analog TV signal according to a predetermined analog broadcasting method and a digital video mode for receiving a TV signal digitally processed according to a predetermined digital signal format: Control means connected to a common bus line of data line (s) and clock lines, the control means for generating mode selection data indicating whether it is an analog video mode or a digital video mode; First signal processing means connected to the common bus line and signal processing an analog TV signal received according to the mode selection data; Second signal processing means connected to the common bus line and decoding digital TV signals received according to the mode selection data; And Connected to the common bus line and provided for decoding of the digital TV signal of the second signal processing means, writing data processed by the first signal processing means according to the mode selection data indicating an analog video mode, A memory for supplying the stored data to the first signal processing means; Switching means for switching one of an output signal of the first signal processing means and an output signal of the second signal processing means in accordance with the mode selection data; And And display control means for controlling a signal switched by said switching means to be displayed on a display. A receiver having an analog video mode for receiving an analog TV signal according to a predetermined analog broadcasting method and a digital video mode for receiving a TV signal digitally processed according to a predetermined digital signal format: A first input terminal for inputting a digitized analog TV signal; A second input terminal for inputting a channel decoded digital TV signal; Generating means for generating a mode selection signal by determining whether the channel selected by the user is a TV channel in an analog video mode or a TV channel in a digital video mode; A memory used for video decoding of the channel decoded digital TV signal; A system decoder for extracting a video data stream from the channel decoded digital TV signal input to the second input terminal; One of the signals input to the first input terminal and the second input terminal is selected and processed according to the mode selection signal. In the analog video mode, the digitized analog signal input to the first input terminal is written into the memory and read out. Microprocessor to control the memory to share the memory; And And display control means for controlling a signal processed by the microprocessor to be displayed on a display. 4. The video processor of claim 3, wherein the microprocessor performs Y / C separation of the digitized analog TV signal input to the first input terminal in the analog video mode, and outputs the video from the system decoder in the digital video mode. And recovers a digital video signal from the data stream. A receiver having an analog video mode for receiving an analog TV signal according to a predetermined analog broadcasting method and a digital video mode for receiving a TV signal digitally processed according to a predetermined digital signal format: A first input terminal for inputting a digitized analog TV signal; A second input terminal for inputting a channel decoded digital TV signal; Generating means for generating a mode selection signal by determining whether the channel selected by the user is a TV channel in an analog video mode or a TV channel in a digital video mode; A memory used for video decoding of the channel decoded digital TV signal; Signal processing is performed by selecting one of the signals input to the first input terminal and the second input terminal according to the mode selection signal. In the analog video mode, Y / C separation of the digitized analog TV signal input to the first input terminal is performed. Write and read into the memory to read and control the memory to be shared, and in the digital video mode, perform system decoding to extract a video data stream from a channel decoded digital TV signal input to the second input terminal. A processor; A video decoder for recovering a digital video signal from a video data stream output from the microprocessor to provide a restored digital TV signal; Switching means for switching a signal-processed analog TV signal provided from the microprocessor and a restored digital TV signal provided from the video decoder according to the mode selection signal; And And display control means for controlling a signal switched by said switching means to be displayed on a display. A receiver having an analog video mode for receiving an analog TV signal according to a predetermined analog broadcasting method and a digital video mode for receiving a TV signal digitally processed according to a predetermined digital signal format: A first input terminal for inputting a digitized analog TV signal; A second input terminal for inputting a channel decoded digital TV signal; Generating means for generating a mode selection signal by determining whether the channel selected by the user is a TV channel in an analog video mode or a TV channel in a digital video mode; A memory used for video decoding of the channel decoded digital TV signal; Signal processing is performed by selecting one of the signals input to the first input terminal and the second input terminal according to the mode selection signal. In the analog video mode, Y / C separation of the digitized analog TV signal input to the first input terminal is performed. Write to and read from the memory to share the memory, and in the digital video mode, perform system decoding to extract a video data stream from the channel decoded digital TV signal input to the second input terminal, A microprocessor for restoring a digital video signal from the extracted video data stream; And And display control means for controlling a signal processed by the microprocessor to be displayed on a display. A receiver having an analog video mode for receiving an analog TV signal according to a predetermined analog broadcasting method and a digital video mode for receiving a TV signal digitally processed according to a predetermined digital signal format: A first input terminal for inputting a digitized analog TV signal; A second input terminal for inputting a channel decoded digital TV signal; Generating means for generating a mode selection signal by determining whether the channel selected by the user is a TV channel in an analog video mode or a TV channel in a digital video mode; A memory used for video decoding of the channel decoded digital TV signal; A system video decoder which extracts a video data stream from the channel decoded digital TV signal input to the second input terminal and restores the video data stream to the digital video signal from the extracted video data stream; Select one of the signals provided from the first input terminal and the system video decoder according to the mode selection signal, and process the signal. In the analog video mode, the digitized analog TV signal input to the first input terminal is input to the memory. A microprocessor which controls to share the memory by writing and reading; Switching means for switching a signal-processed analog TV signal provided from the microprocessor and a restored digital TV signal provided from the system video decoder according to the mode selection signal; And And display control means for controlling a signal switched by said switching means to be displayed on a display. 8. The receiver of claim 7, wherein the microprocessor further performs post-processing using the separated Y signal. 8. The receiver of claim 7, wherein in the analog video mode, the memory is used as a frame memory for Y / C separation of the digitized analog TV signal. 9. The receiver of claim 8, wherein in the analog video mode, the memory is used as a frame memory for Y / C separation and post processing. 8. The receiver of claim 7, wherein in the digital video mode, the memory is used as a channel buffer for converting a fixed bit rate into a variable bit rate, as a frame buffer for motion compensation and as a display buffer. A receiver having an analog video mode for receiving an analog TV signal according to a predetermined analog broadcasting method and a digital video mode for receiving a TV signal digitally processed according to a predetermined digital signal format: A first input terminal for inputting a channel demodulated analog TV signal; A second input terminal for inputting a channel decoded digital TV signal; A generator for generating a mode selection signal indicative of an analog video mode or a digital video mode; A memory for storing data for source decoding of the channel decoded digital TV signal and for processing the channel demodulated analog TV signal; Digital processing means having an input for receiving the channel decoded digital TV signal and extracting a video data stream from the channel decoded digital TV signal; A microprocessor which receives the video data stream extracted from the digital processing means and restores the digital video signal, and writes and reads the digitized analog TV signal into the memory in the analog video mode; An input terminal for receiving the channel demodulated analog TV signal, an input terminal for inputting data read from the memory from the microprocessor, an output terminal for outputting the data to the microprocessor for storing data in the memory, and outputting the processed analog TV signal Analog processing means having an output stage; Switching means for selecting one of an output signal of the digital processing means and the processed analog TV signal; And And display control means for controlling the signal switched by the switching means to be displayed on the display. 13. The method of claim 12, further comprising converting means for converting the digital video signal restored by the microprocessor into an analog signal and supplying it to the switching means, wherein the signal output from the analog processing means is an analog signal. Receiver. 13. The receiver as claimed in claim 12, wherein the display control means converts the signal switched by the switching means into an analog signal, wherein the switched signal is a digital signal. 13. The receiver of claim 12, wherein in the digital video mode, the memory is used as a channel buffer for converting a fixed bit rate into a variable bit rate, a frame buffer for motion compensation, and a display buffer. 13. The receiver of claim 12, wherein the analog processing means performs luminance / color separation of the channel demodulated analog TV signal. 17. The receiver of claim 16, wherein in the analog video mode, the memory is used as a frame memory for luminance / color separation of the channel demodulated analog TV signal. 13. A receiver as claimed in claim 12, wherein said analog processing means performs post-processing of said channel demodulated analog TV signal. 19. The receiver of claim 18, wherein in the analog video mode, the memory is used as a frame memory for post-processing the channel demodulated analog TV signal. In a method for receiving a TV signal that has been analog processed according to a predetermined analog broadcasting method and a TV signal that has been digitally processed by a predetermined digital signal format: (a) generating a mode selection signal by determining whether the channel selected by the user is a TV channel in an analog video mode or a TV channel in a digital video mode; And (b) storing the digital TV signal received according to the mode selection signal in a digital video decoding memory and decoding the data using the data stored in the memory. In a method for receiving a TV signal that has been analog processed according to a predetermined analog broadcasting method and a TV signal that has been digitally processed by a predetermined digital signal format: (a) generating a mode selection signal by determining whether the channel selected by the user is a TV channel in an analog video mode or a TV channel in a digital video mode; And (b) storing the analog TV signal received according to the mode selection signal in the digital video decoding memory, and reading and processing the data stored in the memory. 4. The receiver of claim 3, wherein the microprocessor further performs post-processing using the separated Y signal. 4. The receiver of claim 3, wherein in the analog video mode, the memory is used as a frame memory for Y / C separation of the digitized analog TV signal. 23. The receiver of claim 22, wherein in the analog video mode, the memory is used as a frame memory for Y / C separation and post processing. 4. The receiver of claim 3, wherein in the digital video mode, the memory is used as a channel buffer for converting a fixed bit rate into a variable bit rate, as a frame buffer for motion compensation and as a display buffer. 6. The receiver of claim 5, wherein the microprocessor further performs post-processing using the separated Y signal. 6. The receiver of claim 5, wherein in the analog video mode, the memory is used as a frame memory for Y / C separation of the digitized analog TV signal. 27. The receiver of claim 26 wherein in the analog video mode the memory is used as a frame memory for Y / C separation and post processing. 6. The receiver of claim 5, wherein in the digital video mode, the memory is used as a channel buffer for converting a fixed bit rate into a variable bit rate, as a frame buffer for motion compensation and as a display buffer. 7. The receiver of claim 6, wherein the microprocessor further performs post-processing using the separated Y signal. 7. The receiver of claim 6, wherein in the analog video mode, the memory is used as a frame memory for Y / C separation of the digitized analog TV signal. 31. The receiver of claim 30, wherein in the analog video mode, the memory is used as a frame memory for Y / C separation and post processing. 7. The receiver of claim 6, wherein in the digital video mode, the memory is used as a channel buffer for converting a fixed bit rate into a variable bit rate, as a frame buffer for motion compensation and as a display buffer. 8. The receiver of claim 7, wherein the microprocessor further performs post-processing using the separated Y signal. 8. The receiver of claim 7, wherein in the analog video mode, the memory is used as a frame memory for Y / C separation of the digitized analog TV signal. 35. The receiver of claim 34, wherein in the analog video mode, the memory is used as a frame memory for Y / C separation and post processing. 8. The receiver of claim 7, wherein in the digital video mode, the memory is used as a channel buffer for converting a fixed bit rate into a variable bit rate, as a frame buffer for motion compensation and as a display buffer.