KR100212304B1 - Apparatus and method for adaptive frequency control of radio receiver - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

In the field of wireless communications

2. Technical problem that the invention tries to solve

In order to adjust the frequency by using the frequency tracking technique to overcome the residual frequency, which is an important factor that determines the performance of the system together with the additive noise, conventionally, the number of zero crossings is calculated according to the number of times to detect the frequency error. Although the method of estimating the residual frequency and the orthogonal channel correlation circuit extracts the phase change component, obtains the frequency deviation, and uses the synchronous loop method to determine the dynamic characteristics through the loop filter, the complex multiplier or adder In addition to the need for circuitry, the solution to the problem of always being exposed to phase noise environments.

3. Summary of the solution of the invention

By using the technique of hardly determining the polarity of the residual frequency at each integer multiple of the reference level (zero point) crossing, defining the spreading or convergence state of the positive and negative polarity and the residual frequency, and generating the control signal of the frequency synthesizer to track the frequency deviation. It provides an adaptive frequency control method and device that can reduce the effects of noise while reducing the size of computation, real-time processing capacity, and system complexity compared to the system.

4. Important uses of the invention

Used for frequency tracking in wireless receiver systems.

Description

Adaptive Frequency Control Method and Device of Wireless Receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a wireless receiver system. In particular, a process of tracking frequency by extracting frequency deviation from a digital synchronization circuit for carrier tracking together with phase correction of a pilot signal applied to automatic frequency control is performed. The present invention relates to an adaptive frequency adjusting method and apparatus for adaptively operating according to a state characteristic.

In general, automatic frequency adjustment is used to track the variation factor of the instantaneous center frequency of the received signal due to the frequency deviation (drift) on the transmitter carrier due to the frequency tolerance of the transmitter (base station) or the strong Doppler phenomenon on the wireless channel. The oscillation frequency of the local oscillator of the receiver (mobile station) is adjusted. Frequency tolerance is the maximum allowable deviation from the reference frequency occupied by the launch. In general, there are various types of carrier synchronization methods using digital technology in the digital communication method. 1 shows a schematic configuration diagram of a wireless receiver having a carrier synchronization circuit. As shown in FIG. 1, the radio receiver 10 is largely composed of a radio frequency (RF) tuning stage 11 for frequency band selection and synchronization and a baseband signal processing stage 12 for digital signal demodulation. . In order to perform synchronous demodulation in the radio receiver 10, it is necessary to keep or lock the input carrier phase of the transmitted signal and the phase of the local oscillator in a certain temporal relationship within an acceptable range. For this purpose, as shown in FIG. 1, a control signal for controlling the voltage controlled oscillator VCO (not shown) in the radio frequency (RF) tuning stage 11 is required. This VCO control signal has the above-described automatic frequency adjustment function.

2 shows a detailed configuration diagram of a radio receiver for synchronous demodulation. Referring to FIG. 2, the demodulation process of the received signal is briefly described. First, the received signal is down-converted through the RF / IF stages 21, 22, and 23, and then the I-channel is passed through the mixers 24A and 24B. And Q-channel signals, filtered through low pass filters 25A and 25B, and then converted into digital signals by analog-to-digital converters (ADCs) 26A and 26B. Next, demodulation is performed using this digital signal. The operation is formulated as follows. When accommodating N channels, the received signal r (t) may be expressed as Equation 1 below.

: 주파수 편차here

Frequency deviation

: 반송파 주파수

: Carrier frequency

: 기저대역 변조신호

= Baseband modulated signal

: 비동기 위상요소

: Asynchronous phase element

When the demodulated signal down-converted by the received signal through the RF tuning circuit is u (t) in Equation 1, the demodulated signal can be expressed as Equation 2 below.

Reference Signal Demodulation Information Channel Signal Demodulation

)에 대한 보정 기능이다. 도2에서 위상보정은 임의의 샘플 주기(칩주기 정수배의 임의값) 동안 수신 값들을 평균화하여 기준 신호(예:파일럿 신호)의 비동기 위상 성분을 추출하는 위상검출부(29)와 그 값의 공액 복소값을 정보 채널 신호에 곱셈하는 처리를 수행하는 위상보정부(27)를 통하여 동기를 위한 위상 보정을 이룬 다음, 복조기(28)에서 복조가 이루어진다. 여기서 정보 채널이라 함은 통신 서비스를 제공하기 위하여 정보가 전송되는 채널을 말한다. 그러나 이와 같은 위상보정기능은 일정한 시간특성을 갖고 변화하는 주파수 편차의 변화속도가 일정값 이상을 벗어나면 비동기 성분을 극복하지 못하게 되어 자동 주파수 조절 기능을 필요로 한다. 이와 같은 주파수 조절 기능을 보면, 위상검출부(29)에서 입력신호와 국부발진기의 위상이 일정한 시간적 관계로 유지할 수 있도록 먼저 디지털 이산 입력신호를 처리하여 기저대역 상에 실려오는 주파수 편차성분(

)을 추출하고, 주파수 조절부(31)에서 그 편차성분의 반대 부호를 갖는 편차 만큼의 주파수를 합성하기 위한 주파수 편차 제어신호를 발생하여, 주파수 합성기(32) 내부의 전압 제어 발진기(도시 안됨)의 발진 주파수를 제어하는 과정을 통하여 이루어진다. 그런데 임의의 환경에서 수신 입력단으로부터 복조기로 유입되는 신호에 주파수 편이가 생기면 도3에 도시된 바와 같은 주파수 편차로 인한 기저 대역 복조 파형이 발생될 수 있다. 도3에 도시된 파형으로부터 알 수 있는 바와 같이, 주파수 편차 검출부(30)의 입력 파형(샘플상관주기 : 1/36 msec)으로서 일정값으로 유지되어야 하는 I-채널과 Q-채널의 상관출력이 위상 비동기 성분과 주파수 편이로 인하여 상관 진폭과 위상이 시간적으로 변화하는 특성을 보여준다. 여기서 수신파형은 자동 이득 제어기(AGC)가 동작하지 않는 상태에서 처리되어 페이딩 특성이 복조파형에 그대로 실려 있으나 실제 시스템은 AGC를 포함하고 있으므로 대체로 일정한 상관값의 크기를 유지한다. 그런데, 도3에 도시된 바와 같은 주파수 편차를 갖는 파형에서, 가산성 잡음과 함께 시스템의 성능을 결정하는 중요한 요소인 잔류 주파수를 극복하기 위해서는 주파수 추적 기법을 이용하여 주파수를 조절해야 하는데, 종래에는 주파수 오차를 검출하기 위해 영점 교차 횟수를 계산하여 그 횟수에 따라 잔류 주파수를 추정하는 방식과 직교 채널 상관회로(Balanced Quadricorrelator)를 이용하여 위상의 변화 성분을 추출하고 주파수 편차를 얻어 루프 필터를 통하여 그 동적 특성을 결정하는 동기 루프 방식을 이용해 왔다. 그러나 이러한 방식에 있어서는 복잡한 곱셈기나 가산기 등의 회로가 필요로할 뿐 아니라, 위상 잡음 환경에 항상 노출되어 있다는 문제점이 있었다.The information for synchronous demodulation is obtained from a reference signal demodulation term among demodulated signals for each channel after downconverting through the RF / IF stages 21, 22, and 23 in association with the term in [Equation 2]. Here, the reference signal is an unmodulated signal transmitted for synchronization used in a CDMA system and may provide synchronization phase information on the I-channel and the Q-channel through PN (Pseudo Noise) code despreading during demodulation. The factor for carrier synchronization can be largely divided into two. Among the reference signal demodulation terms described in [Equation 2], the correction for the phase (θ) represented by the asynchronous component, which is a later term, and the rest are frequency deviations that change with time (

) Is a correction function. In Fig. 2, phase correction is a complex conjugate of a phase detector 29 and a value of a phase detector 29 which extracts an asynchronous phase component of a reference signal (e.g., a pilot signal) by averaging received values for an arbitrary sample period (an arbitrary value of chip period integer times). Phase correction for synchronization is performed through a phase compensator 27 which performs a process of multiplying the value by the information channel signal, and then demodulation is performed in the demodulator 28. The information channel refers to a channel through which information is transmitted to provide a communication service. However, such a phase correction function has a constant time characteristic and does not overcome the asynchronous component when the change rate of the changing frequency deviation exceeds a certain value and thus requires an automatic frequency adjustment function. In this frequency adjustment function, first, the phase detection unit 29 processes the digital discrete input signal so that the phase of the local signal and the local oscillator maintain a constant temporal relationship.

), And the frequency adjusting unit 31 generates a frequency deviation control signal for synthesizing the frequency by the deviation having the opposite sign of the deviation component, the voltage controlled oscillator (not shown) inside the frequency synthesizer 32 Through the process of controlling the oscillation frequency of the. However, if a frequency shift occurs in a signal flowing into the demodulator from the receiving input terminal in any environment, a baseband demodulation waveform may be generated due to the frequency deviation as shown in FIG. As can be seen from the waveform shown in Fig. 3, as the input waveform (sample correlation period: 1/36 msec) of the frequency deviation detection unit 30, the correlation output of the I-channel and the Q-channel, which should be kept at a constant value, The correlation amplitude and phase change in time due to the phase asynchronous component and frequency shift. Here, the received waveform is processed in the state that the automatic gain controller (AGC) does not operate so that the fading characteristics are displayed in the demodulation waveform as it is, but since the actual system includes the AGC, it maintains a substantially constant magnitude of correlation value. However, in a waveform having a frequency deviation as shown in FIG. 3, in order to overcome the residual frequency, which is an important factor that determines the performance of the system together with additive noise, the frequency must be adjusted using a frequency tracking technique. In order to detect the frequency error, the number of zero crossings is calculated and the residual frequency is estimated according to the number of times, and the phase change component is extracted by using a quadrature channel correlation circuit (Balanced Quadricorrelator), and the frequency deviation is obtained. The synchronous loop method of determining the dynamic characteristics has been used. However, this method requires not only a circuit such as a complex multiplier or an adder, but also has a problem that it is always exposed to a phase noise environment.

Accordingly, the present invention devised to solve the above-mentioned problem is a constant change environment while reducing the size of computation, real-time processing capacity, and system complexity compared to various frequency detection circuits currently used for automatic frequency adjustment in a digital synchronization system. It is an object of the present invention to provide a method and apparatus for adaptive frequency regulation of a structure that can reduce the effects of noise in the present invention.

1 is a schematic configuration diagram of a conventional carrier synchronous radio receiver.

2 is a detailed block diagram of a conventional carrier synchronous radio receiver.

3 is an illustration of a baseband demodulation waveform due to frequency deviation.

4 is a signal processing flowchart of an adaptive frequency adjusting method according to an embodiment of the present invention.

5 is a schematic structural diagram of a frequency deviation detector according to an embodiment of the present invention.

6 is an exemplary input waveform diagram of a frequency deviation detector.

7 is a processing waveform diagram of a frequency deviation detection signal.

8 is a flowchart illustrating a process of generating a frequency deviation signal in accordance with the present invention.

9 is a detailed configuration diagram of a frequency adjusting unit according to an embodiment of the present invention.

Fig. 10 is a state diagram according to the number of bits of the state signal.

Fig. 11 is a diagram showing an example of the adjustment gain according to the state value of each state function when the state bit number is two.

12 is a simulation output diagram using the frequency control device according to the present invention.

* Explanation of symbols for main parts of the drawings

51,57: Hard decision unit 52,53,54: delay element

55,56,58: Modulo-2 adder 90: Frequency deviation detector

91: frequency regulator 92: delay element

93: state function processor 94: gain regulator

95: Comparators and Selectors 96: Absoluteizers

97: delay element 98: integrator

According to an embodiment of the present invention, a frequency adjusting device includes: means for detecting frequency deviation from I-channel and Q-channel input signals; And means for controlling the frequency deviation in accordance with the output of the frequency detecting means, the frequency deviation detecting means comprising: first hard decision means for hard determining an I-channel input signal and converting it into a binary signal; Second hard decision means for hard determining a Q-channel input signal and converting it into a binary signal; And means for generating a frequency error increase and decrease signal from the output signals of the first and second hard decision means, wherein the frequency deviation control means stores the output signal of the frequency deviation detection means by delaying the signal for a predetermined period. Means for doing so; Means for delaying and feeding back the output of said frequency deviation control means for a predetermined period; Means for absoluteizing the output values of the delay and feedback means; Comparing and selecting means for selecting and outputting a larger one of the two signals by comparing the output of the absolute means with a predetermined reference value; Gain adjusting means having a plurality of output stages configured to multiply outputs of the delay and feedback means and outputs of the comparing and selecting means, respectively, and output the results to different output stages; Switching means for selectively outputting the output of one of the plurality of output stages of the gain adjusting means in accordance with the output of the frequency deviation detecting means and the output of the delay and storage means; And means for generating a control signal for controlling said frequency synthesizer from said switching means output.

In a radio receiver system according to another embodiment of the present invention, a radio frequency signal tuning stage for downconverting a received radio frequency signal, separating the signal into an I-channel and a Q-channel signal, and then converting the signal into a digital signal ; Phase detection means connected to said radio frequency tuning stage for detecting phases of said I-channel and Q-channel signals; Phase correction means for correcting a phase of an output signal of the radio frequency tuning step according to the output of the phase detection means; Demodulation means for demodulating the output signal of the phase correction means; Means for detecting a frequency deviation from the I-channel and Q-channel input signals; And means for controlling the frequency deviation in accordance with the output of the frequency detecting means, the frequency deviation detecting means comprising: first hard decision means for hard determining the I-channel input signal and converting it into a binary signal; Second hard decision means for hard decision of the Q-channel input signal to convert to a binary signal; And means for generating a frequency error increase and decrease signal from the output signals of the first and second hard decision means, wherein the frequency deviation control means stores the output signal of the frequency deviation detection means by delaying the signal for a predetermined period. Means for doing so; Means for delaying and feeding back the output of said frequency deviation control means for a predetermined period; Means for absoluteizing the output values of the delay and feedback means; Comparing and selecting means for selecting and outputting a larger one of the two signals by comparing the output of the absolute means with a predetermined reference value; Gain adjusting means having a plurality of output stages configured to multiply outputs of the delay and feedback means and outputs of the comparing and selecting means, respectively, and output the results to different output stages; Switching means for selectively outputting the output of one of the plurality of output stages of the gain adjusting means in accordance with the output of the frequency deviation detecting means and the output of the delay and storage means; And means for generating a control signal for controlling the oscillation frequency of the frequency synthesizer from the switching means output.

A frequency adjusting method according to another embodiment of the present invention includes: a first hard decision step of hardly determining an I-channel input signal and converting it into a binary signal; A second hard decision step of hardly determining the Q-channel input signal and converting it into a binary signal; Identifying threshold crossings of the I-channel signal; When the I-channel signal crosses a threshold, generating a signal indicating increase or decrease of a frequency error according to the hard decision result; Determining a frequency adjusting gain of the frequency synthesizer according to the frequency error increase and decrease signal; Generating a control signal for controlling the frequency deviation in accordance with the determined frequency adjusting gain; And generating a control signal for adjusting the oscillation frequency of the frequency synthesizer from the frequency deviation control signal.

The invention is now described in more detail with reference to the accompanying drawings, in which preferred embodiments thereof are shown. In the present invention, a new algorithm is used to automatically adjust the frequency by tracking the frequency deviation component in the waveform shown in FIG. 4 shows a signal processing procedure according to the frequency adjusting method of the present invention. First, when the receiver enters the frequency tracking mode (step 41), first a hard decision of the I-channel and Q-channel signals is performed (step 42), and then a threshold of the I-channel signal (e.g., For example, a zero crossing is checked (step 43). Next, using the hard decision result, a frequency error increase and decrease signal is generated (step 44). Then, a state function is generated according to the frequency error increase / decrease signal, the adjustment gain is determined according to the state function (step 45), and then the voltage controlled oscillator (VCO) inside the frequency synthesizer (32 in FIG. 2) is controlled. Generate a control signal (step 46). This process will be described in more detail with reference to FIGS. 5 to 10 as follows. 5, there is shown a schematic block diagram of a frequency deviation detector according to an embodiment of the present invention. First, the hard decision unit 51 performs hard decision of the I-channel digital input signal (2's complememt type) among the input signals and checks the zero point (reference level) intersection. 6 is an exemplary diagram of I-channel and Q-channel signal waveforms input to a frequency deviation detector in an environment in which an automatic gain controller (AGC) operates. As shown in Fig. 6, the I-channel signal appears as a signal that is 90 ° out of phase with respect to the Q-channel signal, where the input signal on the I-channel interferes at the zero crossing point as an interference component for the CDMA code correlation value. Zero noise can occur repeatedly due to noise or noise. In order to overcome this problem, in the present invention, the frequency deviation is detected using a frequency deviation detector having the configuration as shown in FIG. A frequency deviation detection process will be described with reference to the frequency deviation detector configuration shown in FIG. 5 and the frequency deviation detection signal processing waveform diagram shown in FIG. First, the input signal of the I-channel passes through the time delay filter and hardly decides '0' and '1' at the point where the L sample period has elapsed from the crossing point to overcome the noise characteristic at the zero crossing point. We use a method of checking the zero crossing by keeping the value for L sample periods. Therefore, the actual zero crossing is detected after the L sample period, and then the frequency deviation is extracted by hard decision of the I-channel and Q-channel signals. In FIG. 7, if a hard decision is made for each sampling period in order to see the reference level crossing characteristic of the I-channel signal, '1' and '0' are repeated due to noise around the zero crossing point. In order to reduce the probability of error due to such hysteresis, if a determination is made at a point (a point, b point) separated by L sample periods from the zero crossing point, the detection value has a noise margin as shown in FIG. More specifically, first, the signal delayed by the L sample period of the hard-determined I-channel signal value (in the delay element 52) and the signal delayed by one sample period again in the delayed element (in the delay element 53) in FIG. The module-2 adder 55 performs the operation. Next, the modulo-2 adder 56 performs an addition operation on the output from the hard decision unit 51 and the signal delayed by 2L + 1 cycles at the time of its output. In this case, the condition under which the modulo-2 adder 56 is enabled is when the output of the modulo-2 adder 55 becomes 1. Next, when the output of the modulo-2 adder 56 becomes 1, the output of the hard decision unit 51 and the hard-determined output (output of the hard decision unit 57) of the Q-channel signal are modulo-2 adder 58. By increasing the frequency deviation, the signal increases or decreases to 1 (increase) or 0 (decrease). In other words, the polarity determination of the frequency deviation amount is +1 deviation when the hard decision I-channel signal and Q-channel signal are modulo-2 added at the time after the L-sample cycle after the zero crossing of the I-channel signal, and '1'. If it is determined as 0 and if it is '0', it may be determined as a deviation to generate a frequency deviation detection signal (or a frequency error increase or decrease signal). At this time, the hard decision can be made by simply treating the control amount as discrete digital signals of 1 and 0, which are roughly divided into positive and negative values, thereby reducing hardware complexity.

) 입력회로(95)를 포함하도록 구성하였다. 증가상태에서 가해지는 초기값

에 따라 기울기 과부하 일그러짐(Slope overload distortion)도 커질 수 있으므로 초기값

는 제한요건에 맞춰 조절해야 한다. 여기서 기울기 과부하 일그러짐이란 주파수 편차 변화가 큰 상태에서 확산기의 제어신호 적응속도가 충분히 그 변화특성을 쫓아가지 못하는 것을 말한다. 이러한 과정을 도9를 참조하여 살펴보면, 먼저 상태 처리기(93)의 초기 출력값이 피드백되어 지연소자(97)를 통해 1샘플 주기 만큼 지연된 후, 절대화기(96)를 거치면서 부호가 제거되고, 다음에 비교기(95A)에서 이 피드백된 값과 초기값

를 비교하여 선택 신호(SEL)를 발생한다. 다음에, 선택기(95B)는 선택 신호에 따라 A, B 단자중 하나의 신호를 출력하게 된다. 즉 주파수 편차가 초기값

보다 큰 경우에는 그 편차에 해당하는 신호가 출력되어 이득 조절기(94)내의 곱셈기(94A,94B)를 통해, 예를 들어, 각각 2배, -2배 곱셈된다. 이때 상태 스위치는 그 다음 주기의 상태함수에 따라 스위칭 기능을 수행하여 곱셈기(94A,94B)중 하나의 출력을 출력단자로 연결하여 출력하게 된다. 이와 같은 동작은 매 주기마다 자동적으로 반복되게 된다. 다시 말하면, 초기 스텝사이즈는 상태 함수 발생기(92)의 모든 상태값이 일치할 때 주파수 편차신호를 반복 횟수에 따라 키워가는 구조를 갖도록 하였다. 이와 달리, 상태함수가 감소상태일때는 이득 조절신호의 가변 스텝사이즈가 수렴되는 구조를 갖는다. 이 과정을 보면, 상태 처리기(93)의 출력값이 피드백되어 지연소자(97)를 통해 1샘플 주기 만큼 지연된 후, 이득 조절기(94)내의 -1/2 혹은 -1/4 곱셈기(94C)를 거치면서 주파수 편차가 수렴되게 된다. 이와 같은 방식으로 발생된 주파수 편차 제어신호는 적분기(98)를 거쳐 적분되어 주파수 합성기(VCO) 제어신호로서 작용하게 된다. VCO 제어 신호의 변화량의 크기는 주파수 조절부의 디지털 분해능과 전압제어 발진기(VCO)에 가하는 제어신호대 출력신호의 이득값 변화에 따라 결정된다. 도12는 본 발명의 알고리즘을 적용하여 1000Hz의 주파수 편차입력이 주어질 경우 주파수 추적과정을 통해 얻어진 추정값의 동적특성의 모의실험을 통한 한 예를 보여준다. 여기서 사용된 상태비트수는 2개를 사용하였으며, 입력 주파수 편차와 추정치 사이의 주파수차에 비례하여 제어신호 발생속도가 달라짐을 볼 수 있다. VCO 제어신호인 추정값과 주어진 입력주파수 편차사이의 주파수 차이가 충분히 작아지면 제어신호의 발생밀도가 아주 줄어들어 상당한 주기 동안 일정한 값을 유지하는 안정화 특성을 갖게 된다는 것을 알 수 있다. 도12의 모의실험에서는 주파수 편차 제어신호로부터 VCO 제어신호를 발생하는 적분기 동작을 산술적인 덧셈으로 처리하였으나 실제시스템에선 R-C 저역통과필터등을 이용한 적분회로를 사용할 수 있으므로 순간적으로 변화하는 성분이 완화되어 나타난다. 이와같은 주파수 차이에 비례하는 제어신호 발생과정은 기존의 동기회로보다 훨씬 안정된 성능을 제공할 수 있다. 그 이유는 기존의 동기회로는 OSC 드리프트등으로 유발된 갑작스런 주파수 편차를 빠르게 추적하는데 있어 주파수 편차량에 관계없이 지속적으로 잡음의 영향을 받는 반면에, 본 발명은 주파수 오차의 상태 특성에 따라 발진 주파수 조절 신호레벨 변화 밀도를 최소화 하는 구조를 갖기 때문이다. 이때 처리주파수의 최대량은 입력되는 위상추정신호의 샘플 속도와 상태레벨수L에 따라 달라지며, 최대 추적주파수(입력 주파수 편차)는 상태레벨수(L)와 입력 샘플링속도(Fs)에 따라 결정되는데 Fs/(2L+1)로 제한된다. 이와같은 전체 과정을 통하여 본 발명은 VCO 제어신호에 유입되는 잡음의 시간적 노출밀도를 최소화 하여 주파수 오차를 일정 영역안에 있게 하여 안정된 복조성능을 얻을 수 있게 한다.Next, referring to Figures 8 and 9, the process of storing the binary signal of the frequency deviation detection signal by the number of state bits to obtain a state function from the temporal characteristics, and using the result to determine the control gain of the oscillator control signal Will be described in more detail. 8 shows a signal processing flowchart of a process of generating a VCO control signal using a frequency deviation detection signal according to the present invention, and FIG. 9 shows a detailed configuration diagram of a frequency regulator according to an embodiment of the present invention. have. First, in the process of generating the frequency deviation control signal, a state function is generated from the frequency deviation detection signal (step 81), the state value of the state function is checked (step 82), and the state values (STATE1, STATE2, STATE3). Then, the control gain is determined (steps 83, 84, 85), and the process of generating the frequency deviation control signal is performed. Here, the process of generating the state function according to the frequency error increase and decrease signal in more detail, the output of the frequency deviation detector 90 is a value obtained by quantizing the frequency deviation to 2 bits to determine the positive (+) state or the negative (-) state The value is represented by '1' or '0'. At this time, the binary signal is stored in the frequency controller 91 by the number of state bits to obtain a state value. The state generation here is a memory content indicating the polarity of the frequency deviation determined at each zero crossing time point of the I-channel signal. Fig. 10 is an exemplary diagram in which a state function is obtained from a frequency deviation increase and decrease signal, and examples of the case where the number of state bits is two and three are shown. The state diagram obtained by storing the hard-determined input signal in a memory (or shift register) may define a state function for generating the increase / decrease control signal according to states such as 2 bits, 3 bits, ..., and the like. As the number of status bits increases, the reliability of frequency tracking improves, but the tracking speed becomes relatively slow, so the number of status bits is appropriately 2 or 3. For example, when the status value consists of 2 bits, the status value 00 is determined as the negative frequency deviation increase state (STATE2), 01 and 10 are determined as the frequency deviation decrease state (STATE3), and 11 is indicated as ( The state value is defined by judging by the frequency deviation increasing state (STATE1). Next, for example, when the status value is composed of 3 bits, the status value 000 is determined as the negative frequency deviation increase state (STATE2), and 001 is the state where the frequency deviation amount is switched to the decrease after the negative increase. Determined by (STATE5), 010 is decreased, 011 is converted to positive increase after decrease (STATE6), 100 is reduced to negative increase after reduction, 101 is reduced (STATE3), 110 Is a state in which the transition to a decrease after a positive increase (STATE4), 111 defines a state value in such a manner as to determine each of the positive frequency deviation increase state. Next, the frequency adjustment gain is determined according to the state value of the state function. Now, this frequency adjustment gain process will be described in more detail with reference to FIGS. 9 and 11. In the state diagram, the increase state (diffusion state) and decrease state (convergence state) and gain and polarity adjustment processes according to various states may be arbitrarily determined and applied. An example of the adjustment process accordingly can be seen in the table shown in FIG. As shown in Fig. 11, when the change amount according to the frequency error is increased in the (+) direction, the gain (for example, K = 2) is determined to increase the variable amount, and when the increase is made in the (-) direction. The gain (e.g., K = -2) is determined to increase the variable amount, and if the deviation of other polarities persists, the gain (e.g., K = -0.25) is determined according to the deviation reduction state. 9 is performed through the frequency regulator 91 shown in Fig. 9. First, the regulator 91 receives a digital signal indicating a frequency deviation from the frequency deviation detection unit 90 and receives a shift register 92 made of a delay element. The number of bits of the state function is determined by the number of delay elements of this register 92. The delay element is composed of a D-flip flop that delays and stores the signal. In this way The state function is then processed by the state function processor 93. The state function processor 93 includes a state switch controlled according to the state function value The number of terminals of the state switch depends on the number of bits of the state function. The frequency deviation control signal, which is determined according to the value of the state function, has a variable step size, and the initial step size is the state when all the state values of the registers match, that is, 11 or 0. It has a structure in which the frequency deviation signal is increased according to the number of repetitions as long as the time is maintained (an integer multiple of the zero crossing period of the I-channel input signal), while the value of 10 or 1 is increased. The frequency deviation control signal has a structure that reduces the size (when switching to the STATE3 terminal). In the case of designing to be reduced by 1/2 or 1/4, a simple signal processing technique using register shift processing of binary signal processing can be used, etc. Through this process, the characteristics of channel change (Doppler frequency shifting OSC lift, etc.) can be used. Granular noise can be almost eliminated in order to track the frequency error caused by However, because the frequency deviation control signal is small enough, it is unable to keep up with the input frequency deviation as it goes through the repetition process.

) Is configured to include an input circuit 95. Initial value applied in increasing state

Depending on the slope overload distortion may also increase, the initial value

Should be adjusted to the limiting requirements. Here, the slope overload distortion means that the control signal adaptation speed of the spreader does not sufficiently follow the change characteristic in the state where the frequency deviation change is large. Referring to FIG. 9, the initial output value of the state processor 93 is fed back to be delayed by one sample period through the delay element 97, and then the code is removed while passing through the absoluteizer 96. In the comparator 95A, the fed back value and the initial value

Are compared to generate a selection signal SEL. The selector 95B then outputs one of the A and B terminals in accordance with the selection signal. Frequency deviation is the initial value

If larger, a signal corresponding to the deviation is output and multiplied by the multipliers 94A and 94B in the gain regulator 94, for example, 2 times and -2 times, respectively. At this time, the state switch performs a switching function according to the state function of the next cycle to connect the output of one of the multipliers 94A and 94B to the output terminal. This operation is automatically repeated every cycle. In other words, the initial step size has a structure in which the frequency deviation signal is increased according to the number of repetitions when all the state values of the state function generator 92 match. In contrast, when the state function is in a reduced state, the variable step size of the gain control signal converges. In this process, the output value of the state processor 93 is fed back and delayed by one sample period through the delay element 97, and then passes through a -1/2 or -1/4 multiplier 94C in the gain adjuster 94. The frequency deviation converges. The frequency deviation control signal generated in this manner is integrated via the integrator 98 to act as a frequency synthesizer (VCO) control signal. The amount of change in the VCO control signal is determined by the digital resolution of the frequency control unit and the change in the gain value of the control signal versus the output signal applied to the voltage controlled oscillator (VCO). 12 shows an example through simulation of dynamic characteristics of an estimated value obtained through a frequency tracking process when a frequency deviation input of 1000 Hz is applied by applying the algorithm of the present invention. The number of status bits used here is two, and it can be seen that the control signal generation speed varies in proportion to the frequency difference between the input frequency deviation and the estimated value. It can be seen that if the frequency difference between the estimated value of the VCO control signal and the given input frequency deviation is sufficiently small, the density of generation of the control signal is greatly reduced, and thus has a stabilization characteristic of maintaining a constant value for a considerable period. In the simulation of Fig. 12, the integrator operation that generates the VCO control signal from the frequency deviation control signal was processed by arithmetic addition. However, since the integrating circuit using the RC low pass filter can be used in the actual system, the components that change instantly are alleviated. appear. The control signal generation process proportional to the frequency difference can provide much more stable performance than the conventional synchronization circuit. The reason is that the conventional synchronization circuit is continuously affected by noise regardless of the frequency deviation amount in order to quickly track the sudden frequency deviation caused by OSC drift, etc., while the present invention provides oscillation frequency according to the state characteristic of the frequency error. This is because the control signal level has a structure that minimizes the density of change. At this time, the maximum amount of processing frequency depends on the sample rate and the state level number L of the input phase estimation signal, and the maximum tracking frequency (input frequency deviation) is determined by the state level number (L) and the input sampling rate (Fs). Limited to Fs / (2L + 1). Through this entire process, the present invention minimizes the temporal exposure density of noise introduced into the VCO control signal, thereby keeping the frequency error within a predetermined range, thereby obtaining stable demodulation performance.

In the frequency tracking system according to the present invention as described above, a stable demodulation performance can be obtained by minimizing the temporal exposure density of noise introduced into the VCO control signal so that the frequency error is within a certain range, and in the conventional system. Compared to this, the effect of noise can be reduced while reducing the size of computation, real-time throughput, and system complexity.

Claims (19)

An apparatus for adaptively adjusting the oscillation frequency of a frequency synthesizer in a wireless receiver system comprising a frequency synthesizer, Means for detecting a frequency deviation from the I-channel and Q-channel input signals; And Means for controlling a frequency deviation in accordance with the output of said frequency detecting means, The frequency deviation detection means, First hard decision means for hard determining an I-channel input signal and converting it into a binary signal; Second hard decision means for hard determining a Q-channel input signal and converting it into a binary signal; And Means for generating a frequency error increase and decrease signal from output signals of the first and second hard decision means, The frequency deviation control means, Means for delaying and storing the output signal of the frequency deviation detecting means for a predetermined period; Means for delaying and feeding back the output of said frequency deviation control means for a predetermined period; Means for absoluteizing the output values of the delay and feedback means; Comparing and selecting means for selecting and outputting a larger one of the two signals by comparing the output of the absolute means with a predetermined reference value; Gain adjusting means having a plurality of output stages configured to multiply outputs of the delay and feedback means and outputs of the comparing and selecting means, respectively, and output the results to different output stages; Switching means for selectively outputting the output of one of the plurality of output stages of the gain adjusting means in accordance with the output of the frequency deviation detecting means and the output of the delay and storage means; And Means for generating a control signal for controlling said frequency synthesizer from said switching means output. The method of claim 1, The frequency error increase and decrease signal generating means, First delay means for delaying the output of said first hard decision means by a predetermined period; Second delay means for delaying the output of said first delay means by a predetermined period; Third delay means for delaying the output of said second delay means by a predetermined period; First modulo-2 calculating means for modulo-2 calculating the output of said first delay means and the output of said second delay means; Second modulo-2 calculating means, enabled according to the output of the first modulo-2 calculating means, for modulo-2 calculating the output of the first hard decision means and the output of the third delay means; And Third modulo-2 calculation means for enabling modulo-2 operation of the output of the first hard decision means and the output of the second hard decision means, enabled according to the output of the second modulo-2 calculation means Frequency control device comprising a. The method of claim 2, The first and third delay means delay each L (L is an integer) sampling period, And said second delay means delays by one sampling period. The method of claim 1, And said delay and storage means comprises a plurality of D-flip flops. The method according to claim 1 or 2, And an output signal of the frequency detecting means and an output signal of the delaying and storing means each consist of 1 bit. The method of claim 5, The gain adjusting means, First increasing means for increasing the output of said comparing and selecting means in the (+) direction; Second increasing means for increasing the output of said comparing and selecting means in the negative direction; And And reducing means for reducing the output of said comparing and selecting means. The method of claim 6, The gain factor of the first increasing means is 2; The gain factor of the second increasing means is -2; And the gain factor of said reducing means is -1/4. The method according to claim 6 or 7, The switching means, Selecting and outputting the output of the reduction means when the output of the frequency detecting means and the output of the delay and storage means are different; And when the output of the frequency detecting means and the output of the delay and storage means are the same, one of the outputs of the first increasing means and the second increasing means selects and outputs the output. The method of claim 8, The switching means, If the output of the frequency detecting means and the output of the delay and storage means are all 1, select and output the output of the first increasing means; And outputting the output of the second increasing means when the output of the frequency detecting means and the output of the delay and storage means are all zero. The method of claim 1, Means for generating a control signal of said frequency synthesizer comprises an integrator. A radio frequency signal tuning step for downconverting the received radio frequency signal, separating the signal into I-channel and Q-channel signals, and then converting the signal into a digital signal; Phase detection means connected to said radio frequency tuning stage for detecting phases of said I-channel and Q-channel signals; Phase correction means for correcting a phase of an output signal of the radio frequency tuning step according to the output of the phase detection means; Demodulation means for demodulating the output signal of the phase correction means; Means for detecting a frequency deviation from the I-channel and Q-channel input signals; And Means for controlling a frequency deviation in accordance with the output of said frequency detecting means, The frequency deviation detection means, First hard decision means for hard determining the I-channel input signal and converting it into a binary signal; Second hard decision means for hard decision of the Q-channel input signal to convert to a binary signal; And Means for generating a frequency error increase and decrease signal from output signals of the first and second hard decision means, The frequency deviation control means, Means for delaying and storing the output signal of the frequency deviation detecting means for a predetermined period; Means for delaying and feeding back the output of said frequency deviation control means for a predetermined period; Means for absoluteizing the output values of the delay and feedback means; Comparing and selecting means for selecting and outputting a larger one of the two signals by comparing the output of the absolute means with a predetermined reference value; Gain adjusting means having a plurality of output stages configured to multiply outputs of the delay and feedback means and outputs of the comparing and selecting means, respectively, and output the results to different output stages; Switching means for selectively outputting the output of one of the plurality of output stages of the gain adjusting means in accordance with the output of the frequency deviation detecting means and the output of the delay and storage means; And Means for generating a control signal for controlling the oscillation frequency of the frequency synthesizer from the switching means output. The method of claim 11, The frequency error increase and decrease signal generating means, First delay means for delaying the output of said first hard decision means by a predetermined period; Second delay means for delaying the output of the first delay means by a predetermined period; Third delay means for delaying the output of said second delay means by a predetermined period; First modulo-2 calculating means for modulo-2 calculating the output of said first delay means and the output of said second delay means; Second modulo-2 calculating means, enabled according to the output of the first modulo-2 calculating means, for modulo-2 calculating the output of the first hard decision means and the output of the third delay means; And Third modulo-2 calculation means for enabling modulo-2 operation of the output of the first hard decision means and the output of the second hard decision means, enabled according to the output of the second modulo-2 calculation means Wireless receiver system comprising a. A method for adaptively adjusting frequency in a wireless receiver system comprising a frequency synthesizer, the method comprising: A first hard decision step of hardly determining the I-channel input signal and converting it into a binary signal; A second hard decision step of hardly determining the Q-channel input signal and converting it into a binary signal; Identifying threshold crossings of the I-channel signal; When the I-channel signal crosses a threshold, generating a signal indicating increase or decrease of a frequency error according to the hard decision result; Determining a frequency adjusting gain of the frequency synthesizer according to the frequency error increase and decrease signal; Generating a control signal for controlling the frequency deviation in accordance with the determined frequency adjusting gain; And And generating a control signal for adjusting the oscillation frequency of the frequency synthesizer from the frequency deviation control signal. The method of claim 13, The frequency error increase and decrease signal generation step, A first delay step of delaying the first hard decision signal by a predetermined period; A second delay step of delaying the signal delayed in the first delay step by a predetermined period; A third delay step of delaying the signal delayed in the second delay step by a predetermined period; A first modulo-2 operation step of modulo-2 calculating the signal delayed in the first delay step and the signal delayed in the second delay step; A second modulo-2 operation step of modulo-2 calculating the signal determined in the first hard decision step and the signal delayed in the third delay step according to the signal calculated in the first modulo-2 operation step ; And According to the signal calculated in the second modulo-2 operation step, a third modulo modulo-2 operation of the hard decision signal in the first hard decision step and the hard decision signal in the second hard decision step And -2 calculating steps. The method of claim 13, And the threshold crossing is a zero crossing. The method according to claim 13 or 15, And the first and second hard decision steps are performed at a point separated by a L (L is an integer) sample period after a zero crossing. The method according to claim 13 or 14, Determining the frequency control gain of the frequency synthesizer according to the frequency error increase and decrease signal, Storing the frequency error increase and decrease signals to generate a state function; And And determining a frequency adjusting gain according to the state value of the state function. The method of claim 16, And said state function comprises two bits or three bits. The method of claim 17, The state function consists of 2 bits, When the state function is 11, it is defined as a state where the frequency deviation increases in the (+) direction. When the state function is 00, the frequency deviation is defined as a state where the frequency deviation increases in the (-) direction. 10 or 01, the frequency adjustment method characterized in that it comprises the step of defining the frequency deviation is reduced.

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