KR100207015B1 - Interface chip and internal register access method of interface chip - Google Patents

Abstract

The present invention relates to an interface chip and an internal register access method of an interface chip, and according to the development of a system and an ASIC, it is necessary to simultaneously support a large number of target devices, and for this, more internal chip of an interface chip is required. Only registers as many as the address of the device had to be utilized.

The present invention provides an internal register for controlling a target element, and when the system reads a predetermined specific address twice, an enable signal (EN) is applied to the internal register to enter the internal register access mode so that the register is accessed. And an internal access control block for controlling the access operation to be terminated according to an end signal, and each time the system reads / writes a register in the internal register access mode, the counter is set by one and the counter value is set in advance in the register. It consists of an interface chip consisting of a counter that sends an end signal to the internal access control block and a decoder that receives the output of the counter and outputs a decoded signal of the register. When the system reads a specific address twice consecutively, the internal register access mode Going into Otherwise, the first step in which data transfer is normally performed between the system and the target element, the second step in which the range of registers to be accessed, i.e., the start address and the end address, to be accessed in advance to the specific register (Reg_AO), If the counter value coincides with the end address set in the second step, it exits the internal register access mode and continues the initial operation. Otherwise, it continues to access the register until the end address is reached. An internal register access method of an interface chip is provided.

This has the effect of enabling the use of more registers than the number of addresses assigned to the target element of the invention.

Description

Interface chip and internal register access method of interface chip

The present invention relates to an interface chip and a method of accessing internal registers of the interface chip, and more particularly, to be able to use more registers than the number of addresses allocated to the target element when using an internal register in the interface chip that can control the target element. An interface chip and an internal register access method of the interface chip are provided.

FIG. 1 illustrates an interface chip 30 between a system bus 10 and a target bus 20. As shown therein, the interface chip 30 includes an internal register 32 that controls a target element (not shown). When the system reads a predetermined address twice, the enable signal EN is applied to the internal register 32 to enter the internal register access mode so that the register is accessed. It is composed of an internal access control block 31 which controls to terminate the access operation when the end signal is applied.

The internal register 32 is a register having the same address as the target element, and each bit in the register Reg_A has a completion bit 33 for completing access to the internal register 32 and a register (Reg_B) (Reg_C). Data for controlling the target element is input.

Referring to the operation of the interface chip 30 between the conventional system bus and the target bus configured as described above are as follows.

Usually the target element has several access addresses.

For example, in order to access a hard disk, addresses of 1FO to 1F7 and 3F7 are allocated and written among the input / output port addresses.

In addition, due to the development of the system and ASIC, many functions have been added to further develop from the simplicity of controlling only the target device, thereby increasing the role of the interface chip 30 between the system and the target device. In order to perform, a register is placed in the interface chip 30 to perform its role.

Next, a method of reading / writing the register 32 to the interface chip 30 having a predetermined address and not the target element based on the interface chip 30 configured as shown in FIG. 1 will be described with reference to FIG. 2. .

First, when the power is turned on, the system attempts to access the target device via the system bus 10. If the system does not read a predetermined specific address twice, the interface chip 30 is connected to the target device. Pass the signal as it is.

That is, data transfer is made between the system and the target device.

However, when the system reads a specific address twice consecutively, the interface chip 30 recognizes that the system wants to transmit data with itself, breaks the path with the target element, and transmits data with the system.

That is, it enters the internal register access mode.

Thereafter, when the system completes the access of the internal register 32 of the interface chip 30 and no longer requires data transmission with the interface chip 30, setting the completion bit 33 of the register (Reg-A) ( If set, the interface chip 30 exits the internal register access mode and subsequent operations start from the initial state.

The operation of this interface chip 30 will be described by way of example.

Assuming that the system writes addresses 1F0 to 1F7 to access the target device, the specific address 1F0 is read twice in succession to access the interface chip 30 between the system and the target device.

Then, the interface chip 30 enters the internal register access mode, and the addresses 1F0 to 1F7 accessed thereafter are used to access the internal register 32 of the interface chip 30 and not the target device.

When one bit of the address 1F0, that is, the completion bit 33 is set when the above access is completed, an end signal is transmitted to the internal access control block 31 to transmit the interface chip 30. Exits the internal register access mode and subsequent operations start from the initial state.

However, according to the development of the system and ASIC, it is necessary to support many target devices at the same time and require more internal registers 32 of the interface chip 30 for this purpose. There is a problem that only the number of registers can be utilized.

The present invention was devised to solve the above-described conventional problem. When the system bus reads a specific address twice so that the interface chip enters the internal register access mode, the number of registers to access a specific register can be specified. Therefore, an object of the present invention is to provide an interface chip and a method of accessing an internal register of the interface chip so that the internal register can be accessed even with a small number of addresses.

1 is an internal configuration diagram of a conventional interface chip.

2 is a flowchart illustrating an internal register access method of a conventional interface chip.

3 is an internal configuration diagram of an interface chip of the present invention.

4 is an operation flowchart showing a register access method of an interface chip of the present invention.

5 is another embodiment of the invention, the configuration diagram of the interface chip consisting of two register blocks.

* Explanation of symbols for main parts of the drawings

100: system bus 200: target bus

300: interface chip 310: internal access control block

320: counter 330: internal register

340: decoder 400: interface chip

410: register block (A) 411: internal register (A)

412: Counter (A) 413: Decoder (A)

420: register block (B) 421: internal register (B)

422: counter (B) 423: decoder (B)

The interface chip of the present invention for achieving the above object is shown in Figure 3, the interface chip 300, the internal register 330 for controlling the target element, and when the system reads a predetermined specific address twice An internal access control block for applying an enable signal EN to the internal register 330 and entering an internal register access mode to access the register 330 and to terminate the access operation according to a termination signal ( 310 and each time the system reads / writes the register 330 in the internal register access mode, and counts one by one to set the counter value preset in the register 330 to the internal access control block 310. A counter 320 for sending an end signal and a decoder 340 for receiving the output of the counter 320 and outputting the decoded signal of the register 330. It is composed.

In addition, the register 330 has the same address as the target element and has a register Reg_A0 for setting a range of an internal register to be accessed in the internal register access mode, and an address irrelevant to the target element. It is addressed by the range set in Reg_A0) and consists of registers (Reg_A1 ~ Reg_A16) on which data to be utilized by the system is loaded.

In the internal register access method of the interface chip configured as described above, as shown in the operation flowchart of FIG. 4, when the system reads a specific address twice in succession, the internal register access mode is entered. Otherwise, data transfer is normally performed between the system and the target device. If the counter value matches the first step and the range of registers to which the specific register Reg_A0 is to be accessed, that is, the start address and the end address preset, the internal register access mode is exited and the initial operation is continued. Otherwise, the third step is to access the register continuously until the end address is reached.

The present invention will be described in more detail as follows.

First, when the power is turned on, the system attempts to access the target device through the system bus 100. If the system does not read a predetermined specific address twice, the interface chip 30 is connected to the target device. Pass the signal as it is.

That is, data transfer is made between the system and the target device.

However, if the system reads a particular address (ie, input / output port address) twice in succession, the interface chip 30 recognizes that the system wants to transfer data with itself, and breaks the path with the target device and And data transfer.

That is, it enters the internal register access mode.

Once the internal register access mode is entered, the system writes the range of registers to be accessed to the internal register 330 increment register (Reg_A0).

That is, the upper 4 bits write the number of the register to start and the lower 4 bits write the number of the register to end.

For example, writing '10001111' means accessing registers 8-16.

Thereafter, when the system reads / writes the registers Reg_A1 to Reg_A16 in the interface chip 30 with the address used to access the target element, the address used in this manner is not used for addressing the internal registers. As shown, it is addressed by the value of the register Reg_A0.

For example, after the register (Reg_A0) is set to the data used earlier, read / write access in the system causes the counter 320 to be counted by one, which makes the number of internal registers to be accessed next. The order is made up to the end address input to the counter 320.

Completed by the access counter 320 of the internal register 330. That is, when the end address preset in the register (Reg_A0) and the counter value in the internal register 330 are the same, the end signal is set to the internal access control block 310 to exit the internal register access mode. do.

In this way, an end signal is set in the internal access control block 310 to exit the internal register access mode to disconnect the system from the interface chip 300 and to make a path between the system and the target device to make an initial state. .

5 is intended to extend the number of registers accessible by these two values when the system has two addresses when accessing a target element, that is, when the system has addresses of registers Reg_A0 and Register_B0. .

A counter range is set in the register Reg_A0 and a counter range for another register group is set in the register Reg_B0. The operation thereof is as follows.

When the access of the register block A is completed by the register Reg_A0, the counter (A) 412 transmits an end signal to the counter (B) 422 and the counter (B) 422 When enabled, counting starts. When the counter value reaches a preset value in the register Reg_B0, an end signal is sent to the internal access control block 410 to exit the internal register access mode.

That is, return to the initial state.

As described above, the present invention has the effect of enabling the use of registers more than the number of addresses allocated to the target element.

That is, the number of internal registers that can be allocated by one target address is a maximum of 16 when one register is 8 bits, and an address of 16 × n internal registers is possible when there are n target addresses.

Claims (6)

The internal register controlling the target device, and when the system reads a predetermined predetermined address twice, the enable signal (EN) is applied to the internal register and enters the internal register access mode to enable the register access and the end signal. An internal access control block for controlling an access operation to be terminated according to the < RTI ID = 0.0 > and < / RTI > And a counter for sending an end signal to the block and a decoder for receiving the output of the counter and outputting a decoded signal of the register. The register of claim 1, wherein the register has the same address as a target element and sets a range of an internal register to be accessed in an internal register access mode, and is set in the register Reg_A0 regardless of a target element. An interface chip, which is addressed by one range and composed of registers (Reg_A1 to Reg_A16) on which data desired to be utilized by the system is loaded. 3. The interface chip according to claim 2, wherein the number of internal registers that can be allocated by one target address is configured to be an address of 16 x n internal registers when there are n target addresses. If the system reads a specific address twice consecutively, it enters the internal register access mode; otherwise, the first step in which data transfer is normally performed between the system and the target device; If the counter value coincides with the end address previously determined in the second step while the register access operation is performed and the register access operation is performed in advance, the internal register access mode is exited and the initial operation is continued. And a third step of accessing the register continuously until the end address is reached. By connecting two register blocks (A) (B) having respective registers (Reg_A0) (Reg_B0) addresses with each other's counters, when access of one block (A) is terminated, another block (B) is accessed. Interface chip, characterized in that configured to expand the number of accessible registers. If you have two registers (Reg_A0) (Reg_B0), set the range of the counter in each register (Reg_A0) (Reg_B0). Then, when access to one register block (A) is finished, the counter (A) A method of accessing an internal register of an interface chip, characterized by sending an end signal to another counter (B) so that another register block (B) is accessed.