KR100206708B1 - Non-volatile semiconductor memory device and fabrication method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device for improving insulation capability and device isolation characteristics by increasing the thickness of an insulating film of a field oxide film in a non-self-aligned fin structure having a high coupling ratio. A plurality of bit lines and a plurality of word lines, memory chips formed at portions where the bit lines and word lines intersect, a wafer array formed of the memory chips, a first conductive layer formed on the memory chips, respectively; A nonvolatile semiconductor memory device having a second conductive layer formed by stacking an upper portion and four sides of a first conductive layer, the nonvolatile semiconductor memory device comprising: a first insulating layer having a predetermined thickness on an entire surface of a substrate and forming active regions; A plurality of device isolation layers having a predetermined thickness so as to be disposed between the plurality of device isolation layers; A third insulating film having a predetermined thickness between the layers and on the upper surfaces of the device isolation layers; and a lower surface of the third insulating film having an upper surface and four sides of the first conductive layer and an upper surface of the third insulating film. The second insulating film is formed to have a predetermined thickness between the two conductive layers.

Description

Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a stacked gate in which a floating gate (hereinafter referred to as F / G) and a control gate (hereinafter referred to as C / G) are stacked on a semiconductor substrate. The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, which can improve a field isolation characteristic between a fin and a fin while increasing a coupling ratio in a stack gate structure.

Generally, in the data processing system, the memory devices for storing information can be classified into a volatile memory device and a nonvolatile memory device in terms of storage and retention. In the volatile memory device, the memory contents are destroyed when the power supply is interrupted, whereas in the nonvolatile memory device, the memory contents are maintained without being destroyed even when the power supply is interrupted. Such nonvolatile memory devices may be classified into Read Only Memory (ROM), Programmable ROM (PROM), Eraserable PROM (EPROM), and Electrically EPROM (EEPROM). Among these, there is a growing demand for ypyrom which can program and erase data using an electric method. Among these nonvolatile memory devices, EPIROM or Flash EEPROM having a batch erase function is a stack in which F / G and C / G are stacked on a semiconductor substrate on which a source and a drain are formed. It has a type gate structure. This pyrom is a NOR type in which each transistor is connected in parallel between a bit line (hereinafter referred to as BL) and a ground line, and several transistors are connected in series. The unit strings can be divided into NAND types in which unit strings are connected in parallel between BL and ground lines. NAND type is advantageous for high integration of a large-capacity memory cell. The basic NAND fin structure is described in detail in page 3334 of a paper entitled Symposium on VLSI Technology, published in 1988 in the United States. Typically, programming operations in EPI or flash EPIROM are performed by tunneling electrons from the drain region or the bulk region to the F / G, and an erase operation is performed inversely to the programming operation. By tunneling electrons from the drain region to the bulk region. Herein, an insulation layer formed between F / G and C / G ensures capacitance required for a program operation, an erase operation, and a read operation. Non-volatile memory such as Ipyrom or Flash Ipyrom requires high voltage during program operation, which makes insulation characteristics between active regions an important factor. This is because the device isolation characteristic from and unselected BL becomes weak. One method of strengthening the insulation capability is to increase the thickness of the field oxide film. However, as the memory devices are highly integrated, the width of the field oxide film, which is an insulating area for device isolation, is rather reduced. The thickness of the field oxide film which can be grown by ordinary thermal oxidation is also relatively reduced. Therefore, as the device is highly integrated, a fin structure having a lower program voltage and enhanced device isolation characteristics is required to enhance device isolation characteristics.

In the program operation, the program voltage applied to C / G is coupled to the capacitance between the series connected F / G and C / G and the capacitance between F / G and the substrate to apply voltage to F / G. One method for programming at G voltage is to increase the coupling ratio to increase the rate at which the voltage applied to C / G is induced to F / G, thereby reducing the voltage induced across the Tunnel Oxide to C / G. The program can be kept constant regardless of the lower voltage of. As described above, the capacitance described above is proportional to the dielectric constant of the insulating film between the two electrodes, that is, the dielectric film, and the overlapping area between the two electrodes, and is inversely proportional to the thickness of the dielectric film between the two electrodes. In addition, when the program voltage is lowered, in order to generate a program voltage or to transfer the generated program voltage to C / G of 쎌, the use voltage or applied voltage of the transistor or capacitance constituting the logic circuit is lowered, so that the breakdown voltage of the oxide film ( It is possible to improve reliability deterioration factors such as a decrease in breakdown voltage, a breakdown voltage of a transistor, or a hot carrier caused by current generation, in this case, a decrease in insulation characteristics due to hot electrons.

1A and 1B are process cross-sectional views in a word line direction and a bit line direction of a nonvolatile memory chip according to an embodiment of the prior art. Referring to FIG. 1A, the structure of a conventional self-aligned conventional Y pyrom or flash Y pyrom in the word line direction is a plurality of active regions and field regions parallel to the substrate 1. The first insulating film 21, for example, a turnel oxide film, is formed on the substrate in the active region. A first conductive layer 31, for example, F / G, is formed on the first insulating layer by patterning the active and field portions on the first insulating layer. A second insulating film 23, for example, a dielectric film is formed on the upper surface thereof, and the second electrode layer 32, for example, C / G is formed on the front surface of the second insulating film 23 by wrapping the F / G 31 in the word line direction. Is formed. That is, it has a laminated structure. Referring to FIG. 1B, the first insulating layer 21 and the F / G 31, the second insulating layer 23, and the C / G 32 are sequentially stacked on the first substrate on which the source and the drain are formed in the BL direction. In the flash Y pyrom structure according to the prior art, two cross-sections of the F / G 31 side surface overlap C / G 32 in the word line direction, but two cross-sections of the F / G side C / G side in the BL direction. The structure does not overlap with. Capacitance between F / G and C / G uses only two cross-sections of the F / G side that are overlapped with C / G in the word line direction, and the F / G top section and F / G in BL direction that does not overlap C / G. The two cross sections on the side are not available. That is, C / G and F / G overlap in the word line direction, but do not overlap in the BL direction. In order to make such a conventional self-aligned stacked gate structure, the ohmic of the F / G sidewall during the self-matching etching process of etching the stacked multiple layers between the word line and the word line with a single mask. Since the ONO: Oxide Nitride Oxide (PE) film is erected in the shape of a cross section, it becomes thicker than the O / O film on the top of the F / G. In this case, a problem arises in that the F / G sidewall is left without removing all of the ohio layer. 2A and 2B are cross-sectional views illustrating a state of forming a floating gate according to an embodiment of the prior art, respectively. 2A and 2B, FIG. 2A shows a floating gate in an inclined shape inward (left). Figure 2b shows a floating gate in the form of a slope in the outer (right) direction. For the reason as described above, it is difficult to make the profile of the side (Profile) completely vertical in the etching process for forming the F / G, and in the normal process it is inclined to the left or right as shown in the cross-sectional view, as shown in Figs. 2a and 2b, As shown in FIGS. 3A and 3B to be described later, the first conductive layer 31, for example, polysilicon, which is under the remaining ohio film, which is not removed at all, is difficult to etch due to a shadowing effect. Problems that remain rather than become prone to occur. This phenomenon is the main cause of the failure of the memory 쎌 caused by the conduction between the word line and the word line. 3A and 3C are cross-sectional views illustrating residual polysilicon generation and field oxide film loss during a self-aligned etching process according to an embodiment of the prior art. Referring to FIG. 3A and FIG. 3C, FIG. 3A shows the result after etching the ohmic film in the state of FIG. 2A. FIG. 3B shows the result after etching the ohio film in the state of FIG. 2B. FIG. 3C shows a state of being deeply etched into the field oxide layer 14 in order to completely remove the residual ONO layers of FIGS. 3A and 3B. That is, FIG. 3C is excessively etched by the thickness of the ohmic layer during the ohmic layer etching to prevent conduction between the word line and the word line. The loss of the field oxide layer 14 causes the insulation characteristics between the active regions to be weak.

4A and 4B are cross-sectional views of a bit line direction and a word line direction of a nonvolatile memory chip according to another embodiment of the prior art, respectively. As shown in FIGS. 4A and 4B, a non-self-aligning Y-pyrom or flash Y-pyrom structure for increasing the coupling ratio, the first conductive film on top of the substrate via the first insulating film 21 For example, F / G is formed. Unlike the fin structure of the self-aligned flash Y pyrom as shown in FIGS. 1A and 1B described above, the second conductive layer 32 (32-1,32-) is formed not only in the word line direction but also in the BL direction through the second insulating layer 23. 2) For example, C / G is not self-aligned and the first conductive layer 31, for example, has a structure surrounding the F / G. The non-self-aligned flash Y pyromium structure has a good effect in terms of increasing the coupling ratio since C / G 32 surrounds four sections of the F / G 31. However, in the conventional manufacturing process in which the structure in which the second insulating film 23, for example, the F / G 31 is overlapped in the BL direction through the ohio film, is patterned through a photolithography process, that is, a photo process, misalignment occurs. There is a disadvantage in terms of design rule scale down compared to the above self-aligned structure due to overlap margin due to the above-mentioned self-aligned structure, and C / which overlaps the active region via the second insulating layer 23. When the program operation is applied to the G 32 region, there is a problem in that the insulating film characteristics become weak due to hot carrier generation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device and a method of manufacturing the same for improving the insulating ability and device isolation characteristics by increasing the thickness of an insulating film of a field oxide film in a self-aligned fin structure having a high coupling ratio.

1A and 1B are cross-sectional views of a word line direction and a bit line direction of a nonvolatile memory chip according to one embodiment of the prior art, respectively.

2A and 2B are cross-sectional views illustrating a state of forming a floating gate according to an embodiment of the prior art, respectively.

Figure 3a is a cross-sectional view showing the remaining polysilicon generation and field oxide film loss during the self-aligned etching process according to an embodiment of the prior art.

4A and 4B are cross-sectional views of a bit line direction and a word line direction of a nonvolatile memory chip according to another embodiment of the prior art, respectively;

5A and 5B are cross-sectional views illustrating a process of forming a field oxide film for device isolation in bit and word line directions, respectively, according to an embodiment of the present invention;

6A and 6B are cross-sectional views illustrating the formation of floating gates in bit line and word line directions, respectively, according to one embodiment of the present invention;

6C and 6D are layout views each showing a forming state of the floating gate.

6E and 6F are layout views showing a photolithography process for forming a floating gate.

7A and 7B are cross-sectional views illustrating the formation of an insulating film for enhancing field oxide film characteristics in bit line and word line directions, respectively, according to one embodiment of the present invention;

8A and 8B are cross-sectional views illustrating the formation of an insulating film, a conductive film, and an oxide film in bit line and word line directions, respectively, according to an embodiment of the present invention;

9A and 9B are cross-sectional views illustrating patterning of oxide masks in bit line and word line directions, respectively, according to an embodiment of the present invention;

10A and 10B are cross-sectional views illustrating the formation of a final flash Y pyrom in the bit line and word line directions, respectively, in accordance with one embodiment of the present invention;

According to the technical idea of the present invention for achieving the above object, a plurality of bit lines and a plurality of word lines orthogonal to each other at a predetermined interval, memory beams formed in the intersection portion of the bit line and the word line, and the memory A nonvolatile semiconductor memory device having a fin array formed of fins, a first conductive layer each formed on a substrate of the memory fin, and a second conductive layer formed by stacking the upper and four sides of the first conductive layer. A first insulating layer formed on the entire surface of the substrate to have a predetermined thickness to form active regions, a plurality of device isolation layers formed to have a predetermined thickness so as to be disposed between the active regions and separated from each other, between the first conductive layers and A third insulating film having a predetermined thickness on upper surfaces of the device isolation layers, and a lower surface of the first insulating layer on an upper surface and four sides of the first conductive layer; And a second insulating film formed on the upper surface of the third insulating film and having a predetermined thickness between the first conductive layer and the second conductive layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings.

5A and 5B are cross-sectional views illustrating a process of forming a field oxide film for device isolation in bit and word line directions, respectively, according to an embodiment of the present invention. 5A and 5B, FIG. 5A shows a vertical cross sectional view in the bit line direction. 5B shows a vertical cross sectional view in the word line direction. Here, a field oxide film 14 having a thickness of about 3000 kPa to 6000 kPa is formed in a predetermined region of the semiconductor substrate 1. In this case, in order to further improve device isolation characteristics on the surface of the semiconductor substrate 1 under the field oxide layer 14, doped ions are implanted at a higher concentration than the semiconductor substrate 1 to form the field ion implantation region 4 together.

6A and 6B are cross-sectional views illustrating the formation of F / G in the bit line and word line directions, respectively, according to an embodiment of the present invention. 6A and 6B, after the process of FIGS. 5A and 5B, the first insulating layer 21, for example, a thin oxide layer or an oxynitride layer having a thickness of about 70 μs to 100 μs is formed on the surface of the semiconductor substrate between the field oxide layers 14. do. Subsequently, a doped first conductive layer 31 having a thickness of about 3000 Å to 4000 Å is formed on the entire surface of the substrate 1 on which the first insulating layer 21 is formed, and then patterned to form the tunnel oxide layer, for example, the first as shown in the layout of FIG. 6C. The predetermined area | region of the edge of the insulating film 21 and the adjacent field oxide film 14 on both sides is covered, and F / G independent from neighboring F / G is formed. 6C and 6D are layout views showing the formation state of the floating gate, respectively. FIG. 6C is a first embodiment for forming the F / G pattern, and forms the F / G 31 on the first insulating layer 21 in one photo etching process using the same photo mask as shown in the layout. This method has a disadvantage in that it is difficult to form a process in the form of an accurate rectangular shape because the rectangular F / G pattern is patterned as an oval as shown in FIG. 6D by a loading effect, for example, a 3D effect. have. 6E and 6F are layout diagrams showing a photolithography process for forming a floating gate. 6E and 6F, first, an F / G pattern (FIG. 6E) in the BL direction is formed by using two photolithography processes, and then an F / G pattern (FIG. 6F) in the word line direction is formed. . In this case, when the F / G pattern is formed in the BL direction, channel stop impurity ion implantation may be performed to enhance the Z-field insulation characteristic. Next, Y-type impurity ion implantation is performed at an energy level that does not pass through the field oxide film to form a source and a drain.

7A and 7B are cross-sectional views illustrating the formation of an insulating film for enhancing field oxide film characteristics in bit line and word line directions, respectively, according to an embodiment of the present invention. Referring to FIG. 7A, a third insulating layer 22, for example, an oxide layer, is formed by chemical vapor deposition (CVD) to have a thickness of about 3000 μm to 4000 μm across the entire surface to fill the step between F / G 31. Thereafter, the third insulating layer 22, for example, the oxide layer is etched so that a predetermined F / G (2000 kV to 3000 kV 31) is formed on the field oxide layer 21 while leaving a third insulating layer having a predetermined thickness, for example, about 1000 kV.

8A and 8B are cross-sectional views illustrating the formation of an insulating film, a conductive film, and an oxide film in bit and word line directions, respectively, according to an embodiment of the present invention. 8A and 8B, a second insulating layer, for example, an ohmic layer 23, and a second conductive layer 32 (32-1, 32-2), for example, C / G, are sequentially formed on the entire surface. Here, the ohio film is preferably formed to have a thickness of 150 kPa to 200 kPa in terms of oxide film by laminating a 100 kPa to 200 kPa nitride film on a 80 kPa thermal oxide film, and thermally oxidizing the second conductive layer 32 (32-1, 32-2). ) Is formed by depositing doped polysilicon 32-1 of about 1000 kV to 3000 kV and by depositing 1000-2000 kPa of silicide 32-2, a metal-silicon compound, to increase the conductivity on top thereof. do. Subsequently, in order to facilitate the subsequent etching of the second conductive layer to form a word line, which is a subsequent process, the deposition thickness during the deposition of polysilicon forming the second conductive layer 32 may be sufficient to fill all of the F / G steps. To be the thickness of. After depositing the second conductive layer 32, a fourth insulating layer, for example, an oxide layer 24 is deposited to a thickness of about 2000 kPa to about 3000 kPa using a chemical vapor deposition method to be used as an etching process mask for forming a word line.

9A and 9B are cross-sectional views illustrating patterning of an oxide mask in bit line and word line directions, respectively, according to an exemplary embodiment of the present invention. 9A and 9B, the pattern of the oxide layer 24 is formed in the word line direction by using a photolithography process, and the oxide layer 24 of the oxide layer 24 is provided to give a mismatched margin for the C / G to overlap the F / G in the BL direction. A fifth insulating layer 25, for example, an oxide spacer is formed in the pattern. The oxide spacer 25 is formed by etching back the oxide film formed by chemical vapor deposition at about 1000 Å.

10A and 10B are cross-sectional views illustrating the formation of a final flash Y pyrom in the bit line and word line directions, respectively, according to one embodiment of the invention. 10A and 10B, second conductive layers 32 (32-1 and 32-2) are etched using the oxide pattern, that is, oxide spacer 25 as a mask, and four cross-sections of F / G in the word line and the BL direction are etched. / G is wrapped and completes the flash Y pyrom 형성된 where the third insulating film 22 is further formed on the field oxide film 21.

According to the present invention, the fin structure can reduce the program voltage by increasing the coupling ratio by increasing the overlapping area than the conventional self-aligned fins overlapping the sidewalls of both ends of the F / G only in the word line direction. In addition, since the oxide film is filled between F / G and F / G to increase the thickness of the field insulating film, the thickness of the insulating film between the substrate and the C / G layer is much thicker than the prior art having only the field oxide film, thereby improving the insulating ability. You can. This has the advantage that the separation length can be reduced, allowing scale down of the fins. In addition, by etching only the C / G layer during the etching process for forming the word line, it is possible to prevent the loss of the field oxide layer or the generation of residual polysilicon, which has been a problem in the conventional self-alignment etching for forming the fin. In the final pattern formation of the C / G overlapping the F / G in the bit line direction, the C / G pattern is not formed using only the photo mask, and the spacer is formed on the oxide mask along with the oxide mask. Since the C / G pattern is formed to overlap the C / G pattern, there is an effect that C / G can give a margin to the minimum design rule as much as the width of the oxide spacer formed in the photolithography process for overlapping the F / G.

Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (15)

A plurality of bit lines and a plurality of word lines orthogonal to each other at regular intervals, memory chips formed at portions where the bit lines and word lines cross each other, a wafer array formed of the memory chips, and an upper portion of the substrate of the memory chips; A nonvolatile semiconductor memory device having a first conductive layer formed and a second conductive layer formed by stacking the upper and four sides of the first conductive layer. A first insulating film formed on the entire surface of the substrate and having a predetermined thickness to form active regions; A plurality of device isolation layers formed to a predetermined thickness so as to be located between the active regions and separated from each other; A third insulating film formed between the first conductive layers and on an upper surface of the device isolation layers to have a predetermined thickness; A lower insulating surface having an upper surface and four sides of the first conductive layer and an upper surface of the third insulating layer and a second insulating layer formed to a predetermined thickness between the first conductive layer and the second conductive layer. Volatile semiconductor memory device. The nonvolatile semiconductor memory device of claim 1, wherein the first conductive layer and the second conductive layer are formed using different photo masks, respectively. The nonvolatile semiconductor memory device of claim 1, further comprising a fourth insulating layer on the upper surface of the second conductive layer, the fourth insulating layer having a width greater than or equal to a width of the first conductive layer and the width of the active region. The nonvolatile semiconductor memory device of claim 3, wherein the fourth insulating layer forms an oxide spacer. The nonvolatile semiconductor memory device of claim 1, wherein the first insulating layer is an oxide layer or an oxynitride layer. The nonvolatile semiconductor memory device of claim 1, wherein the second insulating layer is an ohon layer. The nonvolatile semiconductor memory device of claim 1, wherein the third insulating layer is an oxide layer. In the manufacturing method of a nonvolatile semiconductor memory device, Forming a field oxide film having a predetermined thickness to separate devices in a predetermined region of the semiconductor substrate, Forming an ion implantation region doped at a higher concentration than the semiconductor substrate on a surface of the semiconductor substrate under the field oxide film; Forming a first insulating film on a surface of the semiconductor substrate between the field oxide films; Forming a first conductive layer having a predetermined thickness on an entire surface of the substrate on which the first insulating film is formed; Patterning the first conductive layer to cover a predetermined region of the edge of the first oxide layer and the field oxide layer adjacent to both sides thereof, and to form a shape independent from the neighboring first conductive layer; Forming a source and a drain by implanting ions into an impurity opposite to that of the semiconductor substrate with energy sufficient to not pass through the field oxide layer on the upper surface of the semiconductor substrate; Forming a third insulating film having a predetermined thickness on a front surface thereof so as to fill a step between the first conductive layers; Etching the third insulating film to expose the first conductive layer at a predetermined distance while leaving a third insulating film having a predetermined thickness on the field oxide film; Depositing a second insulating film to a predetermined thickness on the entire surface; Forming a second conductive layer on the front surface; Forming a pattern using a photolithography process after forming a fourth insulating film deposited to a predetermined thickness for use as a mask; Forming a fifth insulating film with a predetermined thickness on the fourth insulating film pattern so as to give mismatch margin for the second conductive layer to overlap the first conductive layer in the bit line direction; Etching back the fifth insulating layer to form an oxide spacer; And etching the second conductive layer using the oxide spacer as a mask. 10. The method of claim 8, wherein the first conductive layer comprises two photolithography processes forming a first conductive layer pattern in a bit line direction and then forming a first conductive layer pattern in a word line direction. A method of manufacturing a volatile semiconductor memory device. The method of claim 8, wherein the first insulating layer is formed of an oxide layer or an oxynitride layer. 10. The method of claim 8, wherein the second insulating layer is formed of an ohio layer. 10. The method of claim 8, wherein the third insulating film is formed of an oxide film. 10. The method of claim 8, wherein the first conductive layer is made of polysilicon doped with impurities. The method of claim 8, wherein the polysilicon layer doped with the second conductive layer and the polyside layer are sequentially formed of a double layer. 10. The method of claim 8, wherein the fourth insulating film and the fifth insulating film are oxide films formed by chemical vapor deposition.