KR100204017B1 - Contact Forming Method of Semiconductor Device - Google Patents
Contact Forming Method of Semiconductor Device Download PDFInfo
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- KR100204017B1 KR100204017B1 KR1019950050949A KR19950050949A KR100204017B1 KR 100204017 B1 KR100204017 B1 KR 100204017B1 KR 1019950050949 A KR1019950050949 A KR 1019950050949A KR 19950050949 A KR19950050949 A KR 19950050949A KR 100204017 B1 KR100204017 B1 KR 100204017B1
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- -1 silicon ions Chemical class 0.000 claims abstract description 8
- 230000003213 activating effect Effects 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000004913 activation Effects 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체장치의 콘택형성방법에 관한 것으로, 기판 전면에 산화막을 형성하는 단계와, 상기 산화막을 선택적으로 식각하되, 일정두께만큼 식각하고 일정두께만큼은 남기는 단계, 상기 잔존하는 산화막 부위에만 선택적으로 실리콘을 이온주입하는 단계, 상기 주입된 실리콘 이온을 활성화시키는 단계, 및 상기 잔존하는 산화막을 식각하여 콘택을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 콘택 형성방법을 제공함으로써 콘택 형성시 문제가 되는 과도식각 및 식각부족 현상을 방지하여 기판 손상에 의해 발생되는 콘택 페일 및 접합파괴로 인한 누설전류에 기인하는 문제점들을 해결할 수 있도록 한다.The present invention relates to a method for forming a contact in a semiconductor device, comprising the steps of forming an oxide film on the entire surface of the substrate, selectively etching the oxide film, etching by a predetermined thickness and leaving a predetermined thickness, and selectively only remaining portions of the oxide film. Implanting silicon, activating the implanted silicon ions, and etching the remaining oxide film to form a contact, thereby providing a contact forming method of a semiconductor device. It prevents the problem of excessive etching and lack of etching to solve the problems caused by leakage current due to contact failure and junction breakage caused by substrate damage.
Description
제1도는 종래기술에 의한 콘택 형성공정에서 나타나는 문제점을 도시한 것이고, 제2도는 본 발명에 의한 반도체장치의 콘택 형성방법을 도시한 공정순서 단면도이다.FIG. 1 is a cross sectional view showing a problem occurring in a contact forming process according to the prior art, and FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 접합 영역 11 : 기판10 bonding area 11 substrate
12 : 산화막 12a : 잔존 산화막12: oxide film 12a: remaining oxide film
13 : 감광막 15 : 스페이서13: photosensitive film 15: spacer
본 발명은 반도체장치의 콘택 형성방법에 관한 것으로, 특히 안정된 계면상태를 갖는 콘택홀을 형성하는 방법에 관한 것이다.The present invention relates to a method for forming a contact of a semiconductor device, and more particularly to a method for forming a contact hole having a stable interface state.
반도체 소자 제조공정중 기판과 도선간의 접촉을 위한 콘택 형성공정은 소자의 집적도가 증가함에 따라 공정수가 많이 증가하게 되었다. 이와 같은 많은 콘택 형성공정중 여러 막들의 적층이 어느 수준 이상으로 누적된 토폴로지(topology)에서 안정적인 콘택을 형성하기는 매우 어려우며, 많은 시간이 요구된다.In the process of forming a contact for contact between a substrate and a conductive line in a semiconductor device manufacturing process, the number of processes increases as the degree of integration of a device increases. In many of these contact forming processes, it is very difficult and time consuming to form a stable contact in a topology in which stacks of various films are accumulated above a certain level.
상기와 같은 종래의 콘택홀 형성공정에서 가장 심각한 문제로 빈번히 나타나는 것으로는 식각이 충분히 이루어지지 않아 나타나는 콘택홀이 오픈되지 않는 문제와 과도식각으로 인해 나타나는 기판의 손상 문제를 들 수 있다. 이러한 문제는 모두 콘택 크기가 서브마이크론 이하로 감소하면서 발생하게 되는 것이다.The most serious problems in the conventional contact hole forming process as described above include a problem in which the contact hole is not opened due to insufficient etching and a problem of damage to the substrate due to overetching. All of these problems arise as contact size decreases below submicrons.
제1도는 상기 종래기술에 의한 콘텍 형성공정에서 나타나는 문제점을 도시한 것이다.FIG. 1 illustrates a problem in the contact forming process according to the prior art.
기판(1)상에 절연막으로서, 예컨대 산화막(2)을 형성하고 이위에 소정의 감광막패턴(3)을 형성한 후, 이 감광막패턴(3)을 마스크로 하여 상기 산화막(2)을 식각하여 콘택을 형성하는바, 제1도에 도시한 바와 같이 기판과 인접한 부분에서 과도식각 또는 식각부족 현상이 나타날 수 있다. 이와 같은 과도식각 및 식각부족현상은 동일한 웨이퍼내에서 같이 발생할 수 있는데, 식각이 부족하여 콘택이 완전히 오픈되지 않은 부분(A)을 식각하기 위하여 식각시간을 증가시킬 경우 과도식각이 이루어진 기판영역(B)이 손상되어 기판의 접합(4)이 파괴되는 결과를 초래할 수 있다.An oxide film 2 is formed on the substrate 1 as an insulating film, for example, and a predetermined photosensitive film pattern 3 is formed thereon. The oxide film 2 is etched using the photosensitive film pattern 3 as a mask and then contacted. As shown in FIG. 1, excessive etching or lack of etching may occur in a portion adjacent to the substrate. Such excessive etching and lack of etching may occur together in the same wafer. If the etching time is increased to etch the portion (A) where the contact is not fully opened due to lack of etching, the substrate region (B) having excessive etching ) May be damaged, resulting in breakage of the junction 4 of the substrate.
본 발명은 이와 같은 문제를 해결하기 위한 것으로, 과도식각으로 인한 기판의 손상 및 접합 파괴 현상을 방지하기 위하여 식각공정시 적정수준의 산화막을 남긴 후, 실리콘 이온을 주입하여 잔존 산화막이 폴리실리콘과 유사한 성질을 갖게 함으로써 산화막 건식식각 공정시 식각장벽층으로 활용하여 과도식각으로 발생되는 문제점을 해결할 수 있도록 한 반도체장치의 콘택형성방법을 제공하는데 그 목적이 있다.The present invention is to solve such a problem, in order to prevent damage to the substrate and damage to the junction due to over-etching, after leaving an appropriate level of oxide film during the etching process, the silicon oxide is injected to the remaining oxide film is similar to the polysilicon The purpose of the present invention is to provide a method for forming a contact of a semiconductor device, which can solve the problems caused by excessive etching by using it as an etch barrier layer in an oxide dry etching process.
상기 목적을 달성하기 위한 본 발명의 반도체장치의 콘택 형성방법은 기판 전면에 산화막을 형성하는 단계와, 상기 산화막을 선택적으로 식각하되, 일정두께만큼 식각하고 일정두께만큼은 남기는 단계, 상기 잔존하는 산화막 부위에만 선택적으로 실리콘을 이온주입하는 단계, 상기 주입된 실리콘 이온을 활성화시키는 단계, 및 상기 잔존하는 산화막을 식각하여 콘택을 형성하는 단계를 포함하여 이루어진다.The method of forming a contact of the semiconductor device of the present invention for achieving the above object comprises the steps of forming an oxide film on the entire surface of the substrate, selectively etching the oxide film, etching by a predetermined thickness and leaving a predetermined thickness, the remaining oxide film portion Selectively implanting silicon, activating the implanted silicon ions, and etching the remaining oxide film to form a contact.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명에 의한 반도체장치의 콘택형성방법을 공정순서에 따라 도시하였다.2 shows a method for forming a contact of a semiconductor device according to the present invention according to the process sequence.
먼저, 제2a도에 도시된 바와 같이 트랜지스터등과 같은 소자(10; 트랜지스터의 접합영역) 및 적정 수준 이상의 적층(도시하지 않음)이 형성된 반도체기판(11) 전면에 절연층으로서, 예컨대 산화막(12)을 형성한 후, 이위에 감광막을 도포하고 이를 소정의 콘택 마스크를 이용하여 선택적으로 노광 및 현상하여 감광막패턴(13)을 형성한다. 이어서 상기 감광막패턴(13)을 마스크로 하여 상기 산화막(12)을 일정두께만큼 건식식각하고, 일정두께만큼은 콘택형성부위에 남긴다. 이때, 통상적인 방법에서는 식각될 산화막의 두께보다 50%정도 과도식각을 하게 되는데, 본 발명에서는 통상적인 식각 범위에서는 식각 두께의 80-110%를 식각목표로 설정하여 식각을 행함으로써 잔존하는 산화막의 두께가 300-1000Å정도로 하는 것이 바람직하다.First, as shown in FIG. 2A, an oxide layer 12 is formed as an insulating layer on the entire surface of a semiconductor substrate 11 on which a device 10 (a junction region of a transistor) such as a transistor or the like and a stack (not shown) of an appropriate level or higher are formed. ), A photoresist film is applied thereon, and the photoresist film 13 is selectively exposed and developed using a predetermined contact mask to form the photoresist pattern 13. Subsequently, the oxide film 12 is dry-etched by a predetermined thickness using the photosensitive film pattern 13 as a mask, and a predetermined thickness is left in the contact forming portion. At this time, in the conventional method, 50% of the oxide film to be etched is excessively etched, and in the present invention, in the general etching range, 80-110% of the etching thickness is set as an etching target to perform etching. It is preferable to make thickness about 300-1000 mm <3>.
이어서 제2b도에 도시된 바와 같이 상기 감광막패턴(13)을 제거하지 않은 상태에서 실리콘(Si)을 상기 콘택 형성부위에 잔존하는 산화막(12A)에 이온주입한다. 이때, 이온 주입 조건은 10-20KeV정도의 에너지로 E15이상의 이온량을 갖는 실리콘을 주입한다. 이어서 주입된 실리콘 이온을 활성화시키기 위하여 600-800℃정도의 온도에서 RTP(rapid thermal process) 또는 로(furnace)를 이용하여 열처리를 행한다. 한편, 스텝 커버리지(step coverage) 향상등을 목적으로 제3도에 도시한 바와 같이 콘택내에 스페이서(15)를 적용하는 경우에는 스페이서 산화막의 증착시 주입된 실리콘 이온이 활성화되므로 상기와 같은 별도의 열처리공정은 필요없게 된다.Subsequently, as illustrated in FIG. 2B, silicon (Si) is ion-implanted into the oxide film 12A remaining at the contact forming portion without removing the photoresist pattern 13. At this time, the ion implantation conditions are implanted silicon having an ion amount of E15 or more with an energy of about 10-20KeV. Subsequently, heat treatment is performed by using a rapid thermal process (RTP) or a furnace at a temperature of about 600-800 ° C. to activate the implanted silicon ions. On the other hand, when the spacer 15 is applied to the contact as shown in FIG. 3 for the purpose of improving step coverage, the silicon ions implanted during the deposition of the spacer oxide film are activated. The process is not necessary.
다음에 제2c도에 도시된 바와 같이 상기 감광막패턴(13A)을 마스크로 이용하여 건식식각을 다시 행하여 상기 잔존하는 산화막(12A)을 완전히 제거함으로써 콘택을 형성한다. 이때, 제2도에 도시된 바와 같이 콘택내에 스페이서를 적용하지 않는 경우에는 1000-3000Å 정도의 산화막을 식각하고, 스페이서를 적용하는 경우에는 스페이서의 두께보다 1000-3000Å정도의 두께를 더 식각한다.Next, as shown in FIG. 2C, dry etching is performed again using the photosensitive film pattern 13A as a mask to form a contact by completely removing the remaining oxide film 12A. In this case, as shown in FIG. 2, when the spacer is not applied in the contact, an oxide film of about 1000-3000 mm 3 is etched, and when the spacer is applied, the thickness of about 1000-3000 mm 3 is etched more than the thickness of the spacer.
상기와 같은 본 발명의 콘택 형성방법에 있어서, 실리콘이 주입된 잔존하는 산화막은 열처리공정에 의해 폴리실리콘과 유사한 성질을 갖게 되어 콘택 형성을 위해 다시 식각될때 콘택 형성부위 이외의 영역에 남아 있는 산화막(12)과 상기 폴리실리콘화된 잔존산화막(12A)과의 식각선택비에 의해 상기 폴리실리콘의 성질을 갖는 잔존산화막(12A)이 산화막에 대한 식각 장벽층(barrier)을 역할을 충분히 할 수 있게 되므로 식각부족 현상 및 과도식각문제를 해결할 수 있게 된다.In the contact forming method of the present invention as described above, the remaining oxide film implanted with silicon has a property similar to that of polysilicon by a heat treatment process and remains in an area other than the contact forming part when it is etched again for contact formation. 12) and the remaining oxide film 12A having the properties of the polysilicon can sufficiently serve as an etch barrier layer for the oxide film by the etching selectivity between the polysiliconized residual oxide film 12A. Etching shortage and excessive etching problem can be solved.
이상 상술한 바와 같이 본 발명에 의하면, 콘택 형성시 문제가 되는 과도식각 및 식각부족 현상을 해결할 수 있게 되므로 기판 손상에 의해 발생되는 콘택 페일(contact fail) 및 접합 파괴로 인한 누설전류에 기인하는 모든 문제점들을 해결할 수 있다.As described above, according to the present invention, it is possible to solve the problem of excessive etching and lack of etching during the formation of the contact, and thus all of the leakage current due to contact fail and contact failure caused by substrate damage are caused. Problems can be solved.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050949A KR100204017B1 (en) | 1995-12-16 | 1995-12-16 | Contact Forming Method of Semiconductor Device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950050949A KR100204017B1 (en) | 1995-12-16 | 1995-12-16 | Contact Forming Method of Semiconductor Device |
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| KR970052271A KR970052271A (en) | 1997-07-29 |
| KR100204017B1 true KR100204017B1 (en) | 1999-06-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100685889B1 (en) | 2005-12-29 | 2007-02-26 | 동부일렉트로닉스 주식회사 | Manufacturing Method of CMOS Image Sensor |
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1995
- 1995-12-16 KR KR1019950050949A patent/KR100204017B1/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100685889B1 (en) | 2005-12-29 | 2007-02-26 | 동부일렉트로닉스 주식회사 | Manufacturing Method of CMOS Image Sensor |
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| KR970052271A (en) | 1997-07-29 |
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