KR100203897B1 - Device Separation Method of Semiconductor Device - Google Patents
Device Separation Method of Semiconductor Device Download PDFInfo
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- KR100203897B1 KR100203897B1 KR1019950050445A KR19950050445A KR100203897B1 KR 100203897 B1 KR100203897 B1 KR 100203897B1 KR 1019950050445 A KR1019950050445 A KR 1019950050445A KR 19950050445 A KR19950050445 A KR 19950050445A KR 100203897 B1 KR100203897 B1 KR 100203897B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000926 separation method Methods 0.000 title claims 2
- 238000002955 isolation Methods 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 125000006850 spacer group Chemical group 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 239000012528 membrane Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- -1 nitrogen Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 반도체기판의 상부에 소자분리막을 형성하기 위한 감광막패턴을 형성하고, 상기 감광막패턴의 측벽에 제1절연막으로 스페이서를 형성하고, 상기 감광막 패턴과 스페이서를 마스크로 하여 트렌치를 형성하고, 상기 트렌치가 형성된 반도체기판의 표면에 이온주입층을 형성하고, 열산화공정으로 상기 구조의 전 표면에 제2절연막을 형성한 후, 반도체기판이 노출될 때까지 평탄하게 식각하므로써 상기 트렌치를 매립하는 소자분리막을 형성함으로써 자직정렬적으로 소자분리막을 용이하게 형성하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method of manufacturing a device isolation film of a semiconductor device, to form a photoresist pattern for forming a device isolation film on an upper surface of the semiconductor substrate, to form a spacer with a first insulating film on the sidewall of the photoresist pattern, and When a trench is formed using a spacer as a mask, an ion implantation layer is formed on a surface of the semiconductor substrate on which the trench is formed, and a second insulating film is formed on the entire surface of the structure by a thermal oxidation process, and then the semiconductor substrate is exposed. By forming a device isolation film to fill the trench by etching to a flat until it is a technique to easily form a device isolation film in a self-aligned and thereby high integration of the semiconductor device.
Description
제1a도 내지 제1e도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조 공정을 도시한 단면도.1A to 1E are cross-sectional views illustrating a device isolation film manufacturing process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 감광막패턴1 semiconductor substrate 2 photosensitive film pattern
3 : 저온산화막 4 : 스페이서3: low temperature oxide film 4: spacer
5 : 트렌치 6 : 산화막5: trench 6: oxide film
7 : 필드산화막7: field oxide film
본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 특히 반도체기판의 상부에 스페이서를 형성하고, 상기 스페이서를 마스크로 반도체기판의 일정깊이를 식각하여 트렌치를 형성하고, 상기 트렌치가 형성된 반동체기판의 표면에 이온주입층을 형성하여 산화막 성장속도의 차이를 이용하여 필드산화막을 형성하므로써, 단순한 공정으로 반도체소자의 신뢰성을 향상할 수 있는 반도체소자의 소자분리막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, and in particular, forming a spacer on an upper portion of a semiconductor substrate, forming a trench by etching a predetermined depth of the semiconductor substrate using the spacer as a mask, and forming a semicoil substrate having the trench The present invention relates to a method for fabricating a device isolation film for a semiconductor device, by forming an ion implantation layer on the surface of the film and forming a field oxide film using a difference in oxide film growth rate, thereby improving the reliability of the semiconductor device in a simple process.
일반적으로, 반도체소자는 트랜지스터나 캐패시터등과 같은 소자들이 형성되는 활성영역과, 상기 소자들의 동작을 서로 방해하지 않도록 활성영역들을 분리하는 소자분리영역으로 구성되어 있다.In general, a semiconductor device is composed of an active region where elements such as a transistor or a capacitor are formed, and an element isolation region that separates the active regions so as not to interfere with each other.
최근, 반도체소자의 고집적화 추세에 따라 반도체소자에서 많은 면적을 차지하는 소자분리영역의 면적을 감소시키려는 노력이 꾸준히 진행되고 있다.Recently, in accordance with the trend of high integration of semiconductor devices, efforts have been made to reduce the area of device isolation regions, which occupy a large area in semiconductor devices.
이러한 소자분리영역의 제조방법으로는 질화막패턴을 마스크로 하여 실리콘 반도체기판을 열산화시키는 통상의 로코스(Local Oxidation of Silicon, LOCOS)방법이나, 반도체기판상에 적층된 별도의 폴리실리콘층을 열산화시키는 세폭스(SEFOX) 방법 또는 반도체기판에 트렌치를 형성하고 이를 절연물질로 메우는 트렌치(trench) 분리등의 방법이 사용되고 있다.As a method of manufacturing the device isolation region, a conventional local oxide of silicon (LOCOS) method of thermally oxidizing a silicon semiconductor substrate using a nitride film pattern as a mask, or a separate polysilicon layer laminated on a semiconductor substrate is opened. A SEFOX method for oxidizing or trench isolation for forming a trench in a semiconductor substrate and filling it with an insulating material is used.
그리고, PBL(Poly Buffered LOCOS)공정은 LOCOS 공정의 응용 기술로 질회막과 패드산화막의 사이에 폴리실리콘층을 형성하므로써, 소자분리막의 버즈빅(bird’s beak)을 감소하며, 반도체기판의 스트레스를 완화한다.The PBL (Poly Buffered LOCOS) process is an application technology of the LOCOS process to form a polysilicon layer between the film and the pad oxide film, thereby reducing the bird's beak of the device isolation film and relieving stress of the semiconductor substrate. do.
그러나, 상기와 같은 종래의 소자분리막 제조방법은 반도체기판의 상부에 산화막, 질화막 또는 폴리실리콘등을 증착하는 공정이 포함되어 공정이 복잡하다.However, the conventional method of manufacturing a device isolation film as described above includes a process of depositing an oxide film, a nitride film, or polysilicon on an upper surface of a semiconductor substrate.
그리고, 상기한 종래의 기술들은 기본적으로 소자분리영역을 산화시켜 형성하는 측면에서 크게 LOCOS로 볼 수 있으며, 반도체소자가 고집적화될수록 사용이 곤란한 단점이 있다.In addition, the conventional techniques described above can be regarded as LOCOS largely in terms of forming the isolation region by oxidizing, and it is difficult to use the semiconductor device as it is highly integrated.
그리고, 소자분리영역의 폭이 좁아질수록 실리콘 밑으로 들어간 산화막의 깊이가 얕아지게 되고 이경우 충분한 소자분리특성을 확보하기 힘들기 때문에 소자분리영역을 미리 건식식각하여 트렌치를 형성한 상태에서 화학기상증착(Chemical Vapor Deposition, 이하에서 CVD라 함.) 방법으로 산화막 증착하여 트렌치를 매립하였다.As the width of the device isolation region becomes narrower, the depth of the oxide film under the silicon becomes shallower, and in this case, since it is difficult to secure sufficient device isolation characteristics, the chemical vapor deposition is performed by dry etching the device isolation region in advance. (Chemical Vapor Deposition, hereafter referred to as CVD) by depositing the oxide film by the method to fill the trench.
그러나, 상기 트렌치를 형성하기 위한 식각공정과, 트렌치를 매립하는 절연막 증착공정과, 상기 절연막을 평탄화식각하는 공정을 포함하여 공정이 복잡하여 반도체소자의 특성을 열화시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.However, the process is complicated, including an etching process for forming the trench, an insulation film deposition process for filling the trench, and a planarization etching process for the insulation film, thereby deteriorating the characteristics of the semiconductor device and consequently making it difficult to achieve high integration of the semiconductor device. There is a problem.
따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 자기정렬적인 식각공정으로 트렌치를 형성하고 후속공정으로 트렌치를 매립하는 소자 분리막을 형성하는 반도체소자의 소자분리막 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a device isolation film of a semiconductor device in which a trench is formed by a self-aligned etching process and a device isolation film is embedded in a subsequent process in order to solve the problems of the prior art. There is this.
상기 목적을 달성하기 위해 본 발명에 따른 반도에소자의 소자분리막 제조방법은, 반도체기판 상부에 소자분리마스크를 이용하여 감광막패턴을 형성하는 공정과, 상기 감광막패턴 측벽에 제1절연막으로 스페이서를 형성하는 공정과, 상기 감광막패턴과 스페이서를 마스크로하는 자기정렬적인 식각공정으로 상기 반도체기판을 식각함으로써 트렌치를 형성하는 공정과, 상기 감광막패턴과 스페이서를 마스크로하여 상기 트렌치 표면에 불순물 이온을 주입하여 이온주입층을 형성하는 공정과, 상기 감광막패턴과 스페이서를 제거하고 상기 반도체기판을 열산화시켜 트렌치를 포함한 전체표면상부에 제2절연막을 형성하는 공정과, 상기 제2절연막을 전면식각하여 상기 트렌치를 매립하는 소자분리막을 형성하는 공정을 포함하는 것을 특징으로한다.In order to achieve the above object, a method of fabricating an isolation layer of a device in a peninsula according to the present invention includes forming a photoresist pattern on an upper surface of a semiconductor substrate using an isolation mask, and forming a spacer on the sidewall of the photoresist pattern as a first insulating layer. Forming a trench by etching the semiconductor substrate by a self-aligned etching process using the photoresist pattern and the spacer as a mask, and implanting impurity ions into the trench surface using the photoresist pattern and the spacer as a mask Forming an ion implantation layer, removing the photoresist pattern and the spacer, and thermally oxidizing the semiconductor substrate to form a second insulating film over the entire surface including the trench; and etching the second insulating film in front of the trench. And forming a device isolation film to fill the gap.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다. 제1a도 내지 제1e도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조방법을 도시한 단면도이다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. 1A to 1E are cross-sectional views illustrating a method of manufacturing a device isolation film of a semiconductor device according to an embodiment of the present invention.
제1a도를 참조하면, 반도체기판(1) 상부에 소자분리영역(B)을 형성하기 위한 감광막패턴(2)을 형성한다. 이때, 상기 감광막패턴(2)은 소자분리마스크를 이용한 노광 및 현상 공정으로 형성한다.Referring to FIG. 1A, a photosensitive film pattern 2 for forming the device isolation region B is formed on the semiconductor substrate 1. In this case, the photoresist pattern 2 is formed by an exposure and development process using an element isolation mask.
그 다음, 상기 구조의 전 표면에 저온에서 500 내지 2000 Å두께의 저온산화막(3)을 증착한다. 이때, 상기 저온산화막(3)은 소자분리영역(B)이 오목한 구조로 형성된다. 그리고, 상기 소자분리영역(B)의 상부에 형성된 저온산화막(3)의 종횡비는 65내지 98%로 된다.Then, a low temperature oxide film 3 having a thickness of 500 to 2000 microns is deposited on the entire surface of the structure at low temperature. At this time, the low temperature oxide film 3 is formed in a concave structure of the device isolation region (B). The aspect ratio of the low temperature oxide film 3 formed on the device isolation region B is 65 to 98%.
제1b도를 참조하면, 상기 저온산화막(3)을 일정두께 전면식각하여 상기 감광막패턴(2)의 측벽에 저온산화막(3)으로 스페이서(4)를 형성한다.Referring to FIG. 1B, the low temperature oxide film 3 is etched by a predetermined thickness to form a spacer 4 as the low temperature oxide film 3 on the sidewall of the photoresist pattern 2.
그 다음 상기 감광막패턴(2)과 스페이서(4)를 마스크로 하여 상기 반도체기판(1)을 200내지 1000Å 깊이로 식각하는 자기정렬적인 식각공정으로 트렌치(5)를 형성한다.Next, the trench 5 is formed by a self-aligned etching process in which the semiconductor substrate 1 is etched to a depth of 200 to 1000 하여 using the photoresist pattern 2 and the spacer 4 as a mask.
참고로, 반도체기판(1)의 일정깊이를 식각하면, 이후에 형성될 필드산화막이 반도체기판 아래쪽으로 더 깊이 들어가 형성되므로 전기적으로 소자분리 역할을 높일 수 있으며, 소자분리공정이 끝난 후 평탄화 특성도 양호해진다.For reference, if the predetermined depth of the semiconductor substrate 1 is etched, a field oxide film to be formed later is formed deeper into the lower side of the semiconductor substrate, thereby increasing the role of device isolation. It becomes good.
그 다음 상기 전체 구조의 상부에서 1 × 1013/㎠ 내지 1 × 1013/㎠정도의 고농도 이온, 예를 들어 붕소, 인, 비소, 질소 등의 불순물 이온을 주입하여 상기 감광막패턴(2)과 스페이서(4)의 상부면과, 노출된 반도체기판(1)의 표면, 즉 트렌치(5) 표면에 이온주입층(A)을 형성한다.That to the next 1 × 10 13 / ㎠ on top of the entire structure 1 × 10 13 / ㎠ amount of high-concentration ions, such as boron, phosphorus, arsenic, by implanting impurity ions such as nitrogen, the photosensitive film pattern (2) and An ion implantation layer A is formed on the upper surface of the spacer 4 and the surface of the exposed semiconductor substrate 1, that is, the surface of the trench 5.
제1c도를 참조하면 상기 감광막패턴(2)과 스페이서(4)를 제거하여 트렌치(5)가 형성된 반도체기판(1)을 형성한다.Referring to FIG. 1C, the photosensitive film pattern 2 and the spacer 4 are removed to form the semiconductor substrate 1 having the trench 5 formed therein.
제1d도를 참조하면, 상기 반도체기판(1)을 열산화하여 상기 트렌치(5)를 포함하는 전체구조상부에 산화막(6)을 형성한다.Referring to FIG. 1D, the semiconductor substrate 1 is thermally oxidized to form an oxide film 6 over the entire structure including the trench 5.
이때, 상기 트렌치(5)가 형성된 영역은 하부의 이온주입층(A)에 의하여 산화반응이 활발히 일어나 산화막(6)이 상기 반도체기판(1)의 아래쪽 으로 더 깊게 형성된다.At this time, in the region where the trench 5 is formed, the oxidation reaction is actively performed by the ion implantation layer A at the bottom, so that the oxide film 6 is formed deeper below the semiconductor substrate 1.
여기서, 이온주입이 형성된 영역과 그렇지 않은 영역의 산화속도비는 3 : 1 내지 12 : 1 이다.Here, the oxidation rate ratio between the region where ion implantation is formed and the region where the ion implantation is not formed is 3: 1 to 12: 1.
제1e도를 참조하면, 상기 산화막(6)을 반도체기판(1)이 노출될 때까지 식각하여 평탄화하므로써 소자분리막, 즉 필스산화막(7)을 형성한다.Referring to FIG. 1E, the oxide isolation layer 6 is etched and planarized until the semiconductor substrate 1 is exposed to form an isolation layer, that is, a fill oxide layer 7.
이때, 상기 필스산화막(7)은 버즈빅이 생기지 않는 이점이 있다.At this time, the pillar oxide film 7 has an advantage that the buzz big does not occur.
또, 256 M DRAM 이상의 고집적 반도체소자에 적합하다.It is also suitable for highly integrated semiconductor devices of 256 M DRAM or more.
상술한 바와 같이 본 발명의 반도체소자의 소자분리막 제조방법은, 저온산화막으로 스페이서를 형성하고, 상기 스페이서를 마스크로 반도체기판의 일정깊이를 식각하는 자기정렬적인 방법으로 트렌치를 형성하고, 상기 트렌치가 형성된 반도체기판의 표면에 이온주입층을 형성한 다음, 산화막 성장속도의 차이를 이용하여 좁은 면적의 필드산화막을 형성하므로써, 버즈빅이 형성되지 않아 소자의 신뢰성을 향상하는 이점이 있으며, 256 M DRAM이상의 고집적 반도체소자에 적합한 이점이 있으며, 공정을 단순하게 하는 이점이 있다.As described above, in the method of manufacturing a device isolation film of the semiconductor device of the present invention, a trench is formed by a self-aligned method of forming a spacer using a low temperature oxide film, and etching a predetermined depth of the semiconductor substrate using the spacer as a mask. By forming an ion implantation layer on the surface of the formed semiconductor substrate, and then forming a field oxide film having a small area by using the difference in oxide film growth rate, there is an advantage in that the reliability of the device is improved due to the absence of buzz big, 256 M DRAM There is an advantage suitable for the above highly integrated semiconductor device, there is an advantage to simplify the process.
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