KR100197774B1 - Solid-state imaging device - Google Patents

Abstract

The present invention is an interline transfer type or a frame interline transfer type, and has a transfer electrode extending on a drain region for connection with a bus line wiring in a solid-state image pickup device having a drain region for removing unnecessary charge along a horizontal charge transfer portion. By setting the pattern as a pattern which avoids the connection fancy in the drain region, the area on the chip is not increased and the overflow is surely prevented.

Description

Solid-state imaging device

1 is a plan view of principal parts of an example of a solid-state imaging device of the present invention.

2 is a schematic plan view of one example of the solid-state imaging device.

* Explanation of symbols for main parts of the drawings

1 drain region 2 gate electrode

3: aluminum wiring layer 4: connection hole

5,6 polysilicon layer 10: imaging unit

11: accumulation part 12: horizontal register

13 gate area 14 bus line wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a solid-state image pickup device of an interline transfer frame or a frame interline transfer type, and more particularly to a CCD solid-state image pickup device having a drain region for removing unnecessary charge along a horizontal charge transfer portion.

The present invention is an interline transfer type or a frame interline transfer type, and has a transfer electrode extending on a drain region for connection with a bus line wiring in a solid-state image pickup device having a drain region for removing unnecessary charge along a horizontal charge transfer portion. By setting the pattern as a pattern which avoids the connection fancy in the drain region, the area on the chip is not increased and the overflow is surely prevented.

In solid-state imaging devices such as CCD imagers, smear is generated by incident light with an excessive amount of light. A technique for providing reverse drainage by providing a drain region for removing unnecessary charge on the proximal end of the vertical register of the vertical register of the conventional imaging unit as the smear removal means (for example, "Television Journal, Image Information Engineering and Broadcasting Technology", VOL 141, No. 11, and 1987) (see pages 1039 to 1046), and smear charge exposure techniques for positively transferring horizontal registers and removing unnecessary charges to precharge drains, etc., of the terminal are known.

By the way, in order to remove unnecessary charges, a technique for performing reverse transfer requires a circuit system for transferring charges in the reverse direction, and the control of the circuit is complicated. In the technique of removing smear charges by the transfer of the horizontal register, when the horizontal register overflows with the smear charges, it appears as an image defect.

Therefore, considering an element having a drain region for removing unnecessary charges adjacent to the opposite side of the image pickup portion of the horizontal register and provided along the horizontal register, the resistance of the drain region can be reduced in order to efficiently remove unnecessary charges. There is a need. In such a device, since the drain region is provided between the bus line wiring and the horizontal resistor, widening the drain region itself increases the area on the chip and increases the length of the transfer electrode of the horizontal resistor. This results in a propagation delay of the transmission clock.

Therefore, in view of the above technical problem, an object of the present invention is to provide a solid-state imaging device that efficiently removes unnecessary charges and prevents image defects caused by smear charges.

In order to achieve the above object, the solid-state imaging device of the present invention includes a plurality of light receiving units arranged in a matrix, and a plurality of vertical charge transfer units which are provided for each vertical column of the light receiving units and transfer charges in the light receiving units in the vertical direction. A horizontal charge transfer unit for transferring charges in the vertical charge transfer unit in a horizontal direction for each horizontal line by control using a plurality of transfer electrodes, and bus line wirings provided along the horizontal transfer unit for rapid forward propagation to the transfer electrode; And a drain region provided between the bus line wiring and the horizontal charge transfer portion and for removing unnecessary charges, each transfer electrode of the horizontal charge transfer portion passing through an area between a plurality of connection holes provided in the drain region. It is characterized by having a pattern connected to the bus line wiring. The vertical charge transfer unit may have a structure having a second vertical charge transfer unit for the temporary accumulation of the second vertical charge transfer unit due to the temporary accumulation such that the solid-state imaging element becomes a frame interline transfer type. Further, a gate region is provided on the side of the horizontal charge transfer section of the drain region for obtaining a reference elimination potential for unnecessary charges.

By providing a drain region between the horizontal charge transfer section and the bus line wiring, overflow due to smear charge is prevented even in the horizontal charge transfer section. By supplying power to the drain region via the plurality of connection holes, unnecessary charges with good efficiency are removed. The transfer electrodes of the horizontal charge transfer portion are connected with the bus line wiring, at which part of the transfer electrodes pass over the drain region.

Therefore, by setting the pattern of the transfer electrode to pass through the area between the plurality of connection holes, power supply to the drain area by the aluminum wiring layer or the like is possible without widening the lower drain area.

Reference is now made to preferred embodiments of the present invention.

First, a schematic overall structure of the CCD imager of this embodiment will be described with reference to FIG. The CCD imager of this embodiment is a frame interline transfer (FIT) type CCD imager formed on a silicon substrate. In the imaging section 10, a light receiving section 21 for converting incident light into signal charges in a matrix form is arranged. If the light receiving portion 21 uses an n-type silicon substrate and a p-type well region, for example, the pnpn structure has a p-type hole accumulation layer and an n-type impurity diffusion region formed on its surface. No light shielding film is formed on the light receiving portion 21. Each light receiving portion 21 is provided with a plurality of first vertical registers 22 for each vertical column. These first vertical registers 22 are registers for transferring the signal charges from the light receiving portion 21 in the vertical (V) direction, and the transfer electrodes are provided with a multi-phase transfer clock to control charges in the buried channel layer. Can be. The accumulating part 11 is provided in this imaging part 10 in the V direction. The accumulation section 11 is composed of the second vertical register 23, and is intended to reduce smear by temporarily accumulating the charge transferred at the first vertical register 22 at a high speed. This accumulator 11 is entirely shielded from light.

A horizontal register 12 is formed adjacent to the storage section 11 and along the end of each second vertical register 23.

The horizontal register 12 is a register for transferring the charge of the storage unit 11 in the horizontal direction for every horizontal line, and the horizontal register 12 is provided with a plurality of transfer electrodes as described later. The transfer clocks ΦH1 and ΦH2 are provided to the transfer electrodes of these horizontal registers 12, respectively.

On the side of the horizontal register 12 in the vertical direction, a gate region 13 is provided along the horizontal register 12. The gate region 13 is a drain region 1 described later in the horizontal register 12, which is a region for controlling the amount of unnecessary charge removal by its potential. In this gate region 13, a gate electrode serving as a polysilicon layer of the first layer as described later is formed.

Along the gate region 13, a drain region 1 for preventing the overflow of the horizontal register 12 is formed. This drain region 1 is formed of an n-type impurity diffusion region formed on the surface of the p-type well region. As described later, a plurality of connection holes for efficiently removing unnecessary charges are provided in the drain region 1, and unnecessary charges are absorbed by the wiring layers connected to these connection holes.

In another V direction of the drain region 1, bus line wirings 14 serving as aluminum-based wiring layers of a plurality of parallel patterns are provided. This bus line wiring 14 is wiring for feeding power to each part on the chip. The bus line wiring 14 includes a line for supplying power to the transfer electrode of the horizontal register 12 and further includes various wirings such as a ground voltage line and a power supply voltage line. Thus, the bus line wiring 14 is connected to a bonding pad portion (not shown), and the bonding pad portion is wire bonded to an external terminal.

At the end of the horizontal register 12, a floating diffusion region 15 is provided via an output gate 19. In this floating diffusion region 15, the amount of signal charge from the horizontal register 12 changes to a variation in potential, and is output through an output buffer 16 to which an input terminal is connected to the floating diffusion region 15. The signal is drawn out. Further, the precharge drain region 17 reaches the floating diffusion region 15 via the precharge gate 18, and the precharge is controlled under the control of the precharge gate 18 of the floating diffusion region 15. Is done.

Next, with reference to FIG. 1, the structure of the drain region 1 vicinity is demonstrated.

First, in the horizontal register 12, a transfer electrode formed by patterning the second polysilicon layer 5 and the third polysilicon layer 6 is provided, and the second polysilicon layer 5 is formed. ) And the buried channel layer 9 is formed in the region where the polysilicon layer 6 of the third layer is formed on the substrate via an insulating film. Here, each of the polysilicon layers 5 of the second layer is a band-shaped pattern extending in the V direction on the horizontal register 12, and is a pattern spaced apart by a predetermined pitch, respectively, but the drain region 1 On the gate electrode 2 formed of the polysilicon layer of the first layer between the horizontal resistor 12 and the horizontal resistor 12, bent and extended in a crank shape while maintaining the side portion 8 extending in the H direction, and again the drain region ( 1) In the above, the pattern extends straight in the V direction. This pattern is a pattern so that the polysilicon layer 5 of each 2nd layer may not overlap on the upper part of each connection hole 4 of the drain region 1, and the polysilicon layer of the 2nd layer which forms a transfer electrode (5) passes through the region between the connection holes 4 on the drain region (1). The polysilicon layer 5 of these 2nd layer is connected with the said bus line wiring 14 in the terminal part, and the transmission line phi H1 and phi H2 are alternately provided for each pattern from the bus line wiring 14. Next, the polysilicon layer 6 of each third layer is in a pattern extending in the V direction on the horizontal resistor 12 like the second polysilicon layer 5, and the H direction is the charge transfer direction of the pattern. Both ends of the portion partially overlap the polysilicon layer 5 of the second layer. Therefore, the polysilicon layer 6 of each of these third layers has a narrow line width at the portion of the side portion 7 extending in the H direction on the gate electrode 2 described above, and extends again in the V direction in the figure. do. The pattern of the polysilicon layer 6 of this 3rd layer is each 2nd in the upper part of each connection hole 4 of the drain region 1 like the pattern of the polysilicon layer 5 of the said 2nd layer. It is a pattern so that the polysilicon layer 5 of a layer may not overlap. The pattern of the polysilicon layer 6 of the third layer passes through the region between the connection holes 4 on the drain region 1 while overlapping the pattern of the polysilicon layer 5 of the second layer. Therefore, the polysilicon layer 6 of these 3rd layer is connected with the said bus line wiring 14 in the terminal part, and the transmission line phi H1 and phi H2 are alternately given to each pattern from the bus line wiring 14 at this end part. .

Next, the gate electrode 2 is formed on the substrate film in the gate region 13. The level at which smear charges are removed is determined by a predetermined potential applied to the gate electrode 2. Therefore, the substrate surface under the gate electrode 2 becomes a channel region of smear charge, and the overflowed charge is removed through the channel region. On this gate electrode 2, the polysilicon layer 5 of the second layer and the polysilicon layer 6 of the third layer are each bent or narrow so as to avoid the connection hole 4, Since the side parts 7 and 8 are not made into the same position of the V direction, the filling and the like can be alleviated.

As described above, the drain region 1 is an n-type impurity diffusion region in which p wells for preventing the overflow of the horizontal register 12 are formed, and smear charges, which are unnecessary charges, are removed. In this drain region 1, connection holes 4 are provided in a plurality of places in order to remove the electric charge with good efficiency. The connection hole 4 is a hole in which an interlayer insulating film for electrically connecting the aluminum-based wiring layer 3 extending in the H direction in the longitudinal direction and the drain region 1 is provided on the drain region 1. The aluminum wiring layer 3 is provided in a pattern parallel to the above-described gate electrode 2, and a predetermined voltage for supplying power to the drain region 1 is supplied. In the CCD imager of the present embodiment, at each of the connection holes 4, the polysilicon layer 5 of the second layer and the polysilicon layer 6 of the third layer avoid the connection holes 4, respectively. Since the wires are bent or narrow so as to pass through the region between the connection holes 4, the aluminum-based wiring layer 3 is reliably connected to the drain region 1. The aluminum wiring layer 3 is formed using the same layer as the bus line wiring 14, for example. In addition, in the present embodiment, one connection hole 4 is provided to correspond to each of the polysilicon layer 5 of the second layer and the polysilicon layer 6 of the third layer, that is, for each bit. It is not limited.

In the CCD imager of this embodiment having such a structure, the polysilicon layer 5 of the second layer and the polysilicon layer 6 of the third layer, which are transfer electrodes of the horizontal register 12, are connected to the drain region 1. It passes through the area | region between each connection hole 4, and has a pattern connected to the bus line wiring 14. As shown in FIG. For this purpose, the smear charge can be effectively removed without widening the width of the drain region 1 in the V direction. In addition, since the width of the drain region 1 in the V direction does not become wider, the distance between the bus line wiring 14 and the horizontal register 12 is also shortened to prevent the propagation delay of the transfer clock supplied to the transfer electrode. Can be.

In the above-described embodiment, the transmission type is FIT type, but may be an IT (interline transmission) type.

In the solid-state imaging device of the present invention, since the pattern of each transfer electrode of the horizontal charge transfer portion is a pattern passing through the region between the plurality of connection holes, on the drain region provided between the bus line wiring and the horizontal charge transfer portion, the drain is drained. The power is surely supplied to the area, which does not increase the area on a chip or cause a propagation delay of a transmission clock, and can efficiently remove unnecessary charges.

Claims (1)

A plurality of light-receiving units arranged in a matrix, a plurality of vertical charge transfer units provided for each vertical column of the light-receiving units for transferring charges from the light-receiving unit in a vertical direction, and a plurality of transfers of charges from these vertical charge transfer units A horizontal charge transfer unit for transferring in the horizontal direction for each horizontal line by control using an electrode, a bus line wiring provided in accordance with the horizontal charge transfer unit and feeding the transfer electrode, the bus line wiring and the horizontal charge And a drain region provided between the transfer units to remove unnecessary charges, and each transfer electrode of the horizontal charge transfer unit has a pattern connected to the bus line wiring through a region between a plurality of connection holes provided in the drain region. It has a solid-state imaging element characterized by the above-mentioned.

Images