KR100197129B1 - Forming method for metal wiring in semiconductor device - Google Patents
Forming method for metal wiring in semiconductor device Download PDFInfo
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- KR100197129B1 KR100197129B1 KR1019950069607A KR19950069607A KR100197129B1 KR 100197129 B1 KR100197129 B1 KR 100197129B1 KR 1019950069607 A KR1019950069607 A KR 1019950069607A KR 19950069607 A KR19950069607 A KR 19950069607A KR 100197129 B1 KR100197129 B1 KR 100197129B1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 37
- 239000002184 metal Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000000206 photolithography Methods 0.000 claims abstract description 14
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 8
- 239000010937 tungsten Substances 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000010936 titanium Substances 0.000 claims abstract description 4
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- BLOIXGFLXPCOGW-UHFFFAOYSA-N [Ti].[Sn] Chemical compound [Ti].[Sn] BLOIXGFLXPCOGW-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속배선 형성방법을 개시한다. 개시된 본 발명은 반도체 기판상에 소정의 고농도 불순물 이온주입 영역이 형성된 상태의 전체 구조 상부에 제1절연막을 형성하는 단계; 상기 제1절연막을 상기 고농도 불순물 이온주입 영역이 노출되도록 사진식각법으로 선택적으로 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀의 내부 및 주변부 전면에 금속 장벽막, 알루미늄 합금막, 및 비반사용 티타늄막을 순차적으로 형성한 후, BCl3또는 Cl2가스에 의한 사진식각법으로 소정의 금속배선을 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성방법에 있어서, 상기의 금속배선을 형성하는 단계 바로 이후에, 상기 노출된 금속배선의 표면에 WF6가스에 의해 텅스텐막을 선택적으로 형성하는 단계; 전체 구조 상부에 소정 두께의 제2절연막을 증착하는 단계; 및 상기 제2절연막의 소정 부분을 상기 알루미늄 합금막이 노출되도록 사진식각법으로 식각하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a method for forming metal wiring of a semiconductor device. The disclosed invention comprises the steps of: forming a first insulating film over the entire structure in a state where a predetermined high concentration impurity ion implantation region is formed on a semiconductor substrate; Forming a contact hole by selectively etching the first insulating layer using a photolithography method to expose the high concentration impurity ion implantation region; And sequentially forming a metal barrier film, an aluminum alloy film, and a non-reflective titanium film on the inside and the periphery of the contact hole, and then forming a predetermined metal wiring by photolithography using BCl 3 or Cl 2 gas. A method of forming metal wirings in a semiconductor device, the method comprising: selectively forming a tungsten film on the surface of the exposed metal wirings by WF 6 gas immediately after the forming of the metal wirings; Depositing a second insulating film having a predetermined thickness on the entire structure; And etching a predetermined portion of the second insulating layer by photolithography so that the aluminum alloy layer is exposed.
Description
제1도는 종래 기술에 따른 금속배선 형성방법을 설명하기 위한 도면1 is a view for explaining a metal wiring forming method according to the prior art.
제2도는 (a) 내지 (c)는 본 발명의 일실시예에 따른 금속배선 형성방법을 공정 순서적으로 설명하기 위한 도면2 is a view for explaining the process of forming a metal wiring in accordance with an embodiment of the present invention (a) to (c)
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,11 : 반도체 기판 2,12 : 고농도 이온주입 영역1,11 semiconductor substrate 2,12 high concentration ion implantation region
3,13 : 제1절연막 4,14 : 금속 장벽막3,13: first insulating film 4,14: metal barrier film
5,15 : 알루미늄 합금막 6,16 : 비반사용 티타튬막5,15: aluminum alloy film 6,16: non-reflective titanium oxide film
7 : 산화물 17 : 텅스텐막7: oxide 17: tungsten film
18 : 제2절연막18: second insulating film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.
오늘날, 반도체 소자의 제조에서 소자와 소자간의 연결을 위해 금속배선을 형성하는 것이 잘 알려져 있다.Today, it is well known to form metallization for connection between devices in the manufacture of semiconductor devices.
이와 같은 금속배선의 형성을 위한 종래의 방법이 첨부도면 제1도에 도시되어 있다. 종래의 방법은 제1도에서 도시된 바와 같이, 반도체 기판(1)상에 소정의 고농도 불순물 이온주입 영역(2)이 형성된 상태에서, 소정 두께의 제1절연막(3)을 적층하고, 사진식각법으로 콘택홀(미도시)을 형성한 다음, 콘택홀의 내부 및 주변부 전면에 소정의 금속 장벽막(4), 알루미늄 합금막(5), 및 비반사용 티타튬(TiN)막(6)을 순차적으로 형성한다. 그리고 나서, 제1절연막(3)의 소정부분이 노출되도록 BCl3또는 Cl2가스를 사용하는 사진식각법에 의해서 소정의 금속배선 패턴을 형성한다. 그리고 상기 금속배선의 상부에 제2절연막(미도시)을 형성하게 된다.A conventional method for the formation of such metallization is shown in FIG. 1 of the accompanying drawings. In the conventional method, as shown in FIG. 1, a first insulating film 3 having a predetermined thickness is laminated on a semiconductor substrate 1 in a state where a predetermined high concentration impurity ion implantation region 2 is formed, and photolithography is performed. After forming a contact hole (not shown) by the method, a predetermined metal barrier film 4, an aluminum alloy film 5, and a non-reflective titanium (TiN) film 6 are sequentially disposed on the entire inner and peripheral portions of the contact hole. To form. Then, a predetermined metallization pattern is formed by a photolithography method using BCl 3 or Cl 2 gas so that a predetermined portion of the first insulating film 3 is exposed. A second insulating film (not shown) is formed on the metal wiring.
그러나 금속배선의 형성을 위한 사진식각시 사용되는 BCl3또는 Cl2가스의 Cl 성분으로 인해 상기 알루미늄 합금막(5)의 노출부위에 부식현상이 발생하여 산화물(7)이 생성된다. 이러한 산화물(7)은 알루미늄 합금막의 신뢰성에 치명적인 악영향을 미치는 문제점을 수반한다.However, due to the Cl component of the BCl 3 or Cl 2 gas used in the photolithography for forming the metal wiring, the corrosion phenomenon occurs in the exposed portion of the aluminum alloy film 5 to generate the oxide 7. This oxide 7 is accompanied with a problem that has a fatal adverse effect on the reliability of the aluminum alloy film.
따라서, 상기의 문제점을 해결하기 위하여 안출된 본 발명은, 알루미늄 합금막의 노출부위에서 부식이 발생하는 것을 방지하여 소자의 신뢰도를 향상시킬 수 있는 반도체 소자의 금속배선 형성방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can improve the reliability of the device by preventing corrosion from occurring in the exposed portion of the aluminum alloy film. .
상기의 목적을 달성하기 위하여 본 발명은, 반도체 기판상에 소정의 고농도 불순물 이온주입 영역이 형성된 상태의 전체 구조 상부에 제1절연막을 형성하는 단계;In order to achieve the above object, the present invention comprises the steps of: forming a first insulating film on the entire structure in a state where a predetermined high concentration impurity ion implantation region is formed on a semiconductor substrate;
상기 제1절연막을 상기 고농도 불순물 이온주입 영역이 노출되도록 사진식각법으로 선택적으로 식각하여 콘택홀을 형성하는 단계;Forming a contact hole by selectively etching the first insulating layer using a photolithography method to expose the high concentration impurity ion implantation region;
상기 콘택홀의 내부 및 주변부 전면에 금속 장벽막, 알루미늄 합금막, 및 비반사용 티타늄막을 순차적으로 형성한 후, BCl3또는 Cl2가스에 의한 사진식각법으로 소정의 금속배선을 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성방법에 있어서,And sequentially forming a metal barrier film, an aluminum alloy film, and a non-reflective titanium film on the inside and the periphery of the contact hole, and then forming a predetermined metal wiring by photolithography using BCl 3 or Cl 2 gas. In the metal wiring formation method of a semiconductor element,
상기의 금속배선을 형성하는 단계 바로 이후에, 상기 노출된 금속배선의 표면에 WF6가스에 의해 텅스텐막을 선택적으로 형성하는 단계;Selectively forming a tungsten film on the surface of the exposed metal wiring by the WF 6 gas immediately after the forming of the metal wiring;
전체 구조 상부에 소정 두께의 제2절연막을 증착하는 단계; 및Depositing a second insulating film having a predetermined thickness on the entire structure; And
상기 제2절연막의 소정 부분을 상기 알루미늄 합금막이 노출되도록 사진식각법으로 식각하는 단계를 포함하는 것을 특징으로 한다.And etching a predetermined portion of the second insulating layer by photolithography to expose the aluminum alloy layer.
상기 금속배선의 표면에 형성되는 텅스텐막은 500 내지 2,000Å의 두께를 갖는 것이 바람직하다.It is preferable that the tungsten film formed on the surface of the metal wiring has a thickness of 500 to 2,000 kPa.
이하, 본 발명의 일실시예를 첨부도면에 의거하여 상세히 설명하기로 한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제2도의 (a) 내지 (c)는 본 발명의 일실시예에 따른 금속배선 형성방법을 공정 순서적으로 설명하기 위한 도면이다.(A) to (c) of FIG. 2 are diagrams for explaining a process of forming a metal wiring according to an embodiment of the present invention.
우선, 제2도의 (a)에서 도시된 바와 같이, 반도체 기판(11)상에 소정의 고농도 불순물 이온주입 영역(12)이 형성된 상태에서, 전체 구조 상부에 제1절연막(13)을 적층하고, 고농도 불순물 이온주입 영역(12)이 노출되도록 사진식각법으로 선택적으로 식각하여 콘택홀(미도시)을 형성한다. 그런 다음, 콘택홀의 내부 및 주변부 전면에 금속 장벽막(14)을 적층한 후, 이것의 상부에 알루미늄 합금막(15) 및 비반사용 티타늄막(16)을 순차적으로 적층한다. 이어서 BCl3또는 Cl2가스에 의한 사진식각법으로 식각을 실시하여 도시된 바와 같이 소정의 금속배선을 형성한다.First, as shown in FIG. 2A, in the state where a predetermined high concentration impurity ion implantation region 12 is formed on the semiconductor substrate 11, the first insulating film 13 is laminated on the entire structure, A contact hole (not shown) is formed by selectively etching the photoconductive etching method so that the high concentration impurity ion implantation region 12 is exposed. Then, after the metal barrier film 14 is laminated on the inside of the contact hole and the entire periphery, the aluminum alloy film 15 and the non-reflective titanium film 16 are sequentially stacked on the top. Subsequently, etching is performed by photolithography with BCl 3 or Cl 2 gas to form a predetermined metal wiring as shown.
그리고 나서, 상기의 금속배선을 형성 바로 이후에, (b)에서 도시된 바와 같이 금속배선(15,16)의 노출부위에 WF6가스에 의해 텅스텐막(17)을 500 내지 2,000Å의 두께로 형성한다. 이때 사용되는 WF6가스의 F는 금속배선 형성을 위해 사용된 BCl3또는 Cl2의 미반응가스인 Cl와 치환반응을 금속배서의 표면에서 일으켜서 Cl로 인한 부식현상의 발생을 억제시킨다.Then, immediately after the formation of the metal wiring, as shown in (b), the tungsten film 17 is formed to a thickness of 500 to 2,000 kW by the WF 6 gas on the exposed portions of the metal wirings 15 and 16. Form. At this time, the F of the WF 6 gas used causes the substitution reaction with Cl, which is an unreacted gas of BCl 3 or Cl 2 used to form a metal interconnection, to suppress the occurrence of corrosion caused by Cl.
그런 다음, (c)에서 도시된 바와 같이, 전체 구조 상부에 제2절연막(18)을 증착한 다음, 알루미늄 합금막(15)의 소정부분이 노출되도록 사진식각법으로 식각을 실시한다.Then, as shown in (c), the second insulating film 18 is deposited on the entire structure, and then etching is performed by a photolithography method so that a predetermined portion of the aluminum alloy film 15 is exposed.
이상에서와 같이 본 실시예에 의하면, 금속배선의 형성 후, 금속배선의 노출부위에 WF6로서 텅스텐막을 형성하고, 이때 사용되는 WF6중의 F가 미반응가스인 Cl와 금속배선의 표면에서 치환반응을 일으키므로써 금속배선의 노출부위에서 Cl로 인한 부식현상의 발생을 억제할 수 있다.According to this embodiment, as in the above, substituted at the surface after the formation of the metal interconnection, forming a film of tungsten, and a WF 6 to the exposed portion of the metal wiring wherein WF 6 F is Cl with a metal non-reacted gas in the wiring which is used By causing the reaction, it is possible to suppress the occurrence of corrosion caused by Cl in the exposed part of the metal wiring.
또한, 본 발명은 상기의 실시예에 한정되는 것은 아니며, 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention is not limited to said Example, It can variously change and implement in the range which does not deviate from the summary.
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| KR1019950069607A KR100197129B1 (en) | 1995-12-30 | 1995-12-30 | Forming method for metal wiring in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950069607A KR100197129B1 (en) | 1995-12-30 | 1995-12-30 | Forming method for metal wiring in semiconductor device |
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