KR100192176B1 - LCD - Google Patents
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- KR100192176B1 KR100192176B1 KR1019950055593A KR19950055593A KR100192176B1 KR 100192176 B1 KR100192176 B1 KR 100192176B1 KR 1019950055593 A KR1019950055593 A KR 1019950055593A KR 19950055593 A KR19950055593 A KR 19950055593A KR 100192176 B1 KR100192176 B1 KR 100192176B1
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- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims description 22
- 239000011159 matrix material Substances 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- 230000008878 coupling Effects 0.000 abstract description 3
- 238000010168 coupling process Methods 0.000 abstract description 3
- 238000005859 coupling reaction Methods 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 230000002542 deteriorative effect Effects 0.000 abstract description 2
- 230000000903 blocking effect Effects 0.000 abstract 2
- 239000011347 resin Substances 0.000 abstract 2
- 229920005989 resin Polymers 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 디스플레이의 화질 저해 요인이 되고 있는 용량 커플링을 방지할 수 있는 액정표시소자를 제공하는 것을 목적으로 한다. 이와 같은 목적을 달성하기 위한 본 발명의 액정표시소자는 하부 유리기판(21) 위에 형성된 절연막(22), 절연막(22) 상에 분리되어 형성된 화소전극(23), 화소전극(23)에 영상 데이터 신호를 공급하는 데이터 라인(24)을 포함하는 하부 패널(20)과, 상부 유리기판(11) 위에 분리되어 형성된 컬러 필터(12), 컬러필터(12) 사이에 형성되어 외부광을 차단하고, 상기 하부 패널의 데이터 라인과 대향하는 위치에 형성된 광차단 수지막(13), 광차단 수지막(13)을 제외한 부분에 형성된 공통전극(14)을 포함하는 상부 패널(10)과, 상 하부 패널(10, 20) 사이에 채워지는 액정(30)을 포함하여 구성한 것을 특징으로 한다.An object of the present invention is to provide a liquid crystal display device capable of preventing capacitive coupling, which is a factor of deteriorating image quality of a display. In order to achieve the above object, the liquid crystal display device according to the present invention includes the insulating film 22 formed on the lower glass substrate 21, the pixel electrode 23 and the pixel electrode 23 formed on the insulating film 22. It is formed between the color filter 12 and the color filter 12 formed separately from the lower panel 20 including the data line 24 for supplying a signal, the upper glass substrate 11, and blocks external light, An upper panel 10 including a light blocking resin film 13 formed at a position facing the data line of the lower panel, a common electrode 14 formed at a portion other than the light blocking resin film 13, and an upper lower panel; It is characterized by including the liquid crystal 30 to be filled between (10, 20).
Description
제1도는 종래의 실시예에 따른 액정표시소자의 부분 회로구성도로서, (a)는 단위 화소의 등가회로도이고 (b)는 박막 트랜지스터의 연결 구성도이다.1 is a partial circuit diagram of a liquid crystal display device according to a conventional embodiment, in which (a) is an equivalent circuit diagram of a unit pixel and (b) is a connection diagram of a thin film transistor.
제2도는 소오스, 드레인 전극의 게이트 전극에서의 접촉면적에 따른 스티칭 문제의 발생을 설명하기 위한 도면.2 is a view for explaining the occurrence of a stitching problem depending on the contact area of the gate electrode of the source and drain electrodes.
제3도는 본 발명의 실시예에 따른 링형 박막 트랜지스터를 구비한 액정표시소자의 부분 평면도.3 is a partial plan view of a liquid crystal display device having a ring-shaped thin film transistor according to an embodiment of the present invention.
제4도는 제3도의 A-A'선을 따라 절단된 단면도.4 is a cross-sectional view taken along the line AA ′ of FIG. 3.
제5도는 본 발명의 실시예에 따른 링형 박막 트랜지스터에서 노광시의 미스얼라인이 발생한 경우의 구성도.5 is a configuration diagram when a misalignment occurs during exposure in a ring-shaped thin film transistor according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 데이터 라인 2 : 소오스 전극1: data line 2: source electrode
3 : 절연층 4 : 게이트 라인3: insulation layer 4: gate line
5 : 게이트 전극 6 : 투명전극5 gate electrode 6 transparent electrode
7 : 드레인 전극 8 : 비정질 실리콘7: drain electrode 8: amorphous silicon
9 : 유리기판 10 : 패시베이션9: glass substrate 10: passivation
본 발명은 박막 트랜지스터 액정표시소자에 관한 것으로서, 특히 링형상의 박막 트랜지스터를 구비한 액정표시소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistor liquid crystal display devices, and more particularly to a liquid crystal display device having a ring-shaped thin film transistor.
액정표시장치의 제조에 있어서 표시장치의 화면 사이즈는 노광 마스크보다 일반적으로 크다. 그러므로, 노광시에는 표시장치의 화면을 여러 쇼트(Shot)로 분할하여 반복하여 노광하고 있다. 그러나 노광장비의 정밀도에 한계가 있어서 쇼트간의 미스얼라인이 발생하여 스티치(Stitch) 불량이라는 액정표시장치의 화질을 떨어 뜨리는 문제점을 야기시키고 있다.In the manufacture of liquid crystal display devices, the screen size of the display device is generally larger than that of the exposure mask. Therefore, during exposure, the screen of the display device is divided into several shots and repeatedly exposed. However, there is a limit in the precision of the exposure equipment, causing misalignment between shots, causing a problem of deteriorating the image quality of the liquid crystal display device, such as a poor stitch.
첨부한 도면 제1도는 종래의 기술에 따른 박막 트랜지스터의 채널구조를 도시한 것으로서, 게이트(G), 소오스(S) 및 드레인(D)으로 구성되는 스위칭 소자인 박막 트랜지스터(이하, TFT로 약칭), 상하판전극 사이의 액정의 존재로 인해 형성되는 게이트와 드레인간의 캐패시터(Cgd), 액정 캐패시터(CL) 및 보조 캐패시터(CS), 게이트 라인(11) 및 데이터 신호라인(12)이 도시되었다.1 is a diagram illustrating a channel structure of a thin film transistor according to the related art, and is a thin film transistor (hereinafter, abbreviated as TFT) that is a switching element including a gate (G), a source (S), and a drain (D). The capacitor C gd between the gate and the drain, the liquid crystal capacitor C L and the auxiliary capacitor C S , the gate line 11, and the data signal line 12 are formed due to the presence of the liquid crystal between the upper and lower plate electrodes. Has been shown.
먼저, 충전(charging) 과정을 살펴보면, 게이트에 신호전압이 인가되면 TFT가 턴-온 상태가 되며, 이 시간동안에 화상에 관한 정보를 가진 데이터 전압이 TFT를 통과하여 액정에 인가되는데, 이 때 캐패시터인 액정을 충전시키기 위해 필요한 전류는 하기의 식에 의해 표현될 수 있다.First, in the charging process, when a signal voltage is applied to a gate, the TFT is turned on, and during this time, a data voltage having information about an image passes through the TFT and is applied to the liquid crystal. The current required to charge the phosphorus liquid crystal can be expressed by the following equation.
이상적인 경우 충전된 총전하량은 게이트가 턴-오프되어 다음 신호가 들어올 때까지 유지가 되나, 실제의 경우는 비정질 실리콘 채널층의 저항(Roff)으로 인해 누설전류(leakage current)가 존재한다.In the ideal case, the total charged charge is maintained until the gate is turned off until the next signal, but in practice there is a leakage current due to the resistance (R off ) of the amorphous silicon channel layer.
이 때 누설전류가 충분히 작지 않으면 액정전압의 왜곡이 발생하여 플릭커의 주요 원인이 된다.At this time, if the leakage current is not small enough, distortion of the liquid crystal voltage occurs, which is the main cause of the flicker.
제1도의 (b)에 도시한 바와 같이, 기생용량(Capacitive coupling)으로는 비정질-실리콘 박막 트랜지스터에서는 게이트 전극과 소오스 전극, 게이트 전극과 드레인 전극 사이에 중첩(overlap) 부분의 존재로 인하여 각각 Cgs, Cgd의 기생용량(Parasitic capacitance)을 갖게 된다. Cgd는 TFT가 턴-온될 때 capacitive coupling에 의해 액정전압에 ΔV만큼 변동을 주며, 이는 화질에 중요한 영향을 끼치는 요인으로 작용하므로 TFT-LCD 설계시 주의를 요한다. ΔV는 근사적으로 다음과 같은 식으로 표현된다.As shown in (b) of FIG. 1, as the parasitic capacitive coupling, in the amorphous-silicon thin film transistor, each C is due to the presence of an overlap portion between the gate electrode and the source electrode, and the gate electrode and the drain electrode. It has parasitic capacitance of gs and C gd . C gd fluctuates by ΔV in liquid crystal voltage by capacitive coupling when TFT is turned on, which is important factor in image quality. ΔV is approximately expressed by the following equation.
TFT-LCD를 구동할 때 액정에 인가되는 실효전압은 제1도의 (b)에 도시한 빗금친 부분과 같다. 또한 LCD는 교류 구동이 필수적이므로 ΔV에 의한 직류(dc) 성분을 소거하기 위해 공통전극 전압 Vcom을 데이터 신호전압 중심으로부터 ΔV 정도 이동한다.The effective voltage applied to the liquid crystal when driving the TFT-LCD is the same as the hatched portion shown in Fig. 1B. In addition, since the AC drive is essential, the common electrode voltage V com is moved about ΔV from the center of the data signal voltage in order to eliminate the direct current (dc) component due to ΔV.
그러나 이러한 TFT-LCD에서 제2도와 같이, 쇼트간의 미스얼라인이 발생하면 Cgs의 값의 차이가 발생한다. 즉, 좌측의 도면과 같이 드레인 전극쪽이 소오스 전극쪽으로 미스얼라인 된 상태(오버레이 +0.5㎛)에서는 게이트와 드레인간 커패스터(Cgd)가 커지게 되고, 소오스 전극쪽이 드레인 전극쪽으로 미스얼라인 된 상태(오버레이 -0.5㎛)에서는 게이트와 드레인간 커패시터(Cgd)가 작아지게 된다. 이러한 차이는 액정표시장치의 화질을 떨어뜨리는 스티칭 문제를 야기시킨다. 즉,식에서 Cgd의 값은 화소에 인가되는 전압을 변형시키고 그 변형치가 쇼트간에 다를 경우 화면 불균형이라는 불량을 발생시킨다.However, in the TFT-LCD, as shown in FIG. 2, a misalignment between shorts causes a difference in the value of Cgs. That is, in the state where the drain electrode side is misaligned toward the source electrode (overlay +0.5 μm) as shown in the figure on the left, the capacitor C gd between the gate and the drain becomes large, and the source electrode side misses toward the drain electrode. In the aligned state (overlay -0.5 占 퐉), the capacitor C gd between the gate and the drain becomes small. This difference causes a stitching problem that degrades the image quality of the liquid crystal display. In other words, In the equation, the value of Cgd deforms the voltage applied to the pixel, and if the strain value is different between shorts, it causes a defect called screen imbalance.
따라서, 본 발명의 목적은 액정표시장치의 화소전극을 스위칭 시키기 위한 박막 트랜지스터를 코어 형상으로 만들어 주므로써, 노광시 미스얼라인이 발생하더라도 스티치 현상을 방지할 수 있는 액정표시소자를 제공하기 위한 것이다.Accordingly, an object of the present invention is to provide a liquid crystal display device capable of preventing a stitch phenomenon even when a misalignment occurs during exposure by making a thin film transistor for switching a pixel electrode of a liquid crystal display device into a core shape. .
이와 같은 목적을 달성하기 위한 본 발명의 액정표시소자는 한 쌍의 투광성 기판과, 상기 한 쌍의 투광성 기판 사이에 충진되고 그의 광학특성이 인가전압에 응답하여 변조될 수 있는 표시매체와, 상기 한쌍의 기판중의 하나의 내부표면상에 매트릭스로 배열되어 있고, 복수개로 분할된 화소전극과, 각 분할화소전극이 형성된 동일 기판에 각 분할화소전극과 전기적으로 접속되는 박막 트랜지스터와, 개개의 분할화소전극에 박막 트랜지스터를 통하여 데이터 신호전압을 인가하는 데이터 라인과, 개개의 스위칭소자를 구동하기 위한 구동전압을 인가하는 게이트 라인을 구비한 액정표시장치에 있어서, 상기 박막 트랜지스터는 평면구조가 코어 형상으로서, 데이터 라인과 전기적으로 연결되는 소오스 전극과, 상기 소오스 전극과 절연층에 의하여 분리되고, 상기 소오스 전극의 외경보다 적은 외경을 가지는 링형으로서, 게이트 라인과 전기적으로 연결되는 게이트 전극과, 상기 링 형상의 소오스, 게이트 전극의 내측에 위치한 원 형상으로서, 투명전극과 전기적으로 연결되는 드레인 전극을 구비한 것을 특징으로 한다.In order to achieve the above object, a liquid crystal display device of the present invention includes a pair of translucent substrates, a display medium filled between the pair of translucent substrates, and an optical characteristic thereof may be modulated in response to an applied voltage, and the pair A thin film transistor arranged in a matrix on an inner surface of one of the substrates and electrically connected to each of the divided pixel electrodes on the same substrate on which the divided pixel electrodes are formed; A liquid crystal display device having a data line for applying a data signal voltage to an electrode through a thin film transistor and a gate line for applying a driving voltage for driving individual switching elements, wherein the thin film transistor has a planar core shape. A source electrode electrically connected to the data line and separated by the source electrode and the insulating layer A ring shape having an outer diameter smaller than the outer diameter of the source electrode, the gate electrode electrically connected to a gate line, the ring shape source, and a circular shape located inside the gate electrode, the drain electrically connected to the transparent electrode It is characterized by having an electrode.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
첨부한 도면 제3도는 본 발명의 실시예에 따른 코어형 박막 트랜지스터를 구비한 액정표시소자의 부분 평면도이고, 제4도는 제3도의 A-A'선을 따라 절단된 단면도이며, 제5도는 화소전극구조에서 노광시의 미스얼라인이 발생한 경우의 구성도이다.FIG. 3 is a partial plan view of a liquid crystal display device having a core type thin film transistor according to an exemplary embodiment of the present invention. FIG. 4 is a cross-sectional view taken along the line AA ′ of FIG. 3, and FIG. 5 is a pixel. It is a block diagram at the time of the misalignment at the time of exposure in an electrode structure.
제3도에서 도시된 바와 같이, 본 발명의 박막 트랜지스터는 코어형상을 갖고, 데이터 라인(1)과 전기적으로 연결되는 소오스 전극(2)과, 상기 소오스 전극(2)과 절연층(3)에 의하여 분리되고, 상기 소오스 전극(2)의 외경보다 적은 외경을 가지는 링형으로서, 게이트 라인(4)과 전기적으로 연결되는 게이트 전극(5)과, 상기 링 형상의 소오스(2), 게이트 전극(5)의 내측에 위치한 원 형상으로서, 투명전극(6)과 전기적으로 연결되는 드레인 전극(7)을 구비한다.As shown in FIG. 3, the thin film transistor of the present invention has a core shape and has a source electrode 2 electrically connected to the data line 1, and the source electrode 2 and the insulating layer 3, respectively. A ring type having a smaller outer diameter than that of the source electrode 2, the gate electrode 5 being electrically connected to the gate line 4, the ring-shaped source 2 and the gate electrode 5. ) Is a circular shape located inside, and has a drain electrode 7 electrically connected to the transparent electrode 6.
상기와 같은 코어형의 박막 트랜지스터 구조를 갖는 액정표시소자를 설계하고, 그 설계에 따라서 제조할 때, 노광공정에서 제5도의 (a) 또는 (b)와 같은 미스얼라인이 발생하더라도, 쇼트간의 Cgd값의 차이가 발생하지 않고, 또한 코어의 안쪽에 드레인이 원형으로 형성되기 때문에 폭(W)/길이(L) 비의 증가로 온 전류(On Current)를 증가시키고 Cgd값은 상대적으로 줄일 수 있게 된다.When a liquid crystal display device having a core-type thin film transistor structure as described above is designed and manufactured according to the design, even if a misalignment such as (a) or (b) of FIG. Since there is no difference in the C gd value, and since the drain is formed inside the core in a circular shape, the increase in the width (W) / length (L) increases the On Current and the C gd value is relatively Can be reduced.
이상에서 설명한 바와 같이 본 발명의 액정표시소자는 박막 트랜지스터를 코어형으로 구성하므로써, 노광시 미스얼라인이 발생하더라도 채널의 게이트와 소오스간의 캐패시턴스 값의 차이가 발생하지 않는다. 따라서, 캐패시턴스의 값의 차이로 발생할 수 있는 화질의 열화를 방지하여 화상의 선명성을 높여주므로써 상품성을 향상시키는 효과를 제공한다.As described above, in the liquid crystal display of the present invention, since the thin film transistor is configured as a core type, even if a misalignment occurs during exposure, there is no difference in capacitance between the gate and the source of the channel. Therefore, it is possible to prevent the deterioration of image quality that may occur due to the difference in the capacitance value, thereby increasing the sharpness of the image, thereby providing an effect of improving the merchandise.
여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Although specific embodiments of the present invention have been described and illustrated herein, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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|---|---|---|---|
| KR1019950055593A KR100192176B1 (en) | 1995-12-23 | 1995-12-23 | LCD |
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| KR1019950055593A KR100192176B1 (en) | 1995-12-23 | 1995-12-23 | LCD |
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