KR100190736B1 - Automatic backup system for advanced power management - Google Patents

Abstract

The present invention relates to a suspend / resume computer system including a CPU, nonvolatile storage, volatile register and memory data, a power management processor, a backup stop timer, and a power source for circuit communication. The power management processor controls the regulation of the power supplied to the CPU by the power source. The suspend / resume system is controlled by an operating system that includes power management controls. The backup stop timer independently runs the power management portion of the operating system. If the power management portion of the operating system ceases to function, or the system must be stopped, the backup stop timer stops the system.

Description

Computer systems

1 is a perspective view of a personal computer in which the present invention may be implemented.

FIG. 2 is an exploded perspective view illustrating the components of the personal computer of FIG. 1 including a chassis, a cover, an electromechanical direct access storage device, and a planar board, and certain relationships between these components. FIG.

3A and 3B are block diagrams showing the relationship between predetermined components of the personal computer shown in FIGS.

4 is a state diagram of the computer system of the present invention showing four system states: normal, standby, suspend, and off.

5 is a block diagram showing a relevant portion of the power supply.

6A is a schematic diagram of a power management circuit of the present invention.

6B is an electrical schematic diagram illustrating the connection of a power management circuit to an internal modem.

Fig. 6C is a waveform diagram showing various signals in the reset circuit of the power management circuit.

6D is a schematic diagram showing a second embodiment of a power supply failure detection and correction circuit.

7 is a state diagram showing one of the switch states maintained by the power management processor of the present invention.

8 is a flow chart schematically showing the power-up routine of the present invention.

9A is a flowchart detailing the supervision routine called by the APM device driver in the operating system approximately every second.

9B is a flowchart detailing an APM job final request routine.

9C is a flowchart detailing the APM rejection final request routine.

10 is a flowchart detailing the stop routine of the present invention.

11 is a flowchart detailing the bootup routine of the present invention.

12 is a flowchart detailing a resume routine of the present invention.

Fig. 13 is a flowchart detailing the storage CPU state routine of the present invention.

14 is a flowchart detailing the CPU state recovery routine of the present invention.

Figure 15 is a flowchart detailing the archive 8959 state routine of the present invention.

Figure 16 is a flowchart detailing the dynamic archive file allocation routine of the present invention.

Figure 17 is a flow chart showing in detail the exit wait routine of the present invention.

18 is a flowchart detailing an entry wait routine of the present invention.

19 is a flowchart detailing the power management processor routine of the present invention.

* Explanation of symbols for main parts of the drawings

11: monitor 12: keyboard

17: power 21: switch

21: switch 23: LED

40: microcontroller 44: numerical coprocessor

48: memory controller 50: address MUX

52: data buffer 56: video controller

62 cache controller 68 latch / buffer with decoder

70: bus controller 72: DMA controller

74: buffer 78: input / output slot

84: 8277 Diskette Adapter 86: IDE Disk Controller

92: interrupt controller 94: RS-232 UART

96: CMOS NVRAM 98: CMOS Clock

100: parallel adapter 102: timer

104: keyboard controller 106: power management circuit

900: internal modem 902: external modem

904: Transformer 906: Clock Synthesizer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to computer system architecture, in particular desktop computer systems having a system suspend / resume capability based on the APM driver and systems in which It is about a backup suspend system that allows you to enter suspend state.

Personal computer systems are well known in the art. In general, personal computer systems, particularly IBM personal computers, have been used extensively to provide computer power in many areas of modern society today. Personal computers can typically be defined as desktops, floor standiugs, and portable microcomputers, which include a single central processing unit (CPU), RAM, and BIOS ROM including volatile memory ( volatile memory and non-volatile memory, system monitors, keyboards, one or more floppy diskette drives, fixed disk storage drives (also known as hard disks), so-called Pointing devices, referred to as mice, and optional printers. One of the salient features of such a system is the use of a motherboard or a system planar to electrically connect these components together. In addition, these systems are primarily designed to provide independent computing power for a single user, and are priced low for individuals or small businesses. Examples of such personal computer systems include IBM's PERSONAL COMPUTER AT and IBM's PERSONAL SYSTEM / 1 (IBM PS / 1).

Personal computer systems typically run software, such as word processing, manipulation of data through spreadsheets, data collection and relationship establishment using databases, and graphing. Perform various operations such as displays of graphics, electrical or mechanical system design using system-design software.

DESKTOP COMPUTER SYSTEM HAVING ZERO VOLT SYSTEM SUSPEND U.S. Patent Application No. O8 / 097,334, filed Jul. 26, 1993, entitled `` METHOD OF SAVING AND RESTORING THE STATE OF A CPU EXECUTING CODE IN A PROTECTED MODE '' 08 / 097,246 and US patent application Ser. No. 08 / 097,251, filed Jul. 23, 1993, entitled DESKTOP COMPUTER SYSTEM HAVING MULTI-LEVEL POWER MANAGEMENT, describe four power managemeut states: A computer system is disclosed that includes a normal operating state, a standby state, a suspend state, and an off state. The change between the off state, the normal operating state and the suspended state is made using one switch.

The normal operating state of the computer system of the present invention is substantially the same as the normal operating state of all typical desktop computers. The user can use the application program and basically treat this computer like any other computer. One difference is that there is a power management driver that runs in the background (in the BIOS and operating system) and runs in a transparent manner to the user. The power management driver portion of the operating system (OS) is the APM Advanced Power Management advanced programming interface written by Intel and Microsoft, and is part of Intel's 80X86 family of processors. It exists in most operating systems written to run on top of it. The power management device portion in the BIOS (APM BIOS) communicates with the APM OS driver. The APM OS driver and APM BIOS routines together control the transition of the computer into three different states and from the other three states.

The second state, the standby state, uses less power than the normal state, but all running applications are left running as before. In general, in the standby state, power is saved by placing each device in a low power mode. For example, in standby, power is saved by stopping the rotation of a fixed disk in the hard drive and stopping the generation of a video signal.

The third state is a suspended state. In the suspended state, the computer system consumes very little power. A suspended computer consumes little power from the wall outlet. The power dissipated is simply a small amount of power generated from a battery in the computer system (if the system is not receiving AC power) or from a secondary power line by the power source (if the system is receiving AC power). There is only a small amount of power that is used to keep the circuitry monitored.

This small amount of power usage is achieved by saving the state of the computer system to fixed disk storage (hard drives) before the power is turned off. To enter the suspended state, the computer system interrupts any executing code and transfers control of the computer to the power management driver. The power management driver checks the state of the computer system and writes the confirmed state of the computer system to the fixed disk drive storage device. The state of the CPU registers, CPU cache, system memory, system cache, video registers, video memory, and other device registers are all written to a fixed disk. The overall state of the system is kept in such a way that the coat application can recover without being adversely affected by interrupts. The computer then writes data to nonvolatile CM0S memory to indicate that the system has been stopped. Finally, the computer neutralizes the power generation of the power source. The overall state of the computer is securely stored in fixed disk storage, the system power is off, and the computer receives only a small amount of regulated power from the power supply and supplies it to the circuit to monitor the switch.

The fourth state, the final state, is off. In this state, the power supply does not provide conditioned power to the system, but the state of the computer system is not stored on a fixed disk. The off state is virtually identical to a typical desktop computer turned off in a conventional manner.

State-to-state switching is handled by the power management driver and typically includes two closure events, a flag, an inactivity staudby timer, and an inactivity suspend timer on a single switch. Is based on a timer. The system has one power button. This button can be used to turn on the computer system, stop the state of the system, restore the state of the system, and turn off the system.

The system facilitates state transitions using Advanced Power Management (APM) and facilitates system maintenance associated with state transitions. APM is an industry standard advanced programming interface developed to provide a way for the operating system and system BIOS in desktop and notebook to cooperatively manage power. APM is an excellent tool for easily stopping and resuming a system because APM includes the operating system within the abort process and allows the operating system to prepare the system before the abort process occurs.

However, depending on the operating system, depending on APM to halt the system, several drawbacks can occur. In Microsoft Windows version 3.1 and MS-DOS, there are many times when the operating system APM driver completely stops serving APM BIOS requirements. For example, when a model dialog box is displayed, the Microsoft Windows APM driver will completely stop servicing APM BIOS requests. As a result, a suspend and resume system based on the Microsoft Windows APM driver will never stop the system when the model dialog is being displayed. This presents a serious problem for the user because the system does not hang in response to the user's request to keep the system state. This result can be confusing to the user, and the user distrusts the suspend and resume system because it is not reliable enough for the suspend and resume system to rely on.

One solution is to rely on hardware system management interrupts (SMI) to halt the system, but such systems lose the benefits offered by the AP. For example, the APM driver can notify the entire APM aware software and hardware application that the system is about to be stopped, and they can respond accordingly. Thus, it is desirable to have a system that allows the system to rely on the APM driver while still stopping the system even when the APM driver is not running.

The system of the present invention is provided with an alternative stop system that automatically detects when the APM driver ceases to function and accordingly stops the system. The automatic backup stop system of the present invention does not intervene in the normal operation of the OS APM driver, and automatically intervenes when the APM driver stops servicing the APM BIOS request. When APM is reactivated, the backup abort system is automatically disengaged, allowing the system to take advantage of APM with the higher reliability provided by the backup abort system.

In the backup abort system of the present invention, the new countdown timer expires if the OS APM has not serviced the APM BIOS request for a predetermined time period. This timer is a free running timer that counts the time units that can be restarted, i.e. reloaded to their original values, e.g. seconds. The timer expires when it counts down to zero. In a preferred embodiment, the new timer is maintained in external hardware and is interrupted by an interrupt service routine, for example a system BIOS timer zero interrupt handler or the SMI interrupt service routine. Serviced. Alternatively, the timer may be implemented and serviced only by an interrupt service routine.

Preferably, the new timer is serviced by the system BIOS timer zero interrupt handler, which is modified to check if the new timer has expired and the user wants to stop (ie, a stop request is pending). If this condition is met, the system can be stopped without notifying the operating system, that is, without stopping being placed in the APM BIOS event queue. Upon system restart, a critical resume event is placed on the APM event queue. When the running APM driver polls for service events again, the APM driver receives a critical resume event, allowing the operating system to initiate operations such as clean up system time updates after resumption.

Preferably, in the APM system BIOS, upon every get event call from the OS APM driver, a new countdown timer is reset, i.e., reloaded to its original value. This prevents the countdown timer from expiring when the APM is servicing the event and operating normally. If the operating system APM driver stops the event service (if an acquisition event call does not exist), the countdown timer will expire without reset. When the user attempts to stop, the system automatically responds when the countdown time reaches zero.

The countdown timer is implemented in a low cost programmed microcontroller that also provides additional features for the system. One of the features of the microcontroller is a general-purpose countdown timer used to provide an automatic backup stop system.

At approximately 32 timer level zero interrupts, the system BIOS interrupt handler checks if the countdown timer has expired and if the user wants to stop. When this condition occurs, the system is immediately stopped. The countdown timer is set to 16 seconds to allow dead zones in APM (e.g., full-screen MS-DOS under Microsoft Windows, where the APM acquisition event poll rate is once every 15 seconds).

The present invention compensates for the shortcomings of Advanced Power Management (APM) in the operating system. The countdown timer starts counting as soon as the OS APM driver fails to service the BIOS event. Such a system is automatically involved when the operating system APM driver stops providing acquisition event services. Similarly, the system automatically leaves the intervention state when the APM driver starts to service the event again. The present invention increases the dependency of the suspend and resume system. Known blind spots are automatically covered by a backup stop system. The backup system is fully automatic and does not require user intervention.

The above and other advantages of the present invention will be apparent from the detailed description of the preferred embodiments of the present invention.

In the accompanying drawings in which the present invention has been implemented and constitutes a part of this specification, embodiments of the invention have been illustrated, and by reference to the accompanying drawings in conjunction with the foregoing general description of the invention and the following detailed description of the invention, the invention Understand the principles of

Although the present invention will be described in detail below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it will be understood by those skilled in the art that various changes may be made while obtaining the preferred results of the invention. Accordingly, the following description is to be understood that it is intended to those skilled in the art for a broader description and not to limit the invention. The invention is not limited to computer architecture design, but includes digital design, BIOS design, protected mode 80486 code desgn, application code design, operating system code design, and use of advanced power management advanced programming interfaces. It deals with the complete design of computer systems. This application is written for those who are familiar with all aspects of computer systems.

Referring now to the accompanying drawings in more detail, a microcomputer system incorporating the present invention is shown by reference numeral 10 (FIG. 1). As mentioned above, the computer 10 has an associated display monitor 11, keyboard 12, mouse 13, and a printer or plotter 14. The computer 10 (FIG. 2) is a cover 15 formed of an inner shield member 18 and a decorative outer member 16 defining a sealed and sealed volume with a chassis 19. And a data processing and storage component for processing and storing digital data in a sealed and shielded volume. At least some of these components are mounted on the chassis 19 to provide the components described above and other associated elements such as floppy disk drives, various types of direct access storage, accessory adapter cards or boards, and the like. It is mounted on a motherboard planer 20 or on a motherboard that provides a means for electrically interconnecting the components of the computer 10 including them. As will be described in more detail later, means are provided to the planer 20 for transmitting input / output signals to / from the operating components of the microcomputer.

The computer system has a power source 17, a power button 21, hereinafter referred to as a switch 21, and a power / feedback LED 23. As described below, unlike conventional power switches in typical systems, power button 21 does not switch unregulated line power to / from power source 17. The chassis 19 has a base 22, a front panel 24, and a rear panel 25 (FIG. 2). The front panel 24 defines at least one open bay (four bays in the form shown) to store data such as disk drives for magnetic or optical disks, tape backup drives, and the like. Accept the device. In the illustrated form, a pair of upper bays 26 and 28 and a pair of lower bays 29 and 30 are provided. One upper bay 26 is suitable for accommodating a peripheral drive of a first size (known as a 3.5 inch drive), while the other upper bay 28 is of two sizes (such as 3.5 and 5.25 inches). It is suitable for accommodating a drive of one size selected. The lower bays are only suitable for accepting one size (3.5 inch) device. Floppy disk drive 27 shown in FIG. 1 is a removable medium direct access storage device, and as is generally known, a diskette can be inserted therein, and the diskette can be used to Can be received, stored and transmitted. Hard disk 31 is a fixed medium direct access storage device capable of storing and transferring data, as is known.

Prior to associating the above-described structure with the present invention, it would be useful to review an overview of the general operation of the personal computer system 10. 3A and 3B, a personal computer that illustrates various components including components mounted to the planer 20, connections connecting the planer to the I / O slots, and other heartware of the personal computer. A block diagram of the system is shown. The system processor 40 (here, CPU 40) connected to the planer includes a microprocessor and is connected to the memory control device 46 by a high speed CPU local bus 42, which is also connected to the memory control device ( 46 is connected to volatile random access memory (RAM) 53. Memory control device 46 includes memory controller 48, address multiplexer 50, and data buffer 52. Memory control Device 46 is connected to random access memory 53, shown as four RAM modules 54. Memory controller 48 maps an address to / from microprocessor 40 to a particular RAM 53 area. This logic is used to reclaim the RAM previously occupied by the BIOS The memory controller 48 generates a ROM select signal ROMSEL to check the ROM 88. Enable or Disable System Program Processor 40 is there any appropriate microprocessor can be used, one instance a suitable microprocessor is the Intel 80486's.

The Intel 80486 has an internal cache, so if the CPU 40 is an Intel 80486, it will have a CPU cache 41.

Although the invention will be described in particular with reference to the system block diagrams of FIGS. 3A and 3B, the apparatus and method according to the invention can also be used in other hardware configurations of the planer board. For example, system processor 40 may be an Intel 80286 or 80386 microprocessor. As used herein, the term 80286,80386 or 80486 refers to an Intel microprocessor. Recently, however, other manufacturers have developed microprocessors capable of executing an instruction set of an Intel X86 architecture, and the above term includes microprocessors capable of executing this instruction set. As can be appreciated by those skilled in the art, early personal computers typically used Intel 8088 or 8086 microprocessors, which are well known as system processors. These processors have the ability to address 1 megabyte of memory. Recently, personal computers typically use high speed Intel 80286,80386 and 80486 microprocessors, which can operate in virtual or real mode to emulate a low speed 8086 microprocessor, Alternatively, some models can operate in a protected mode that extends the addressing range from 1 megabyte to 4 gigabytes. In essence, the real-mode features of the 80286, 80386, and 80486 provide hardware compatibility for software written for the 8086 and 8088 microprocessors. Processors in the Intel family described above are often identified by the last three digits in the overall type designater, such as 486.

Referring again to FIGS. 3A and 3B, the CPU local bus 42 (including the data, address and control components) is a number of microprocessors 40 (if not provided to the CPU 40 itself). A coprocessor 144, a video controller 56, a system cache memory 60, and a cache controller 62 are provided. Video controller 56 is associated with a monitor (or video display terminal) 11 and video memory 58. In addition, a buffer 64 is connected on the CPU local bus 42. The buffer 64 is connected to the slow system bus 66 (relative to the CPU local bus 42) and contains address, data and control components. System bus 66 connects between buffer 64 and another buffer 68. The system bus 66 is also connected to the bus control, the timing device 70 and the DMA device 71. The DMA device 7 consists of a central arbiter 82 and a DMA controller 72. The additional buffer 74 provides an interface between an optional feature bus, such as the system bus 66 and the Industry Standard Architecture (ISA) bus 76. The bus 76 is connected with a number of I / O slots 78 to accommodate ISA adapter cards (not shown). The ISA adapter cart is plugged into a number of I / O slots 78 to provide additional I / O devices or memory to the system 10.

Arbitration control bus 80 provides DMA controller 72 and central arbiter 82 with I / O slots 78, diskette adapters 84, and integrated drive electronics (IDE) fixed disk controllers (86). ).

The microcomputer system 10 is shown as having a basic 4 megabyte RAM module 53, but additional memory can be added by adding optional higher-density memory modules 54 to the third memory. It should be understood that they may be interconnected as shown in FIGS. 3 and 3B. The invention is described with reference to a basic 4 megabyte memory module for illustrative purposes only.

Latch buffer 68 is connected between system bus 66 and planer I / O bus 90. Planer I / O bus 90 includes address, data, and control components. Along the planer I / O bus 90, a diskette adapter 84, an IDE disk adapter 86, an interrupt controller 92, an RS-232 adapter 94, a nonvolatile CMOS, also referred to herein as NVRAM. Various such as RAM 96, CMOS real time clock 98, parallel adapter 100, multiple timers 102, read only memory (ROM) 88, 8042 (104), and power management circuits 106. I / O adapter 84 and other components are connected. 8042 104 is a slave microprocessor that interfaces keyboard 12 and mouse 13. The power management circuit 106 is in circuit communication with a power source 17, a power switch 21, a power / feedback LED 23, an internal modem 900 and / or an external modem 902. . The external modem 902 is typically connected to a transformer 904, which is connected to a wall outlet as is well known to those skilled in the art. Modems 900 and 902 are connected to a typical telephone outlet. The power management circuit 106 is shown in FIGS. 6A and 6B and will be described in more detail with reference to FIGS. 6A, 6B, 6C and 7. Read-only memory 88 includes a BIOS used to interface between the operating system of microprocessor 40 and the I / O device. The BIOS stored in the ROM 88 may be copied to the RAM 53 to reduce the execution time of the BIOS. ROM 88 also responds to memory controller 48 (via a ROMSEL signal). When ROM 88 is enabled by memory controller 48, the BIOS is run from ROM. When the ROM 88 is disabled by the memory controller 48, the ROM does not respond to address inquiries from the microprocessor 40 (ie, the BIOS is executed from RAM).

The real time clock 98 is used to calculate the time of day and the NVRAM 96 is used to store system configuration data. That is, NVRAM 96 contains a value that indicates the current configuration of the system. For example, NVRAM 96 includes information such as fixed disk or diskette capacity, display type, memory capacity, time, date, and the like. Moreover, each time a special configuration program such as SET Configuration is executed, these data are stored in NVRAM. The purpose of the set configuration program is to store values in NVRAM that represent the configuration characteristics of the system.

Almost all of the foregoing devices include volatile registers. For simplicity, the register of a particular device will be referred to as that device. For example, the CPU register is referred to as the CPU 40 register, and the video controller register will be referred to as the video controller 56 register.

As mentioned above, the computer includes the above-described components of the microcomputer, with a cover forming a sealed and shielded volume with the chassis 19. The cover 15 is preferably an outer decorative cover member 16, which is a single casting component made of a modable synthetic material, and a thin metallic sheet liner formed to match the shape of the decorative cover member. liner) 18.

However, the cover can be manufactured in other known manners, and furthermore, the usefulness of the present invention is not limited to an enclosure of the type disclosed.

(Operation state)

Referring now to FIG. 4, a state diagram of a computer system of the present invention is shown. The computer system 10 of the present invention has four states: a normal operating state 150, a standby state 152, a suspended state 154, and an off state 156. The transitions between the states shown in FIG. 4 are for illustration of the preferred embodiment only and are not intended to limit the invention. Thus, additional events can be used to cause state transitions.

The normal operating state 150 of the computer system 10 of the present invention is substantially the same as the normal operating state of a typical desktop computer. The user can use the application and basically treat it like any other computer. One difference that the user can see is the presence of a power management driver (APM OS driver) in the operating system, which runs in the background and in various APM BIOS routines.

The APM BIOS routines will be described later, including the Suspend routine, Resume routine,

Boot-Up routines, supervisor routines, Save CPU State routines, and Restore CPU State routines. An APM BIOS routine not shown in the figure is an APM BIOS Routing Routine. The APM BIOS routing routine essentially receives commands from the APM OS driver and invokes the appropriate APM BIOS routine. For example, when the APM OS driver issues a stop command, the APM BIOS routing routine calls the stop routine. In another example, whenever the APM OS driver issues a Get Event command, the APM BIOS routing routine calls the supervision routine. These routines are located in the BIOS and are shadowed together when the BIOS is shadowed. Power management drivers in the OS and APM BIOS routines control the transition between the four states of the computer. The word APM generally refers to the APM OS driver, although it may vary in context.

The second state, i.e., the standby state 152, uses less power than the normal operating state 150, but allows the application to run as if it had normally run. In general, power in standby state 152 is saved by a coat that places the device in its respective low power mode. In the preferred embodiment, by stopping the rotation of the fixed disk (not shown) in the fixed disk storage device 31 in the standby state 152, stopping the generation of the video signal, and placing the CPU 40 in the low power mode Saving power, which will be described in more detail later. However, this is not intended to limit the invention and other methods may be used, such as slowing down or stopping the CPU clock to reduce power consumption.

In a preferred embodiment, power is saved in three separate ways. First, in the normal operating state 150, the fixed disk in the fixed disk storage device 31 rotates constantly, for example, at 3600, 4500, or 5400 revolutions per minute (RPM). In the standby state 152, the IDE disk controller 86 has a command for entering the fixed disk storage device 31 into the low-power mode (i.e., stopping the rotation of the fixed disk in the fixed disk storage device 31). This saves the power typically consumed by a motor (not shown) in the fixed disk storage 31 during rotation of the fixed disk.

Secondly, in the normal operating state 150, the video controller 56 of the computer system is connected to a video signal corresponding to the image shown in the video display terminal 11 (HSYNC, VSYNC, R, G, well known in the art). B) always occurs. In standby state 152, video controller 56 stops generating video signals, thereby saving power typically consumed by video controller 56. HSYNC, VSYNC, R, G and B are all driven at approximately 0.00 VDC. Video Electronics Standards Association compliarnt monitors turn off by themselves, saving even more power.

Third, in the normal operating state 150, the CPU 40 always executes commands, thus consuming power. In standby state 152, the BIOS issues a HALT instruction in response to an APM CPU Idle Call. Executing the HALT instruction significantly reduces CPU power consumption until the next hardware interrupt occurs. If the CPU is truly idle, the CPU will remain idle for more than 90% of the time.

Some systems have a screen saver to prevent phosphor burn-in at the front of the video display terminal by darkening the screen 11. In most such systems, video controller 56 still generates a video signal. It simply generates a signal that corresponds to a dark screen or dynamic display. Thus, a computer system running a screen-saver still consumes the power required to generate this video signal.

The third state is suspended state 154. In the suspended state 154, the computer system consumes very little power. In a preferred embodiment, the suspended computer consumes less than 100 milliwatts of power from the wall outlet. The power consumed is about 5 watts of power consumed due to inefficiency in the power supply 17 and a small amount of power used by the power management circuit 106.

This extremely small amount of power usage is achieved by storing the state of the computer system in a fixed disk storage device (hard drive) prior to turning off the power supply. To enter suspend state 154, CPU 40 interrupts all application programs and transfers program execution control of the CPU to the power management driver. The state of the power management driver computer system 10 is checked and the overall state of the computer system is recorded in the fixed disk storage device 31. The states of the CPU 40 register, the CPU cache 41, the system RAM 53, the system cache 60, the video controller 56 registers, the video memory 58, and the remaining volatile registers are all fixed disk drives 81. ) Is recorded. The overall state of system 10 is stored in such a way that it can be recovered without significant significant usability penalties. That is, the user does not have to wait for the loading of the system operating system, the loading of the graphical user interface, and the loading of the application program, which are normally required.

The computer then writes data to nonvolatile CMOS memory 96 indicating that the system has been stopped. Finally, the CPU 40 instructs the microcontroller U2 to stop the supply of regulated power to the system via ± 5 VDC and ± 12 VDC of the power source 17. Computer system 10 can now lower power consumption because the entire state of the computer is safely stored in fixed disk storage 31.

State is used throughout the specification in two ways that are similar but can be confused. The device may be in a certain state. Four system states--normal 150, standby 152, suspend 154, and off 156-- refer to the general states of the computer system of the present invention. These states describe computer system 10 in a general manner. For example, while in the normal operating state 150, the CPU 40 is still executing code and changes a number of registers in the system 10. Similarly, similar activity occurs while in standby state 152. Thus, the memory and register configurations of the computer system 10 are dynamic while the system 10 is in the normal operating state 150 and the standby state 152.

Other devices may also be in a given state. The power management circuit 106 preferably uses a second processor such as the microcontroller U2 shown in FIG. 6A of the power management processor to implement various power management features. There are a number of processors suitable as such processors. This embodiment uses a preprogrammed 83C750 microcontroller as the power management processor. Variables and pins of the microcontroller U2 may be in various states as described with reference to FIG. 6A.

The foregoing meaning may be contrasted with the state of a device, for example the state of the computer system 10 or the state of the CPU 40. The state of a device refers to the condition of that device in a particular computer cycle. All memory locations and registers have specific binary values. The state of a device is a static binary snapshot of the device's contents.

The state of computer system 10 refers to operational equivalents and does not necessarily mean exact copies. For example, a computer system in state A may be a CPU cache 41 or a system cache ( 60 may have a predetermined memory. It is possible to place this computer system in state B by flushing the contents of either cache to the system RAM 53. Purely speaking, because the contents of the cache and system RAM are different, the state of the computer system in state A is different from that of the computer system in state B. However, state A and state B are identical in terms of software operation, since they do not affect the running program except for a slight reduction in system speed (which occurs because the program cannot run using the cache). In other words, because of the cache being flushed, the computer is slightly degraded until the cache area is reloaded with useful code, but the computer in state A and the computer in state B are identical in terms of software operation.

The word power is also used in two similar meanings that can be confusing.

But power is about electric power. However, power is also used as it relates to computational power. However, these differences will be clearly understood by context.

Circuitry generally refers to a physical electronic device or a plurality of devices that are electrically interconnected. However, the circuit is also intended to include CPU code equivalents of the physical electronics. For example, the two-input NAND gate may be implemented by 74LS00 on the one hand or may be implemented in the same programmable device. These two devices are physical electronic devices. On the other hand, by causing the CPU 40 to read both inputs from two CPU-readable input ports, generate NAND results using CPU commands, and output the results through the CPU-writable output port. The NAND gate can be implemented. Such a CPU-interfaceable port can be as simple as decoded latches, their programmable device equivalent, or as complex as a PIA, as is well known in the art. The circuit should be construed broadly to include all three NAND gate implementations described above. In some cases, a circuit may simply refer to an electrical pathway. Types of electrical pathways include wires, traces, or vias on a printed circuit board, or form a single electrically connected path. Several types of electrical path combinations.

The signal may represent a single electrical waveform or multiple waveforms. For example, the video controller generates a video signal. This video signal is actually a signal on a number of electrical conductors (such as HSYNC, VSYNC, R, G, B, etc., well known in the art).

Referring back to FIG. 4, the last fourth state is an off state 156. This off state 156 is substantially the same as a typical computer system turned off in a conventional sense. In this off state, the primary / regulation unit 172 of the power source 17 is connected to the computer 10 with a small amount of regulated power via AUX5, as described in more detail with reference to FIG. The regulated power supply is turned off except for the regulated power, and the state of this computer system 10 has not been stored on the fixed disk 31.

Suspend state 154 and off state 156 are similar in that power source 17 no longer generates regulated power. In other words, in the off state 156, unlike the suspended state 154, the state of the computer system is not stored in the hard drive 31. Also, when exiting off state 156, computer 10 is booted as if it is turned on. That is, any executable code must be started by the user or automatically by a means such as the AUTOEXEC.BAT file. However, when leaving the stopped state, execution resumes from the state at the time when the computer 10 was interrupted.

4 also shows a general schematic of the events causing the transition between the four states. These events will be described in detail with reference to FIGS. 6 through 8, but some explanation at this point may be helpful. Power button 21, two timers (inactivity wait timer and inactivity stop timer, see description of FIG. 9), minutes to wake up timer suspend enable flag (See the description with reference to FIGS. 6A and 7) all affect the state in which the computer enters. In general, the two timers may be hardware or CPU code timers that run as programs on the CPU. In a preferred embodiment, these two timers are CPU code timers that run from the BIOS data segment. However, these two timers may be hardware timers, which may be a better solution in terms of reducing the overhead of the system. These timers will be described in more detail with reference to FIG. These two timers are activated when the computer 10 is in the normal operating state 150 or the standby state 152. The timers communicate with other routines such that the expiration of either timer causes a transition as described below. Either or both timers may be configured to expire after a certain peroid of time, depending on the particular needs of the user. In a preferred embodiment, the inactivity wait timer and inactivity stop timer may be set to end after 10 to 90 minutes. Either or both timers can be stopped.

That is, it can be configured to never terminate. Stopping the timer may take the form of actually stopping the incremental counting action of the timer or simply ignoring the end of the timer. In a preferred embodiment, setting 0 as the timer end value does not test the timer end.

For example, a user of a network computer may not want the computer to enter the suspended state 154 because the LAN may fail with respect to the computer as the computer enters the suspended state.

In theory, the timers can count-up or count-down, reset to a fixed predetermined state, and the timer can be started (or resumed). When one counts to another constant predetermined state, or the current value may be used to calculate the sum or difference as an endpoint expiration trigger In a preferred embodiment, when the timer is reset, a real time clock ( The present value of the minutes variables from 98) is stored, and the timer checks whether it is finished by subtracting the current minute value from the stored minute value and comparing this difference with the user-selected value. .

Both timers are affected by certain system activity.

For example, in a preferred embodiment, each timer may be set by the user's action of pressing the keyboard 12 key, moving the mouse 13, and pressing the button of the mouse 13, or by the operation of the hard drive 31. It is restarted, which will be described in detail with reference to FIG. Therefore, neither timer is ever terminated while the user presses a keyboard 12 key or uses the mouse 13, or while an application accesses the hard drive 81. It is also possible to use other system events to reset the timer. Alternatively, any hardware interrupt activity may be monitored. Thus, it may be desirable to allow printing (IRQ 5 or IRQ 7) or COMM port access (IRQ 2 or IRQ 3) operations to prevent entering the suspended state 154 of the system.

The stop enable flag is a CPU-manipulable and readable latch in the microcontroller U2, which will be described in detail with reference to FIG. 6A. In summary, when the switch 21 is pressed with the microcontroller U2 set to one mode, the system 10 is turned off, and the switch 21 is set with the microcontroller U2 set to another mode. When pressed, system 10 enters a suspended state 154. When the computer button 10 is in the normal operating state 150 and the power button 21 is pressed while the stop enable flag set in the microcontroller U2 is cleared, the computer system 10 is referred to by reference numeral 158. Enter the off state 156 as shown. Pressing the power button 21 when the computer system 10 is in the off state 156 causes the computer system to enter a normal operating state 150, as shown by reference numeral 160. The system can also enter the normal operating state 150 from the off state 156 by various external events described in detail below.

If the computer system 10 is in the normal operating state 150, the computer 10 may enter the standby state 150 by one event. As shown at 162, when the inactivity wait timer expires, computer system 10 will change to standby state 152. Alternatively, the system may provide means such as dialog boxes, switches, other input devices, etc., to allow the user to force the system into immediate standby. As shown by reference numeral 164, if there is any system or user activity of the type described above, including the user pressing the power button 21 while the computer system 10 is in the standby state 152, Computer system 10 exits from the standby state and reenters the normal operating state.

When the power button 21 is pressed, the system enters the normal operating state 150 from the standby state 152. As described above, in the standby state, the monitor 11 is in a blank state and the power / feedback LED 23 is on or flashes depending on how the flag in the microcontroller U2 is configured. A user who is accessing the system to use the system recognizes that the monitor 11 is off, thinks that the system is in the stopped state 154 or the off state 156, and presses the power button 21 to do so. An attempt may be made to enter the system into a normal operating state 150. If the system has entered the suspend state 154 or the off state 156 as a result of pressing the power button 21, the user will turn off or halt the computer, which is not his original intention. Thus, when the power button 21 is pressed in the standby state 152, the system changes from the standby state 152 to the normal operating state 150. The CPU 40 will soon know that the switch was pressed even in the idle state. The hardware interrupt causes the CPU 40 to escape from the idle state approximately 20 times per second, and then during the next APM acquisition event, the microcontroller U2 is acted on to determine whether the switch 21 has been pressed.

If the computer 10 is in the normal operating state 150, two events may cause the computer to enter the suspended state 154. First, as shown at 166, when the inactivity suspend timer expires, computer system 10 will change to suspend state 154. Second, as shown by reference numeral 166, pressing the power button 21 while the suspend enable flag recorded in the microcontroller U2 is SET causes the computer system 10 to immediately enter the suspend state 154. Can enter. Alternatively, the APM driver may additionally issue a suspend request via the Set Power State (Suspend) command, which causes the APM BIOS driver to invoke the suspend routine. When the user presses the power button 21 while in the suspended state, the computer changes to the normal operating state 150, as shown at 168.

Also, the system 10 is changed from the stopped state 154 to the normal operating state 150 (reference number 168), or from the off state 156 to the normal operating state 15o (reference number 160). You can use various external events to do this. For example, a telephone ring detect circuit in the microcontroller U2 of the circuit of FIG. 6A may turn off the system 10 when the attached telephone line rings and from normal to stop state 154. And may enter the operational state 150. This feature is useful for systems that receive fax data or digital data. The system enters normal operation in response to a telephone ring, performs preset functions such as receiving incoming fax transmissions, uploading or downloading files, allowing remote access of the system, and terminating an inactivity timer. By re-entering the suspend mode in response, it consumes power only while the system is in a normal operating state.

The microcontroller U2 likewise implements a mitotes to make alarm counter, by which an alarm event causes the system 10 to operate normally from the stopped state 154 or the off state 156. State 150 may be entered. Such a system is useful for transmitting a fax or digital data at a predetermined time at a low phone charge, and performing a system maintenance function such as backing up the system hard drive 31 to a tape backup system. For example, the wake up time is set to cause the scheduler to turn on the system at a predetermined time prior to executing the tape backfill program. Alternatively, the APM BIOS scheduler may be configured for execution of the tape backup program.

Finally, as shown at 170, if the inactivity suspend timer expires when the computer system 10 is in the standby state 152, the computer system 10 changes to the suspended state 154. The computer system 10 may not change back from the suspended state 154 to the standby state 152 and may only transition to the normal operating state 150, as described with reference to reference numeral 168.

Clearly, computer system 10 may not change state immediately. In transitions from any of the four states, a certain period of time is required to make the necessary system changes. Details of each transition period will be described in detail with reference to FIGS. 6 to 15.

(System hardware)

Before describing in detail the code executed on the CPU 40, it is helpful to first discuss the hardware required to achieve the four states described above.

5 shows a block diagram of the power source 17. The power source 17 has two devices, the control device 174 and the main / regulator 172. Power source 17 has a number of inputs, such as Line-in receiving 115 VAC from a typical wall outlet, ON to control the regulating activity of power source 17, and the like. The power source 17 has a number of outputs such as AC line-out, _± 5 VDC, _± 12 VDC, AUX5, GND, and POWERGOOD. AC line-out is typically 115 VAC (unregulated 115 VAC) delivered to the power input (not shown) of video display terminal 11. Control device 174 receives an ON input and generates a POWERGOOD output. The main / regulator 172 selectively regulates 115 VAC from the line-in input to _± 5, _± 12 VDC. The main / regulator 172 is interfaced by the controller 174 to regulate power to _± 5 VDC and _± 12 VDC depending on the value of ON. In a preferred embodiment, the control device 174 must provide insulation, such as a suitable optosolator, for the circuit which generates the ON signal.

Line-in input and AC tin-out, _± 5 VDC, _± 12 VDC, GND, and POWERGOOD are well known in the art. When the power supply 17 is off, i.e., does not provide a regulating voltage from line-in, the POWERGOOD signal is logically zero (ZERO).

When power source 17 is on, power source 17 generates a regulated voltage of _± 5 VDC, _± 12 VDC from the 115 VAC line-in. These four regulating voltages and their associated GNDs are system power commonly known in the art. If the regulated voltage level is within acceptable tolerances, the POWERGOOD signal will change to logic 1 (ONE). If the +5 or +12 voltage line is out of tolerance, the POWERGOOD signal will be logic 0, indicating this condition.

The AUX5 output provides an auxiliary +5 VDC (auxiliary _± 5 VDC) to the planer. When the power source 17 is plugged into a typical wall outlet providing a nominal 115 VAC, the main / regulator 172 will adjust the regulation +5 VDC regardless of whether the power source is on or off. To provide. Thus, while the power source receives AC power, power source 17 always provides the nominal +5 VDC to AUX5. The main / regulator 172 differs from the AUX5 output in that it generates an regulated +5 VDC through the +5 output only during the power up 17. Also, in the preferred embodiment, the main / regulator 172 provides a few amps of current at +5 VDC through the +5 output, while a current of less than 1 amp at +5 VDC through the AUX5 output. It is different in that it is provided.

A typical conventional power supply uses a high-amperage double-throwswitch to connect and disconnect line-in inputs to and from the regulation section of the power supply. The power supply 17 of the present invention does not use a high-current twin throw switch. Instead, the switch 21 controls the circuit that generates the ON signal.

In a preferred embodiment, the switch 21 is a momentary single-pole, single throw pushbutton. However, one of ordinary skill in the art would be able to modify the circuit of FIG. 6A to use other types of switches, such as single pole double throw switches. The AC line-in is always connected to the main / regulator 172 from the wall outlet. When ON is a logic 1 (approximately AUX5, nominally +5 VDC), primary / regulation unit 172 is 115 VAC line - no control over the the _± 5 or _± 12 outputs to _± 5 VDC or _± 12 VDC. Main / regulator 172 provides a low-current nominal +5 VDC at the AUX5 output. On the other hand, when ON is logic 0 (approximately GND), the main / regulator 172 regulates 115 VAC line-in to _± 5 VDC and _± 12 VDC, respectively, via four _± 5 and _± 12 outputs. Thus, when ON is 1, the power supply 17 is off '' and when ON is 0, the power supply 17 is on.

In specific cases, a power source with an AUX5 output and an ON input, such as the power source 17 described above, can be obtained from more conventional power suppliers.

Referring now to FIG. 6A, FIG. 6A is a schematic diagram of an electronic circuit of the computer system 10 of the present invention. The circuit of FIG. 6A is responsible for the interface between the switch 21, the power / feedback LED 23, the power supply 17, the video display terminal 11 and the code executed on the CPU 40. FIG.

The circuit comprises four integrated circuits, namely a first preprogrammed PAL16Lb (U1), a preprogrammed 83C750 microcontroller U2, a 74LS05 (U3) and a second programmed PAL16L8 (U4) well known in the art. (Not shown) and various discrete components in circuit communication as shown in FIG. 6A. In general, PAL U1 and U4 (not shown) interface between planar input / output bus 90 and microcontroller U2 of FIGS. 3A and 3B, and microcontroller U2 It is interfaced to the remaining circuitry of FIG. 6A and to the switch 21, the power supply 17, the video display terminal 11 and the programmable clock synthesizer 906. Clock synthesizer 906 is one of a number of clock synthesizers well known to those skilled in the art. One such component is the CH9055A manufactured by Chrontel, which is readily available from a number of sources.

The circuit of FIG. 6A is suitable for acting as a switch 21, 16 MHz crystal Y1, 18 resistors R1-R18, 8 capacitors C1-C8, in a preferred embodiment as a logic switch. It further comprises three N-type MOSFETs Q1-Q3, six 1N4148 small signal diodes CR1-CR6, which are standard low current NMOS FETs, all of which are configured and connected as shown in FIG. 6A. Resistor R1-R18 is a 1/4 watt resistor and has the value (± 5%) shown in Figure 6A. The capacitance C1 is a 10 μF (± 10%) electrolytic capacitor. Capacities (C2 C3) are 22pF (± 10%) tantalum capacitors. Capacitors C4-C8 are 0.1 μF (± 10%) ceramic capacitors. Finally, capacitor C9 is a 1000 pF (± 10%) ceramic capacitor.

Crystal Y1 and capacitors C2 and C3 generate signals used by microcontroller U2 to control the timing of operation as is well known in the art. Diodes CR1 and CR3 and resistor R14 separate the AUX5 signal from the VBAT signal, while allowing the AUX5 signal to complement the VBAT signal so that the battery 171 is not depleted while the power source 17 generates the AUX5 signal. Do not The AUX5 signal is stepped down through the diodes CR1 and CR3 to supply the appropriate voltage to the device connected to VBAT. Alternatively, the VBAT line may be separated from the AUX5 line.

The second PAL U4 (not shown) is connected to the address line from the SA 1 to the SA 15 and the AEN (address enable) line. SA 1 to SA 15 and AEN are part of the planar input / output bus 90 shown in FIGS. 3A and 3B. The second PAL U4 is simply programmed to function as an address decoder, and a preset address appears on the address line from address line SA 1 to SA 15, and when the AEN line is active, the active low signal ( active low signal) Provides DCD #. In this particular embodiment, the second PAL U4 is programmed to decode two consecutive 8-bit input / output ports at addresses 0ECH and 0EDH. Alternatively, the DCD # signal may be generated by another electronic device, such as a memory controller or ISA controller chipset, as is well known in the art.

The first PAL U1 has (i) a read / write interface function between the CPU and the microcontroller U2 for command and data to be transferred between the CPU 40 and the microcontroller U2, and (ii) the mouse interrupt INT12. And a logical OR function of the keyboard interrupt INT1, and (iii) a reset output function for resetting the microcontroller U2 in response to a command from the CPU 40.

The first PAL U1 uses two consecutive input / output ports, which are also referred to herein as power management ports. The first PAL U1 has eight inputs from the planar input / output bus 90, i.e. SD (4), SD (0), SA (0), IOW #, IOR #, RST-DRV, IRQ1 and Has IRQ12. The first PAL U1 is reset to its known initial state by the active high signal RST-DRV input at pin 7 (I6) generated by the memory controller 46 as is well known to those skilled in the art.

The reset line RST751 of the microcontroller U2 is present at the pin 9. A reset subcircuit 920 is responsible for the generation of the RST751 signal, four resistors R4, R16, R17 and R18 and two capacitors C1 and C8 as shown in FIG. 6A. And two MOSFETs Q2 and Q3, and are in circuit communication with the first PAL U1 and the microcontroller U2. The reset subcircuit 920 interfaces the reset output signal RESET from the first PAL U1 and the reset input signal RST751 of the microcontroller U2 so that if the RESET line is logic 1, the RST751 line In logic 1, the microcontroller U2 is reset.

The first PAL U1 resets the microcontroller U2 in response to the CPU 40 writing logic 1 to bit 0 of the control port OEDH. Writing logic 1 to bit 0 of control port OEDH causes the RES D line to be logic 1 by the first PAL (U1), thereby causing the RST751 line to be logic 1, thereby resetting the microcontroller U2. . The CPU 40 clears the reset request by writing logic 0 to bit 0 of the control port OEDH.

In addition, the reset subcircuit is generated after the AUX5 voltage drops while the brownout or blackout of the AC source to the power source 17 occurs, as shown in FIG. 6C. Each time the voltage of the AUX5 signal rises by a given amount, reset the microcontroller U2 by making the RST751 line logic 1.

Philips, manufacturer of the 83C750, uses a simple RC to prevent reset problems.

Although the use of the circuit is suggested, a simple RC circuit can cause the 83C750 to latch up during a power supply brownout. In the specific configuration of FIG. 6A, when the AUX5 voltage rises by a threshold amount within a time period greater than the time constant determined by R4, R16, and C1, the RST751 line goes through the time period determined by R17 and C8. It becomes logic 1 (the microcontroller U2 is reset by this). In the preferred embodiment shown in Figure 6A, the threshold is approximately 1.5 VDC.

Referring now to FIG. 6C, the waveform of the reset circuit 920 is shown for the time period during which AUX5 rises and the time period during which brown out occurs as AC power is applied to the power source 17. . Before t0, the supply does not generate AUX5, and VBAT is approximately 3.3V, so Q3 is conductive and the RST751 line is grounded. At t0, the power supply starts generating AUX5, and the voltage starts rising at a rate based on the load and capacity in the power supply affecting AUX5. Node 1, a note between C1 and R4, is capacitively coupled with AUX5, so node 1 is raised as the AUX5 rises.

At t1, node 1 reaches approximately 1.5V, which is enough voltage to trigger Q2, so that Q2 is conductive and node 2 is grounded. At t2, as Note 2 passes 2.5V, Q3 stops conducting, and the RST751 line jumps to RUX5's level via R18 and rises with AUX5 to approximately 5V. When the RST751 line becomes approximately 3V, the microcontroller U2 is reset.

At t3, as AUX5 stops rising, node 1 also stops rising and begins to discharge to ground (the RESET line of the first PAL (U1) is low) at a rate determined by C1 and R4. At t4, when note 1 passes approximately 1.5V, Q2 stops conduction and note 2 charges at the rate determined by C8 and R17. At t5, when note 2 passes approximately 2.5V, Q3 is conductive and the RST751 line is grounded. Thus, a reset on power-on is completed and the system is typically in a state where AUX5 is 5V, VBAT is 3.3V, Node 1 is ground, and Node 2 is VBAT.

At t6, brown out is started at the AUX5 line, and AUX5 discharges. Node 1 capacitively coupled to AUX5 attempts to follow AUX5, but fails to follow, because the diode in the first PAL (U1) prevents node 1 from getting much lower than -0.5V. At t7, AUX5 is the lowest point and starts rising again. Node 1 is also raised following AUX5. At t8, node 1 reaches approximately 1.5V, which is enough voltage to trigger Q2, so that Q2 is conductive and note 2 is grounded. At t9, when Note 2 passes 2.5V, Q3 stops conduction, and the RST751 line jumps to RUX5 level via R18 and rises with AUX5 to approximately 5V. When the RST751 line becomes approximately 3V, the microcontroller U2 is reset.

At t10, AUX5 stops rising, so note 1 also stops rising and begins to discharge to ground [RESET line of first PAL (U1) is low] at the rate determined by C1 and C4. When approximately 1.5V passes, Q2 stops conducting, and node 2 charges at the rate determined by C8 and R17. At t12, when node 2 passes approximately 2.5V, Q8 is conductive and the RST751 line is grounded. Thus, the brownout-induced reset cycle due to brown out is completed. During this particular brown out node 1 will not rise above 3V, so if note 1 is connected to the RST751 pin, node 1 will not reset the microcontroller. However, the voltage of AUX5 is lowered below 4V, and this voltage will be sufficient to enter the microcontroller U2 into an undefined state.

The threshold for triggering the reset is limited to a reference value, and therefore, to raise or lower the threshold voltage, the reference value (VBAT in this case) must be raised or lowered respectively. This reset circuit provides the advantage of increased reset protection for the microcontroller U2, while being very inexpensive and virtually consuming no power while not resetting the microcontroller U2.

Referring back to FIG. 6A, microcontroller U2 is interfaced to CPU 40 via first PAL U1 and has a number of input, output, and internally controllable functions.

The SWITCH signal is input at pin 8 (P0.0) and represents the current state of pushbutton 21. The push button 21 is normally open. While the pushbutton 21 is open, the SWITCH line goes to logic 0 (ground) across the resistor R1. When pushbutton 21 is pressed, it causes a closure event, which causes the SWITCH line to be logic 1 via resistor R13. Capacity C6 acts to debounce switch closure events. Any subsequent debounce of the closing event of the switch 21 may be performed by reading the switch a predetermined number of times, for example 50 times, and ascertaining that the switch line is the same for all such readings, as is well known to those skilled in the art. It is performed in the controller U2.

The regulation of the power source 17 can be controlled directly by the microcontroller U2.

As shown in FIG. 6A, the ON signal is output at pin 5 (P3.0) and wired OR with the signal in SWITCH via resistor R6 to provide the ON # signal of the power supply. To control.

If the ON signal is logic 1, MOSFET Q1 will conduct and lead to the ON # line (pin 2 of JP2), thereby causing the power supply 17 to regulate power to the system via the ± 5 VDC and ± 12 VDC lines. Provide it. On the other hand, MOSFET Q1, where the ON line is logic 0, is not conducting, so the ON # line (pin 2 of JP2) is led to logic 1 by resistor R7, causing power supply 17 to have ± 5 VDC and ± Stop providing regulated power to the system through the 12VDC line.

The state of the ON line is in response to the closing event of the switch 21 and also in response to the CPU 40 via a writable register bit in the microcontroller U2 which can be written by the CPU 40. Is controlled. Microcontroller U2 is powered by AUX5, so microcontroller U2 is always powered to execute code and control the system. If the power source 17 does not provide regulating power to the system via the ± 5VDC and ± 12VDC lines, and (i) the switch 21 is pressed or (ii) one of the external events occurs, then the microcontroller (U2) Asserts an ON signal, which causes power supply 17 to provide regulated power to the system via the ± 5 VDC and ± 12 VDC lines. The microcontroller continues to apply an ON signal after the switch 21 is released.

As a backup system, the power supply 17 can also be turned on under the direct control of the user via the pushbutton 21. This option will typically only be used if the microcontroller U2 does not function as expected, as evidenced by a system that is not powered up in response to the press of the power button 21. As shown in FIG. 6A, the switch 21 also controls the ON # line of the power supply 17 through the diode CR2, the MOSFET Q1, the resistor R7 and the connection JP2. Typically, pushbutton 21 is open, MOSFET Q1 is not conductive, so ON # line (pin 2 of JP2) is led to logic 1 (AUX5) by resistor R7, and power supply 17 Does not provide regulated power through the ± 5VDC and ± 12VDC lines. When pushbutton 21 remains pressed by the user, SWITCH line is led to logic 1, MOSFET Q1 conducts to lead ON # line (pin 2 of JP2) to logic 0 (ground), thereby Power source 17 begins to provide regulated power over the ± 5VDC and ± 12VDC lines. With the button 21 held down, after the system is powered up, the BIOS causes the CPU 40 to test whether the microcontroller U2 is still functioning. If it is determined that the microcontroller U2 is not functioning, the CPU 40 resets the microcontroller U2, and after the microcontroller U2 is reset, the switch 21 is kept pressed. Is detected. As a result, with the button 21 kept pressed, the microcontroller applies the ON signal, and the user can now recognize that the microcontroller is controlling the power source 17 and eventually release the switch 21. . In order to use this backup option, the user must press the button 21 for a period of approximately 2 seconds after the logo appears.

The microcontroller U2 turns off the system only in response to (i) the switch 21 being pressed or (ii) the CPU 40 instructing the microcontroller to turn off the system.

These events are the same for the microcontroller, because the microcontroller allows the switch press to be triggered either by the closing event of the switch 21 or by the CPU 40 (ie, hardware button press / release). / release) is actually treated the same as software button press / release.

The microcontroller U2 only stops the system without a command by the CPU when the stop enable flag in the microcontroller U2 is cleared. In this case, if the system is powered up and the suspend enable flag is cleared, in response to the close event of the switch 21, the microcontroller U2 clears the ON signal, so that the power supply 17 is ± 5 VDC. And stop providing regulating power through the ± 12VDC line. The ON signal remains clear after the switch 21 is released.

When a command is issued after the system state has been successfully stored (hanged) on the hard disk drive, the microcontroller U2 also turns off the system in response to the command by the CPU. In response to this command, microcontroller U2 clears the ON signal, thereby stopping the power supply 17 from providing regulating power over the ± 5 VDC and ± 12 VDC lines.

In addition, the microcontroller U2 can also detect when an external event occurs and affect the system. The EXT_RING signal is input at pin 7 (P0.1), allowing microcontroller U2 to detect a ring from powered external modem 902. As is known to those skilled in the art, a typical external modem supplies a ring signal that toggles to logic 1 in the well-known RS-232C format when a ring signal is detected across the tip and ring telephone line. This signal is interfaced to the microcontroller U2 via the diode CR6, divided by the resistors R10 and R11, and finally input to the microcontroller U2 via the EXT_RING line. The toggle signal is sampled every 25 seconds and analyzed by microcontroller U2 to determine that a ring is present whenever this input is logical 1 for two consecutive samples.

In response to this condition being met, microcontroller U2 applies an ON signal, thereby causing power supply 17 to provide regulating power over the ± 5 VDC and ± 12 VDC lines. For the EXT_LRING signal to be used to detect incoming telephone calls, an external powered modem 902 must be provided.

Alternatively, another device that provides a binary signal in accordance with the RS-232 specification (or sufficiently close to apply the EXT_RING signal) may be interfaced to the EXT_RING line and may be used in systems such as motion sensors and buzzers. It is used to wake up systems such as burglar alarm sensors, voice activatecl sensors, light sensors, infrared light sensors and claDDer type sensors.

As shown in FIGS. 6A and 6B, the present embodiment also provides a ringing signal from the built-in modem 900 that includes an optosolator OPTO1 based on a ring-detection circuit. Means for detecting. Many suitable optical insulators, for example manufactured by Hewlett-Packard, Inc., are readily available from a number of sources. The internal modem 900 may be designed within the circuitry of the system planer 20 or placed in one of the expansion slots 78. In the latter case, the modem 900 should be modified to provide a Berg or similar connector to allow the signal from the opto-insulator OPT01 to be electrically connected to the circuit of the power management circuit of FIG. 6A. Many modem manufacturers modify their internal modems to provide connectors suitable for use with the circuitry of the present invention. The EXT_WAKEUP # signal is input at pin 4 (P0.2) of the microcontroller U2 and is used to input the signal from the ring detection optical insulator OPTO1 to the internal modem 900. This signal is interfaced via resistors R9 and R5, diode CR6 and capacitor C9 and finally input into microcontroller U2 via EXT WAKEUP # line.

The threshold and protection portion 905 of the internal modem 900 is connected to standard tip and ring telephone lines and, as is known to those skilled in the art of modem design, includes: (i) lightning and modem ( Protect from other electrical events that may damage 900, and (ii) set a ring threshold voltage.

The toggle signal from the optical insulator OPTO1 is detected and analyzed by the microcontroller U2, and a ring is present whenever three successive signal periods of the signal on the EXT_WAKEUP have a frequency between 15.1 Hz and 69.1 Hz. To judge. Unlike the EXT_RING signal circuit, which must be powered to provide a ring signal along the EXT_RING, the internal modem 900 needs to be powered by the opto-isolator OPT01 to supply the appropriate signal along the EXT_WAKEUP # line. None, the EXT_WAKEUP # line is normally driven by R5 to AUX5.

If the CPU 40 allows a system management interrupt (SMI) (the CPU 40 need not include SMI for a system useful to take advantage of the many benefits of the present invention), the microcontroller (U2). ) Can interrupt the CPU 40 via the system management interrupt (SMI) of the CPU. The SMI_OUT # signal is output from pin (3) (P3.2) of microcontroller U2, and microcontroller U2 can interrupt the CPU 40 immediately through this, so that the operating system enables this interrupt or Or you don't have to wait when you allow it. The state of the SMI_OUT # line can be recorded by the CPU 40 and located in the microcontroller U2. It can be controlled by a writable register bit and written by the CPU 40. Microcontroller U2 may also apply an SMI_OUT # signal, whereby (i) in response to activity detected on the ACTIVITY # line, or (ii) microcontroller U2 causes power source 17 to adjust the system. The CPU 40 may be interrupted before stopping providing power. Either or both of these events can be enabled and disabled by instructions from the CPU to the microcontroller U2.

Each SMI, microcode in CPU 40, stores the state of the CPU in a specific CPU state storage area to and from memory. The CPU 40 then executes an SMI interrupt handler, which performs the following functions. To recover the state of the CPU, the SMI interrupt handler issues an RSM (resume) instruction, causing the CPU 40 to recover its state from a particular storage area.

Before the CPU 40 causes the microcontroller U2 to interrupt the CPU 40 via the SMI of the CPU, the CPU 40 writes to a variable in the CMOS NVRAM indicating the reason for the SMI. This value in the CMOS NVRAM has an OOH value by default, which is interrupted before the microcontroller U2 causes the power supply 17 to stop providing regulated power. Indicates that the CPU 40 is asynchronously interrupting the CPU 40. After each SMI, the CPU 40 sets its variable in the CMOS NVRAM to OOH. In response to this value, the CPU 40 performs certain tasks under the assumption that the system is urgently powered down by the microcontroller U2. The CPU 40 may extend the time period before the microcontroller U2 powers down the system by periodically restarting the power down extend timer in the microcontroller U2.

During this time period before the system is powered down, the CPU 40 can perform a number of tasks. For example, since the user may have changed one or more parameters affecting the weather alarm, the CPU recalculates the weather wait minute value and writes it to the microcontroller U2. In addition, the CPU writes predetermined information to be written to the hard drive 31 in the CMOS NVRAM in the order, such as the time period in which the computer system has been operating since it was last powered on.

Another value recorded by the CPU 40 is O1H, which indicates that the CPU 40 will jump from the reference number 254 to the Suspend Routine, and the CPU 40 returns the resume routine (at the reference number 454). O2H indicating jump to Resume Routine and OFFH indicating CPU 40 will set up a special CPU state save area in the segment EOOOH data structure.

In a preferred embodiment, the microcontroller provides control regarding the display 11 being blank. The DISP_BLANK signal is output via pin 1 (P3.4) of microcontroller U2, and directly controls the blanking of display 11. Two inverters (U3D and U3E) interface the DISP_BLANK signal with the ESYNC # and BLANK # lines. With the ESYNC # and BLANK # lines at logic 1, video controller 56 generates a video signal. If BLANK # and ESYNC # are logical 0 (ground), video controller 56 stops generating video signals. The state of the DISP_BLANK line is written by the CPU 40 and controlled by a writeable register bit located in the microcontroller U2. The CPU 40 instructs the microcontroller U2 to enter the display in a blank state when the system enters the standby state 152. In addition, the DISP_BLANK line is sequentially set, and then cleared in response to the closing event of the switch 21. Similarly, activity in any one of the activity interrupts INT1 and INT12 in this case causes the microcontroller to clear (CLEAR) the DISP_BLANK line, allowing the video controller 56 to generate a video signal.

The microcontroller U2 also controls the frequency of the clock signal generated by the clock synthesizer 906. Three Berg-type jumpers (not shown) (JP0, JP1 and JP2) control the clock synthesizer as follows. That is, if JP0 = 0, JP1 = 1 and JP2 = 0, the clock synthesizer generates a 33 MHz clock signal, and if JP0 = 1, JP1 = 1 and JP2 = 0, the clock synthesizer generates a 25 MHz clock signal, If JP0 = 0, JP1 = 1 and JP2 = 1, the clock synthesizer generates an 8 MHz clock signal. Clock synthesizer 906 is also controlled by three clock lines CLK0, CLK1 and CLK2 corresponding to JP0, JP1 and JP2. As shown in FIG. 6A, these clock lines CLK0, CLK1 and CLK2 are controlled by the microcontroller U2 via the CLK_SLOW # signal output from pin 2 (P3.3) of the microcontroller U2. Controlled. As shown, the CLK_SLOW # signal is doubly iuverted by open collector outputs U3A, U3B and U3C. In addition, resistors R15 and R8 are pullup resistors used to drive the CLK0 input to U3A's open collector output and clock synthesizer 906 to logic 1, respectively.

Three clock signals CLK0, CLK1 and CLK2 and three jumpers JPO, JP1 and JP2 control the clock synthesizer as follows. That is, if CLK_SLOW # is logic 1, the CLK1 and CLK2 signals are also logic 1, and consequently, clock synthesizer 906 is controlled by jumpers JP1 and JP2 and is higher 25 MHz or 33 MHz for use by the system. Generates a clock signal. On the other hand, if the clock CLK_SLOW # signal is logical 0, the CLK1 and CLK2 signals are also logical 0, and as a result, the clock synthesizer 906 generates a lower 8 MHz signal for use by the system, causing the system to lose power. Try to consume less. As shown in FIG. 6A, the berg jumper separates the CLK_SLOW # line from the CLK0 line. When the jumper is in place, the CLKO line follows the CLK_SLOW # signal. On the other hand, if the jumper is not in place, the CLKO line remains drawn to logic 1 by resistor R8 regardless of the state of the CLK_SLOW # signal. The state of the CLK_SLOW # line is controlled by a writeable register bit that can be written by the CPU 40 and located in the microcontroller U2. In addition, the CLK_SLOW # line may be cleared by the microcontroller U2 in response to activity on the ACTIVITY # line. As will be apparent to those skilled in the art, other clock synthesizers may be used in the present invention, and the interconnection between the microcontroller U2 and the clock synthesizer may need to be changed to match the specific specifications of the particular synthesizer used. have.

In addition, the microcontroller U2 directly controls the illumination of the power / feedback LED 23. The LED CNTRL signal is output at pin 22 (P3.6), allowing direct control of power / feedback LED 23 by microcontroller U2. Resistors R2 and R3 and diodes CR4 and CR5 allow power / feedback LEDs 23 to be driven by AUX5 power lines or VCC power lines in response to LED_CNTRL lines of logic zero. If the LED_CNTRL line is logic 1, the power / feedback LED 23 is not illuminated. As will be described in more detail below, the state of the LED-CNTRL line is in response to the closing event of the switch 21, in response to a weather alarm, or in response to one or more rings at the ring detection input, or the system is in standby mode. Is controlled by the microcontroller U2 in response to being placed into the.

The microcontroller U2 can control the LED 23 as a simple power LED. In this way, the LED 23 illuminates after the closing event of the switch 21 changing the system from the off state 156 or the stop state 154 to the normal operating state 150. Similarly, the microcontroller U2 turns off the LED 23 after the release of the switch 21 which changes the system from the normal operating state 150 to the suspended state 154 or the off state 156.

In addition, the LED 23 may be selectively flashed by the microcontroller U2 at a specific speed, eg every second, to indicate that the system is in standby state 152. In addition, the LED 23 is selectively flashed by the microcontroller U2 at different speeds, eg every 1/2 second, to indicate that the system has been started by a ring or an alarm and the system is in the off or stopped state. can do. Alternatively, during the paused state, the LEDs 23 are selectively flashed in groups by the microcontroller U2 to indicate the number of times the system has been powered up by external events such as rings, alarms, and the end of the inactivity stop timer. It can also display the number of times the power down again. In this case, one or more functions are provided in the BIOS to allow the OS and applications to modify the number of times microcontroller U2 will flash the LEDs 23. For example, if the system wakes up by the ring and an incoming fax transmission is received, the communication application can invoke a specific BIOS function to add one flash to the flash count. Thereafter, the BIOS causes the CPU 40 to write the new flash value to the microcontroller U2, and then the LED 23 to flash the indicated number of times.

The POWERGOOD signal is input at pin 4 (P3.1) of microcontroller U2, and allows microcontroller U2 and CPU 40 to use this signal. In particular, the microcontroller uses the POWERGOOD signal to implement a feedback-based fault detection and correction circuit to determine whether there is a fault in the power supply 17 and to clear the faulty state. Let's do it. As described elsewhere herein, the ON signal has been applied for a certain period of time (eg, 3 seconds), and the POWERGOOD signal indicates that the power source 17 is not providing an appropriate level of regulated voltage. If the logic is 0, the microcontroller U2 assumes that the power supply 17 has failed, for example, due to an overcurrent condition. As a result, in order to as far as possible clear the state that caused the failure, the microcontroller U2 stops applying the ON signal for a certain period of time (eg 5 seconds) so that the failure can be cleared. The microcontroller U2 then reapplies the ON signal and waits until the POWERGOOD signal is a logic 1 indicating that the power source 17 is now providing regulating power to the system. Without a fault detection and correction circuit based on this feedback, the power supply 17 will remain faulted and the microcontroller U2 will continue to apply an ON signal to allow the power supply 17 to begin generating regulated power. will be. The only solution would be to remove AC power from the power source to clear the fault.

6D, an alternative embodiment of a power failure detection and correction circuit is shown. This embodiment uses four FETs Q10-Q13, resistors R20-R23, capacitors C20, and 74HC132 to detect when the power supply 17 has failed and clear the failure. Q12 leads the ON signal to LOW during the time period determined by R22 and C20. When the ON signal is HIGH, power is supplied to AUX5, and VCC is below the threshold to trigger Q11, thereby causing an in-power fault condition. Clear

The ACTIVITY # signal is input at pin 19 (INT1) of microcontroller U2 and used by microcontroller U2 to respond to activity in keyboard 12 and mouse 13.

IRQ1 is a keyboard hardware interrupt signal, which is input at pins 8 and 17 of the first PAL U1, and when the key on the keyboard 12 is pressed, the IRQ1 signal is pulsed. IRQ12 is a mouse hardware interrupt signal, which is input from pins 11 and 19 of the first PAL U1, and when the button of the mouse 13 is pressed, the IRQ12 signal is pulsed. The IRQ1 and IRQ12 signals are logically ORed in the first PAL U1 and are output as ACTIVITY # signals. The ACTIVITY # signal is used to ensure that the microcontroller U2 never misses keyboard 12 or mouse 13 activity.

During the standby state, activity on the keyboard or mouse interrupts causes the microcontroller to immediately restore the video display. In this way, interrupts IRQ1 and IRQ12 are used to provide the user with immediate feedback in the form of a recovered video display upon return from standby state 152 to normal operation state 154. If not using this approach, as described with reference to FIG. 9, the user will not receive feedback until several minutes have elapsed until the APM checks for user activity.

Communication between the CPU 40 and the microcontroller U2 is input from pin 18 (I / 06) of the first PAL U1 (pin 13 (I / 03) of the first PAL U1). Of the microcontroller U2 and the SD (0) inputted to the microcontroller U2 via the RWD (0) line outputted from the microcontroller U2 and input from pin 13 (P1.0) of the microcontroller U2. SD (1) input from pin 14 (P1.1), SD (2) input from pin 15 (P1.2) of microcontroller U2, and pin of microcontroller U2 ( 16 (SD) input at (P1.3), SD (4) output at pins 6 (15) of the first PAL (U1), and pin 18 (of microcontroller U2) ( This is done using IO_STROBE # input from INTO) and PROC-RDY output from pin 20 (P1.7) of microcontroller U2. The first PAL (U1) and microcontroller U2 are (i) microcontroller U2 from CPU 40 along SD (0), SD (1), SD (2) and SD (3) via RDWO. 4-bit parallel write (one address is essentially a 1-bit write to reset microcontroller U2) and the other address is written to microcontroller U2, which is only valid when data bit SD (4) is HIGH. Serial (1 bit) read from the microcontroller U2 by the CPU 40 along the nibble to be read and (ii) SD (0) via RDW (0) (one address is a status bit And other addresses are configured and programmed to provide data bits from microcontroller U2).

Referring to FIG. 19, various routines are shown executed on microcontroller U2 starting from reference numeral 1160. Microcontroller U2 typically executes one of two main routines, one of the power-on routine of tasks 1168 through 1216 or the power-off routine of tasks 1260 through 1308. The power-on routine provides a microcontroller when the power supply 17 provides regulated power at ± 5 and ± 12 lines or the power supply 17 does not provide regulated power at ± 5 and ± 12 lines but the system is in a power-on process. It is executed by the controller U2. The power-off routine is not used when the power supply 17 provides regulated power at ± 5 and ± 12 lines or when the power supply 17 provides regulated power at ± 5 and ± 12 tines but the system is in the power off process. It is executed by the controller U2. In addition, three interrupt-driven routines, i.e., routines 1220 through 1232 in communication with the CPU 40, routines 1236 through 1244 that detect activity of the mouse 13 or keyboard 12; ) And routines (1248 to 1256) that provide a time-base with resolutions of 25 milliseconds, 1/2 second, 1 second, and 1 minute.

First, microcontroller U2 is initialized in task 1164, during which all variables are initialized, counter variables are initialized, timer interrupts are initialized and enabled, and external interrupts that control communication routines and activity routines. Is initialized.

The communication routine is an interrupt drive routine initiated at task 1220, which is executed in response to the IO_STRORE line becoming logical 0 by the first PAL U1, which is executed by the CPU 40 by a command or query. Indicates that it starts.

In summary, this routine receives one or more nibble commmand or query from CPU 40 at task 1224 and implements and / or responds to the command at task 1228. The program execution control is returned to the code that was interrupted at task 1232.

The microcontroller sequentially receives nibbles that form a command or query from the CPU. After receiving one nibble, the microcontroller sets the PROC-RDY to LOW. The microcontroller sets PROC_RDY high again when it is ready to receive the next nibble. The CPU 40 may record the next command nibble upon detecting that the PROC_RDY transitions from LOW to HIGH.

While the microcontroller U2 implements a command or query from the CPU 40, the microcontroller U2 cannot receive other commands, so the microcontroller U2 controls the ROC_RDY line to logic 0 to control the microcontroller. Indicates to CPU 40 that the next command / query is not yet acceptable (via reading of the status port). When the implementation is complete, the PROC_RDY line is applied to logic 1 indicating to the CPU 40 that the microcontroller U2 is ready to accept the next command / query (by reading the status port).

The activity routine is an interrupt-driven routine initiated at task 1236, which is executed in response to the ACTIVITY # line becoming logical 0 by the first PAL U1, which causes the user to move the mouse 13 or keyboard 12. It was used. In summary, in response to receiving an interrupt, the routine may (i) set a bit indicating that mouse 13 or keyboard 12 activity is present, and (ii) recover clock speed if clock deceleration is enabled. (iii) recover the screen 11 from the blank state if the blank state is enabled, (iv) restart the fail-safe timer, and (v) SMI to the CPU 40 if enabled in task 1240. Generates. The routine then returns to 1244 the program execution control to the code that was interrupted. The bits set by this routine are then queried by the supervisor routine at every APM get event, as described in detail elsewhere herein.

The timer routine is an interrupt drive routine that starts at task 1248 and is a 16-bit free-running counter configured to generate an interrupt every 25 milliseconds to provide a time base for microcontroller U2. Is executed in response to an internal timer interrupt based on the < RTI ID = 0.0 > The timer routine provides time bases such as 25 milliseconds, 1/2 second, 1 second and 1 minute. In summary, these routines receive interrupts, determine when various times occur, perform appropriate actions in task 1252, and return program execution control to interrupted code in task 1256.

Every minute (every 25 milliseconds), if the power supply does not provide regulated power and the microcontroller is configured to respond to the ring, the timer routine checks the RS-232 ring on the EXT_RING line to clear the bit if a ring occurs. Set it.

For every 1/2 second, either in the off state or in the stopped state, the timer routine turns on the LEDs 23 to implement an awake an external ring indicator flashing sequence, which is described in detail elsewhere herein. Determine if you need to toggle.

During every second standby state, the timer routine determines whether to toggle the LED 23 to implement the suspend indicator flashing sequence described in detail herein.

In addition, every second, the timer routine, if appropriate, decreases the failsafe timer, the APM failure stop timer, and the power failure timer, and sets the corresponding bit if any timer has expired. The failsafe timer is a 20-second timer that allows the microcontroller to turn off the system when the failsafe timer is turned off. The failsafe timer is often restarted (reset) by the supervisor routine in response to an APM acquisition event, so that the failsafe timer never expires as long as the code running on the CPU 40 is properly executed. However, if the code does not run properly, the fail-safe timer ends, and in response to pressing and releasing the power button 21, the microcontroller U2 returns to the power source 17 under the assumption that the BIOS and other routines have failed. To stop providing regulating power at the ± 5 and ± 12 lines.

The APM fail-suspend timer is enabled when switch 21 is in the off / disable state (indicating that the user is about to turn off the system) and causes the system to terminate this timer (eg, a fail-safe timer). Is an 18-second timer that causes the microcontroller to turn off the system, by attempting to abort (before is terminated). As with the failsafe timer, the APM failure stop timer is often restarted by code running on the CPU 40, e.g., an APM acquisition event, so as long as the code running on the CPU 40 is properly executed, the APM failure stop timer. Never ends. However, if the code does not run properly, the APM failure stop timer expires.

When the APM failure stop timer expires, the microcontroller U2 sets one bit. This bit is checked during each timer rennell 0 interrupt, which occurs approximately every 55 milliseconds as is well known to those skilled in the art. The timer level 0 interrupt service routine also restarts the failsafe timer. If the timer remel 0 interrupt service routine detects that the APM failure stop timer has expired, it will attempt to stop the system by jumping to the stop routine as described with reference to FIG.

Suspension initiated by a timer level 0 interrupt service routine is not a preferred suspend method. Many applications and adapters are aware of APM and perform tasks in response to system hangs. Suspensions initiated by the timer level 0 interrupt service routine cannot use APM to indicate that a suspend is imminent for these APM aware entities. As a result, the system may be stopped without these individuals being properly prepared. In this way, the system state will be preserved by a stop initiated by a timer level 0 interrupt service routine and no data in memory will be lost, but the user may need to place the system in the proper state after the desired data has been stored. have.

In particular, the APM failure stop timer is useful for patching holes in the APM driver of the OS. For example, when a Microsoft Windows 3.1 modal dialog box is displayed, the Windows APM driver stops generating APM acquisition events. As a result, if the mode interactive box is displayed when the user presses the power button 21 to stop the system, the system will not be stopped. The microcontroller U2 will notify that the switch is in the off / off state, but the supervisor routine will not be called because all APM acquisition events have been aborted. The switch press will not work until the mode interactive box is cleared by the user. However, once the APM failure stop timer expires and the end of the timer is detected by the timer level 0 interrupt service routine, the system state will be kept to the extent possible without indicating to the APM aware entity that the system is being stopped.

Every minute, the timer routine decrements the wake wait minute alarm timer and the activity timer. If the wake up timer is enabled, when this wake up timer expires, the microcontroller causes the power supply 17 to begin providing regulating power at the ± 5 and ± 12 lines.

After microcontroller U2 is initialized, power is tested at task 1168 to determine if the power is off. If the power is still present, microcontroller U2 checks at task 1172 whether power supply 17 has failed. The power source 17 includes several internal protection devices that cause a shutdown or fault. The microcontroller U2 determines whether the power supply 17 has failed as follows. That is, the microcontroller is in operation (while power is being supplied to AUX5, that is, AC power is being supplied to the power supply 17), and the microcontroller U2 applies the ON signal to cause the power supply 17 to have ± 5. And provide regulated power at ± 12 lines, and if the POWERGOOD line is not applied (unless power source 17 provides regulated power at ± 5 and ± 12 lines), power source 17 will fail and reset Should be.

In task 1172, power source 17 is actually tested twice. The microcontroller U2 waits for 3 seconds after applying the ON signal as measured by the internal time base. If the POWERGOOD signal is not applied after ON is applied for 3 seconds, the microcontroller U2 clears the ON signal and waits for another 5 seconds. Microcontroller U2 then applies the ON signal again and waits for another 3 seconds. If the POWERGOOD signal is not applied after ON is applied for 3 seconds, the microcontroller U2 clears the ON signal and determines that the power supply 17 has failed.

If the power source fails, microprocessor U2 jumps to a power off routine as indicated at task 1174. On the other hand, if the power supply does not fail or is off, the microcontroller causes the power supply 17 to begin providing regulating power at ± 5 and ± 12 at task 1175 and input / output at task 1176. Initializes the port, turns on LED 23 and enables external interrupts.

7 shows a switch state machine held in microcontroller U2. As shown in the figure, the state changes in response to other events such as the closing event of the switch 21 and the resetting of the computer system 10 and is recorded by the CPU 40. If AUX5 is not powered by the power source 17, the microcontroller U2 is not powered, so the switch state 174 is meaningless. When the switch 21 is pressed, the telephone ring from either source, the wake up of the minute alarm timer, and the command from the CPU 40 are detected, the microcontroller is configured as described with reference to FIG. 17) to start providing system power.

As shown in FIG. 7, the switch 21 has four states that are monitored by the microcontroller U2, i.e. on / push state 176 (the user is pressing the button and is about to turn on the machine and ), (Ii) on / off state (178) (user releases button and is about to turn on machine), (iii) off / press state (180) (user presses button and turns machine on) State to be turned off) and (iv) off / release state 182 (the user has released the button and is about to turn off the machine). In the next task 1180, microcontroller U2 tasks whether the switch is in the off / off state, which indicates that the user has released the button and is about to turn off the machine.

When state 174 and switch 21 are pressed, microcontroller U2 enters on / push switch state 176. Release of switch 21 causes microcontroller U2 to enter on / off switch state 178. Similarly, when microcontroller U2 is reset, microcontroller U2 enters on / off state 178. Pressing the switch 21 again causes the microcontroller U2 to enter the off / push switch state 180. Releasing switch 21 again causes microcontroller U2 to enter off / release switch state 182. Subsequent closing of switch 21 causes microcontroller U2 to cycle through four states as shown in FIG. When computer system 10 is in a normal operating state 150, microcontroller U2 is in an on / off switch state 178.

The application will run during this state. System 10 may enter standby state 152 and exit standby state 152 in this state. This state also corresponds to a user-generated suspend about request.

The off / release switch state is a switch state corresponding to a stop request by a user.

That is, starting with the system in the off state 156, pressing and releasing the switch 21 once puts the computer system into a normal operating state 150. Pressing and releasing the switch 21 again generates a stop request, which is read by the supervision routine discussed in detail with reference to FIG. Prior to system 10 being in suspend state 154, pressing and releasing switch 21 a third time results in a suspend about request that is read by the suspend routine.

Referring back to FIG. 19, if the user releases the button and is about to turn off the machine, microcontroller U2 jumps to the power off routine as indicated in task 1184.

On the other hand, if the user is pressing the button and indicating an off / push indicating that he is about to turn off the machine, the microcontroller tests at task 1192 whether the switch has been masked by the BIOS. The BIOS once masks the switch 21 upon entering the standby state, thereby preventing the switch press from forcing the system from the standby state to the suspended state, thereby preventing user confusion as described elsewhere herein.

If the switch 21 is masked by the BIOS, the microcontroller code jumps back to task 1176 to clear the mask bit so that the next switch press causes the system to enter the off or stop state. Allow. On the other hand, if the switch 21 is not masked or if the switch 21 does not exist in the off / push state, the microcontroller starts a heartbeat routine at task 1196.

The hard bit routine is used to indicate to the CPU 40 that the microcontroller U2 is functioning properly. The CMD-STATE # line output (pin 17, p1.4) of the microcontroller is typically logic one. Microcontroller U2 drives this line to logic 0 for approximately 1.5 seconds and then back to logic 1 every 50-60 microseconds. Since the power management status port read by the CPU 40 is the logical AND of the CMD_STATE # line and the PROC_RDY line, this high to low transition is monitored very often by the CPU 40, for example when the system boots. It is possible to ensure that the microcontroller U2 is functioning properly.

Next, the microcontroller U2 tests whether the BIOS commanded a power-off at task 1200. The CPU 40 can access and change virtually all variables in the microcontroller U2. If the BIOS has set a variable indicating that the system should be powered off, for example after the state of the system has been written to the hard drive 31 during the shutdown, the microcontroller U2 will power off as indicated in task 1204. You will jump to the routine.

On the other hand, if the BIOS did not command a power off, the microcontroller executes a failsafe routine at task 1208. The failsafe timer is a 20 second timer that is enabled when the power supply 17 is supplying regulating power on the ± 5 and ± 12 lines. This routine checks whether the failsafe timer has expired and sets one bit when it has finished. This routine also restarts the failsafe timer when instructed to restart by the BIOS.

Next, at task 1212, in order to synchronize the microcontroller and the power supply 17 as a safety measure, the microcontroller checks the POWER_GOOD line so that the power supply 17 continues to regulate power at ± 5 and ± 12 lines. Detect whether or not to supply.

If the power supply 17 is not supplying regulating power at the ± 5 and ± 12 lines, the microcontroller U2 jumps to the poweroff routine as indicated in task 1216. On the other hand, if the power supply 17 is supplying regulating power on the ± 5 and ± 12 lines, the microcontroller code jumps back to task 1180 to continue execution.

The power off routine begins at task 1260. First, microcontroller U2 disables the activity interrupt at task 1264 to cause the display to be blank.

Next, at task 1286, the microcontroller checks the POWER_GOOD line to detect whether the power supply 17 continues to provide regulating power at the ± 5 and ± 12 lines. If the power source 17 is providing regulating power at the ± 5 and ± 12 lines, then the microcontroller U2 may determine whether the display should be blanked at task 1272 and / or whether the LED 23 should be turned off. Test The display must be blanked and / or turned off. Microcontroller U2 causes video controller 56 to stop generating video signals and / or turn off LED 23.

Then, or if the LED and display should not be blanked, the microcontroller next (i) whether the BIOS commanded the system to be turned back on by setting one bit, and (ii) the user pressed the power button. Test whether the system is commanded to be turned on again by pressing (21). If either of these has occurred, the system must be powered up again and microcontroller U2 jumps to a power-on routine as indicated by task 1284.

Next, the microcontroller determines whether the ring is ringed on the EXT_WAKEUP # line from the optical insulator OPTO1. For the RS-232 line, this only checks if the EXT_RING line is high. In the case of the signal from the optical insulator OPTO1, it is further checked by the microcontroller U2. The EXT_WAKEUP # line is typically drawn high by resistor R5. The opto-isolator OPT01 pulls this line low when the voltage across the tip and ring is higher than the threshold voltage set by the threshold and protector 905, for example 60 V when the telephone line rings. . However, this condition can also be met when the telephone line is tested or from noise on the line. Thus, just waiting for the EXT_WAKEUP # line to go low may cause the wrong ring to wake up the system.

As a result, the microcontroller measures the frequency of the ring to determine whether the signal is a ring. In-standard rings are signals between 16 Hz and 58 Hz. Microcontroller U2 measures three time periods between the four rising edges of the EXT_WAKEUP # signal and if all three time periods correspond to frequencies between 15.1 Hz and 69.1 Hz, an appropriate ring occurs on the EXT_WAKEUP # line. The corresponding bit is set by thinking that it is done.

The check routine starts when a low is detected on the EXT_WAKEUP # line. If the EXT_WAKEUP # line is low for three consecutive reads, the microcontroller U2 waits for the line to return high for three consecutive reads. Immediately thereafter, a 16-bit counter that forms the base for the timer interrupt is read and its value stored, and microcontroller U2 waits for this line to transition low for three consecutive reads. Next, the microcontroller tests whether the time between the first two rising edges is between 15 milliseconds and 66 milliseconds (indicating that the signal is between 15.1 Hz and 69.1 Hz). If the time is between 15 milliseconds and 66 milliseconds, the high resolution counter is resampled and the microcontroller calculates the difference between these two counter samples as it waits for the next low to high transition. This process is repeated during the transition from the next two rows to high on the EXT_WAKEUP # line. If all three time periods are within range, the microcontroller U2 determines that the appropriate ring has occurred on the EXT_WAKEUP # line and sets the corresponding bit. If no row exists on the EXT_WAKEUP # line, or if any of the time periods are out of range, the microcontroller code continues without setting the bit.

Next, at task 1286, the microcontroller tests whether the ring is present or whether the wake up alarm timer has expired. In the case of an RS-232 ring, optoisolator ring, or meteorological atmospheric alarm, this test includes testing whether the microcontroller U2 sets the associated bits.

If a ring is present or the wake up alarm timer has expired, the system must be powered on again and microcontroller U2 jumps to a power-on routine as indicated in task 1287.

Then, at task 1288, the microcontroller determines whether the power source 17 is providing regulating power at the ± 5 and ± 12 lines. If no power is being provided, the code jumps back to task 1280 to resume the loop. On the other hand, if the power supply 17 is providing regulating power at the ± 5 and ± 12 lines, the microcontroller U2 executes the hardbit routine in task 1292 and the failsafe routine in task 1296. do. These two routines have been discussed with reference to tasks 1196 and 1208.

The microcontroller U2 may only (i) command an immediate power off, in which the BIOS is implemented in the communication routine, (ii) the fail-safe timer expires, or (iii) the user presses the power button, and the microcontroller U2 Stops providing regulated power on ± 5 and ± 12 lines only under three conditions where the stop enable flag is not set (this is the condition that the microcontroller U2 tests each time the SWITCH input is read). Let's do it. Therefore, the microcontroller tests whether the failsafe timer has expired in the task 1300. If the failsafe timer has not expired, the code jumps to task 1280 to resume the loop.

On the other hand, if the failsafe timer expires to indicate that the system should be powered down, microcontroller U2 generates SMI (if enabled) to CPU 40 at task 1304. This allows the CPU to perform certain tasks under the assumption that the system will power off immediately. For example, the CPU 40 records the updated wake wait value alarm value in the microcontroller U2.

If no further action is taken by the CPU 40, the microcontroller powers off the system after the programmable SMI timer expires. The CPU 40 can extend this time period by restarting the SMI timer by writing an appropriate value to the microcontroller U2.

The microcontroller U2 then powers down the system at task 1308, if the test at task 1268 also indicates that the power source is not supplying good power. This includes (i) stopping the power supply 17 from supplying regulated power on the ± 5 and ± 12 lines, (ii) disabling the communication interrupt since the CPU 40 will lose power, ( iii) setting the output ports (except ON) high to minimize their power consumption (SWITCH, EXT_RING, EXT_WAKEUP, etc. can still be read by microcontroller U2 in this mode), (iv) The rest of the routine includes setting the power off variable to recognize that power to the system is off and (v) changing the switch state to off / off so that the next switch press turns the system back on.

The code then jumps back to task 1280 to resume the loop while simultaneously waiting for a ring or switch press, or for instructing the BIOS to wake up the system, or for the wake up alarm timer to expire.

System Software A hardware aspect of the computer system 10 of the present invention has been described and the code aspect will now be described.

Referring now to FIG. 8, a schematic of the power up routine is shown. This routine is initiated in task 200 when the CPU jumps to the code indicated by the Reset Vector and executes this code. This case occurs whenever the CPU is powered up, the CPU is reset by a reset hardware signal, or the reset instruction is executed by jumping to the code indicated by the reset vector. Such reset procedures are well known in the art.

First of all, the flow of the power-up routine depends on why the machine is powered up. As described in more detail with reference to FIG. 11, the system 10 may have been powered up by brown out or black out. In this case, it would be inappropriate to allow the system to stay on. Thus, the power-up routine first determines at task 940 whether the system should remain on. If the system has been improperly powered up, CPU 40 instructs microcontroller U2 at task 942 to stop the power supply from supplying regulated power to the system.

One test performed to determine whether the system will maintain power is to verify that the telephone line is ringing if the system is powered up when the microcontroller determines that it is a ring. In particular, if the system wakes up in response to the ring after the system is powered up, the CPU 40 (now fully powered on) may wait while the system waits for the hard disk in the hard drive 31 to spin. Or 902 to determine whether to detect a ring signal as well. Otherwise, the system is powered down. If the modem 900 or 902 also detects a ring signal, the system must maintain power and the booting process will continue.

Assuming the system should maintain power, the flow of the power-up routine typically depends on whether the system is in an off state 156 or a suspended state 154. That is, it depends on whether the stop flag is cleared or set in the CMOS NVRAM 96. As shown in task 202, system 10 determines whether the system is in an off state 156 or a suspended state 154 by reading the suspend flag from nonvolatile CMOS memory 96. As the system exits the normal operating state 150 and enters the off state 156 or suspend state 154, each routine sets or clears a suspend flag in the NVRAM 96. If the suspend flag is set in NVRAM 96, computer system 10 is in suspend state 154, and the state of computer system 10 is stored in fixed disk storage 31. On the other hand, if the stop flag is cleared in the NVRAM 96, the computer system 10 is in an off state 156, and the state of the computer system 10 is not stored in the fixed disk storage device 31. Thus, if the suspend flag is set in NVRAM 96, the computer executes the normal boot routine shown in tasks 204-214. The first task is a power-on self-test (POST) as shown at 204 and will be described in more detail with reference to FIG. 11 and after returning from the POST, the CPU ( 40 calls a PBOOT routine to load the operating system as shown at 206.

The PBOOT routines are a slight variation of the typical routines that run on IBM PS / 2 computers, which will be explained later. The PBOOT determines the boot location (either from the hard drive 31 or from a disk in the floppy drive 27), loads the operating system (OS), and changes the system as indicated by the CONFIG.SYS file. After analyzing and implementing the changes, ultimately run the AUTOEXEC.BAT batch file before returning control to the operating system. PBOOT routines are well known in the art. The OS loads the APM device driver, which asks the BIOS if the BIOS recognizes APM. If aware, these BIOS APM routines and OS APM routines cooperate to provide the various features described herein after performing handshaking. The operating system executes the code directed by the user indefinitely as shown in task 210. However, as shown in task 212, when notifying the supervisor routine of the API, the APM BIOS and APM OS cause the supervisor routine to be executed in parallel with the executing program. That is, computer system 10 is a time-multiplexed multitasking system, and APM get-events and supervision routines are executed periodically. The end result is that the supervision routine is executed approximately every second. The supervision routine will be described in more detail with reference to FIG. As described with reference to FIG. 4, after the normal boot routines 204-210 have ended, the computer system 10 is in the normal operating state 150.

Referring back to task 202, if the stop flag is set in NVRAM 96, the system state is stored on hard drive 31, and system 10 boots as shown in tasks 214-220. Resume the routine. First, as shown in task 214, the system executes an abbreviated POST (POST). The shorter POST will be described in more detail with reference to FIG. After a short POST, the system calls the resume routine, as shown in task 216, which will be described in more detail with reference to FIG. At this point, the resume routine is sufficient only to restore the state of the computer system 10 back to the configuration it had before the system 10 was stopped. Unlike the normal boot routine shown in tasks 204-210, the resume boot routine must be running because the APM routine must have been running to halt this system and APM is loaded back into memory when the system state is restored. There is no need to inform the APM API routines of the existence of the supervision routine. Thus, when the resume routine has completed recovery of the system 10 state, as shown in tasks 212 and 220, the APM is executed in parallel with the code already located in memory and recovered. After completion of the resume boot routines 214-220, as described with reference to FIG. 4, the computer system 10 is in a normal operating state 150. Thus, after the normal boot routines 204-210 or resume boot routines 214-220 are executed, the computer system 10 is in the normal operating state 15.

9 shows a detailed flowchart of the supervision routine called by the APM approximately every second during an acquisition-event. Different operating systems will execute acquisition-events at different frequencies.

In FIG. 9, the supervision routine starts at task 222. The description below assumes that computer system 10 starts in a normal operating state 150. The first task is to test whether the user pressed the switch 21 in task 224. As described in detail with reference to FIGS. 6A and 7, the switch 21 is tested by the CPU 40 querying the microcontroller U2.

If the test at task 224 determines that the user has pressed the switch 21, the supervision routine determines at task 350 whether a suspend request was previously issued to the APM device driver in the OS. do.

If the test at task 950 determines that it has not already been sent to the stop APM driver, the supervisor routine issues a stop request to the OS APM driver at task 226 and returns to APM at task 228. In response to the SET Suspend Request APM Return Code, APM broadcasts that the suspension is imminent so that the APM-aware device can perform any necessary system tasks (such as synchronization of hard disks). And issue a stop command to cause the APM BIOS routing routine to call the stop routine. The stop routine will be described in more detail with reference to FIG. The stop routine essentially causes the system 10 to exit from the normal operating state 150 and enter the stop state 154 (if the system is not ready to stop), or after a number of instructions, or (the system stops) If resumed, control may return to the supervision routine in minutes, hours, days, weeks or years. The suspend routine always sets the Normal Suspend APM return code, whether returning without suspending or returning after full suspend and resume.

In task 224, in most cases the switch 21 has not been pressed and the supervisory routine moves to task 952 to determine if a Critical Suspend Flag is set. Similarly, if an abort request was previously sent to an APM driver in the OS, the supervisor routine moves to task 952 to determine if the threshold abort flag is set. If the threshold abort flag is set, then at task 954 the supervisor routine tests whether a critical abort request has previously occurred with the APM driver.

If a critical stop request has not been issued to the APM driver, the supervisor routine generates a threshold stop request APM return code at task 954 and then returns to the APM driver at task 958. In response to the critical suspend request, the APM driver stops the system immediately without broadcasting that the suspend is imminent, and thus the APM-aware device is unable to perform their respective pre-suspend taks.

If the threshold stop flag is not set in task 952, or if a threshold stop request has already been made to the APM driver in the OS in task 954, the supervisor routine is suspended for more than 15 seconds in task 954 ( whether or not pending).

If the pause has been pending for more than 15 seconds, the supervisor routine sets a threshold pause flag at task 958, causing the test at task 954 to be tested during the next APM acquisition event.

Thereafter, or if the suspension has not been pending for more than 15 seconds, the supervisor routine checks in task 959 whether the suspension is pending. If pause is pending, at task 960, CPU 40 causes microcontroller U2 to restart (reset) the failsafe timer and the APM fail-stop timer.

Then, or if the suspension is not pending, the supervisor routine moves to task 230 to check whether the system has just resumed. If the stop routine is called, whether the stop routine returns without stopping or after a complete stop and resume, the system assumes that it has just resumed. Resume is tested at task 230, and if the system has just been resumed (or if no stop was performed due to DMA or file activity), then a normal resume APM return code is generated at task 232 and at APM at task 234 Return to. In response, the APM OS driver updates the system clock and other values that may have been contaminated between them.

In most cases, system 10 is not just resumed, and the supervision routine moves to task 236 to test any user activity. In task 236, three types of user activity are tested: hard file 31 activity, keyboard 12 activity, and mouse 13 activity. For every APM acquisition event, the supervisor routine reads the hard file head, cylinder, and sector values from the hard drive 31 and checks whether there is activity (both indicating user activity) on the mouse interrupt line or on the keyboard interrupt line. The controller U2 is queried and reads the minute value (the minute value ranges from 0 minutes to 59 minutes and returns back to 0 minutes at the beginning of each hour) from the real time clock 98. Three hard drive activity variables (head, cylinder and sector) and minute values are stored temporarily. Then, these three hard drive activity variables are compared with the hard drive activity variables archived from previous acquisition events. If the three current hard drive values are the same as the values from the previous acquisition event and there is no activity on the mouse interrupt line or the keyboard interrupt line, then there was no user activity. If the hard drive values are different, or if there is activity on the mouse interrupt line or keyboard interrupt line, then there is user activity, and the current disk drive activity variable values are compared for readings during the next acquisition event Are kept.

The activity-detection approach described above is one where a routine is run on the CPU to determine hard drive activity and only two hardware interrupt activities are monitored.

Alternatively, activity can also be monitored in a hardware manner. For example, activity of all sixteen hardware interrupt lines can be monitored.

If there was activity, at task 238 the supervisor routine tests the wait flag to determine if computer system 10 is in standby state 152. If the wait flag is set to indicate that system 10 is in standby state 152, at task 240 the supervisor routine leaves standby state 152 and enters normal operating state 150. The supervisor routine exits the standby state 152 by repowering the device that was powered down upon entering the standby state 152 as shown in FIG. In summary, when the system goes out of standby, the supervisor routine recovers the video signal, spins the hard disk in the hard drive, recovers the system, and disables the APM CPU Idle calls. The CPU idle call from prevents further stopping the CPU 40, and clears a flag indicating that the system 50 is in a waiting state.

In addition, if there is activity, the minute value of the real time clock 98 is stored and compared with the minute value read during subsequent acquisition-events. Task 241 stores the current minute value to effectively reset the inactivity wait timer and inactivity stop timer. During normal use, there will be user activity and at task 242 the supervisor routine will set a No Event APM return code and return to APM call code at task 243. APM does not call any more routines in response to an event-free return code.

If the test at task 236 determines that there is no user activity, then at tasks 245 and 247 the supervisor routine tests whether the inactivity wait timer and the inactivity stop timer have expired, respectively. If system 10 is in standby state 152, no investigation is made regarding the end of the inactivity wait timer. Instead, the test skips in task 244.

By subtracting the current minute value from the stored minute value to obtain a value corresponding to the number of minutes that have elapsed since the user activity, whether the two timers are checked for termination. Task 245 compares this value to the inactivity wait timeout value, and task 247 compares this value to the inactivity stop timeout value. Two timeout values can be selected by the user, and the end of one of the two timers causes the system to enter either standby state 152, suspended state 154, standby state 152 or suspended state 154. It can also be set to prevent entry. Setting the timeout value to zero indicates that the timer should never end.

If the fraction that has elapsed since the last user's activity is equal to or greater than the inactivity wait timeout value, then at task 246, the supervisor routine causes system 10 to enter standby state 152. If the inactivity wait timer has not expired, at task 247, the supervisor routine tests the end of the inactivity stop timer. On the other hand, if the inactivity wait timer has expired, the supervisor routine places certain components into their respective low-power modes as shown in FIG. 18, causing the system 10 to enter standby state 152. FIG. .

In summary, in the preferred embodiment, the supervision routine blanks the video signal, spins down the hard disk in the hard drive, slows down the system clock, and enables the APM CPU idle call from the APM driver. CPU idle call causes CPU 40 to halt, and sets a flag indicating that system 10 is in standby state 152. After causing system 10 to enter standby state 152, at task 247, the supervisor routine tests the end of the inactivity stop timer.

At task 247, the supervisor routine determines if the inactivity stop timer has expired. If the fraction that has elapsed since the last user activity is equal to or greater than the inactivity suspend timeout value, the supervisor routine at task 248 sets a suspend request APM return code and returns to APM at task 243. As described with reference to task 226, in response to the set abort request APM return code, the APM performs any necessary system operation and invokes the abort routine. The stop routine is described in more detail with reference to FIG. 10 and, in summary, causes the system 10 to exit the normal operating state 150 and enter the suspended state 154. As described with reference to task 226, control may be returned to the supervisory routine from the stop routine, with or without stopping the system. On the other hand, if the inactivity stop timer has not expired, the supervisor routine at task 242 sets an eventless APM return code and returns to APM call code at task 243.

Although in most cases an eventless APM return code is returned to the APM, other various events may be returned to the APM. However, only one APM return code can be specified for each APM get-event. For example, after entering the standby state 152, no events are returned to the APM. After leaving the suspend state 154, the Normal Suspend APM return code is returned to APM. The particular message queued for APM depends on the exact nature of the computer system. Also, the supervision routine returns a normal resume return code or a pause resume APM return code.

Referring to FIG. 9B, an APM Working on Last Request routine is shown as starting at task 961. In response to the APM Working on Last Request, the BIOS APM routine initiates a fail safety timer and an APM fail-stop timer in the microcontroller U2 at task 962 and generates a task 963. Restarts the 15 second suspend hold timer to prevent a critical suspend request from occurring while the OS APM is waiting for the system to properly prepare for persistence, and returns from task 964.

Referring to FIG. 9C, the APM Reject Last Request Routine is shown as starting at task 965. In FIG. In response to the APM rejection final request being generated, the BIOS APM routine restarts the microcontroller U2's failsafe timer and APM fail stop timer at task 966, and immediately sets a stop flag at task 967. Force a stop routine and return from task 968.

Power-up and resume routines will be well understood by understanding the stop routine. Therefore, the description of the APM BIOS routine is most clearly understood based on the following sequence.

General overview of the power-up routine of the present invention (FIG. 8), details of the supervision routine (FIG. 9), suspending routine of the present invention (FIG. 10), details of the power-up process of the present invention (FIG. 11), details of the resume routine of the present invention (FIG. 12), details of the stored CPU state routine (FIG. 13), details of the CPU state recovery routine (FIG. 14), and the storage 8259 state routine. Details of (figure 15).

Since most routines interact with other routines and the suspend / resume process is a cycle that follows, although the description of the computer system 10 of the present invention is somewhat circular, a boot routine (FIG. 11) or a resume routine (Twelfth) It would be most helpful to describe the stop routine (FIG. 10) before FIG. Referring now to FIG. 10, a flow diagram of a stop routine is shown. Recall that after normal boot routine 204-210 or resume boot routine 214-220 is executed, computer system 10 is in a normal operating state. Moreover, as described with reference to FIG. 8, once this boot routine is over, whether the computer system is normally booted (204-210) or resume-boot (214-220), the APM OS driver is shown in FIG. Recognizes APM BIOS routines such as supervision routines. As a result, the APM polls the supervision routine approximately every second.

10 illustrates a stop routine starting at task 250. The abort routine is called by the APM in response to the supervisor routine returning the abort request APM return code to the APM. The stop routine is also called and specifically executed when the system performs a checkpoint as described in more detail with reference to FIGS. 17 and 18. First, the flow of the pause routine depends on whether the CPU 40 in task 970 is an S part with SMI. If so, the CPU 40 causes the microcontroller U2 to regenerate the SMI to the CPU 40 at task 972. In response to the SMI, the microcode within the CPU 40 stores the state of the CPU 40 in the segment E000H data structure, as is well known to those skilled in the art at task 974.

On the other hand, if the CPU 40 is not the S portion with SMI, the archive CPU state routine is called as shown in task 252. The storage CPU state routine will be described in more detail with reference to FIG. At this point, note the following: That is, regardless of which mode the CPU 40 was in when the stop routine was first called, the remainder of the stop routine will run in real mode on the CPU 40, thus allowing for an allowed address space. It can be executed without fear of an error that may occur by attempting to execute an instruction beyond the scope of, or by attempting to execute a privileged instruction.

At task 253, the storage CPU state routine returns the program control to the stop routine in a unique manner. Returning from the save CPU state routine to the stop routine includes resetting the CPU, which will be described in more detail with reference to tasks 630 and 632 of FIG. The important thing about the pause routine is that the CPU registers are written to the segment E000H data structure and the CPU 40 is now in real mode.

After the save CPU state routine returns or after the CPU saves its state in response to SMI, at task 254 the stop routine checks whether the switch 21 has been pressed.

The closure of the switch 21 is tested as described with reference to FIGS.

The key is that if the switch 21 is pressed, the power management port will return the FEH when it is read. If the switch is not pressed, the ongoing stop is software-stop and a software-stop flag is set in the CMOS NVRAM 96. This avoids confusing the software stop with the hardware stop initiated by the switch closure. All software-stops are converted by setting one bit in the microcontroller U2. Closing the switch after converting a software halt to a hardware halt causes abandonment of the halt.

The next step is to set up the stack, as shown in task 262.

After setting up the stack in the suspend routine, task 264 examines the DMA controller 72, diskette adapter 84, and IDE disk controller 86, where DMA transfers, floppy drive transfers, or hard file transfers are currently in progress. Judge. If in progress, satisfactory suspension cannot be performed due to the unique nature of these three types of transmissions. For example, if a hard file transfer from a hard drive is in progress, this data has already been read by the IDE controller but has not yet been transferred to system memory 53. Since this data cannot be properly accessed by the CPU, it is likely that this data will be lost when the system is stopped in the middle of a hard file read. Thus, if any of these three types of transmissions are in progress, the suspension is postponed until the next APM acquisition-event, in which the activity of the DMA controller and diskette controller is tested once more.

As a result, the task performed in tasks 252, 260 and 262 must be reversed so that control can be returned to APM again. First at task 265, the BIOS is changed from read / write to read-only. This is accomplished by closing the segment E000H which still contains the shadowed data. The stack created in task 262 is popped and recovered. Finally, at task 266, the CPU state recovery routine recovers the CPU state, and then at operation 267, control returns to APM. The abort routine will be polled again by the APM after approximately another second during the next acquisition-event. At that point, the transfer (s) that made the suspend process impossible may have been completed, and so the suspend may continue.

Referring now to task 264 again, if there is no DMA transfer, floppy drive transfer, or hard file transfer currently in progress, the abort may be performed. The pause routine continues at task 268. Recall that the fail-safe timer continues to decrease and causes the system to turn off on its own when it expires when the switch 21 is in the off / off state.

Thus, as described with reference to FIG. 6, in task 268, the first task is to reset the failsafe timer.

Next, the state of the 8042 coprocessor 104 is stored in task 270. Registers of the 8042 coprocessor 104 are well known in the art. These registers can be accessed directly by the CPU 40, and these values are written directly to the data structure in E000H.

Next, task 272 holds the state of 8259 interrupt controller 92. The abort routine calls the 8259 stored state routine, which will be described in detail with reference to FIG. At this point, it is sufficient to recognize that the 8259 archive state routine verifies the contents of the unknown registers of the two 8259 interrupt controllers 92 (although some registers may be write-only). The values of these registers are written directly into the data structure of E000H.

After the state of the interrupt controller 92 is stored, the configuration of the interrupt controller 92 changes to a known state so that various interrupt-driven tasks executed by the interrupt routine operate properly. It should be done. Thus, at task 274 the BIOS data area and the vector table are swapped. The suspend routine copies the contents of the present-state BIOS data area and vector table in segment 0000H to one location in segment E000H. Next, the contents of the known-state BIOS data area and the vector table from the data structure in segment E000H are copied to the position in segment 0000H. The known-state BIOS data area and vector table are copied into segment E000H in task 414 of the FIG. 11 boot-up routine described below.

Finally, the current-state BIOS data area and vector table are copied from segment 0000H into the data structure in segment E000H. At the end of the routine at task 274, all interrupts such as interrupt 13H (disk read / write) and interrupt 10H (video access) will function as expected.

Next, at task 276 the state of timer 102 is stored. Registers of timers are well known in the art. The CPU 40 can read all the registers directly, and writes the read register values directly into the data structure in E000H. At task 276, the state of IDE disk controller 86 is also stored. IDE disk controller 86 registers are well known in the art. The CPU 40 can read all the registers directly, and write these read values directly into the data structure in E000H.

The next step is to prepare the system memory for writing to a pause file on the hard drive 31. The system memory has a system RAM 53 (including main memory and extended memory) and a video memory 58. At this time, part of the RAM 53 may be in an external cache 60. In task 628 the CPU cache was flushed, which will be described with reference to FIG. Next, at task 286 the external cache is flushed and enabled to expedite writing to hard drive 31.

Code running on system 10 may leave IDE controller 86 unknown. Thus, the next step is to initialize IDE controller 86 to a known state in task 292. This is accomplished by writing the values directly into the registers in the IDE controller 86.

Next, an interrupt-driven parallel thread is started at task 976 to read the state of any modem and store it in the E000H data structure. This routine detects the interrupt corresponding to the COMM port associated with a particular modem, sends a command to the modem to cause the modem to resequentially send the contents of its register, receives a register contents transmission from the modem, and registers the register value. Store in E000H data structure. This routine sends the first command to the modem, responds in an interrupt-driven manner, receives the modem's response in response to each COMM port interrupt until all of its modem registers are stored, and sends the next command to the modem. do. If not run as a parallel thread, this routine can add several seconds (3-5 seconds per modem, depending on the specific modem and current baud rate) to the time it takes to shut down the system. The interrupt driven parallel thread adds little or no time to the time it takes to halt the system if it completes execution before the system state is written to the hard drive 31.

After the interrupt driven parallel thread modem storage routine is initiated, at task 294 the pause file must be located on a fixed disk in hard drive 31. The heads, sectors, and cylinders of the pause file are stored in the CMOS memory 96. Once the pause file is located, the file size, signature is read. In a preferred embodiment, the signature indicates the presence of a pause file in any length ASCII code. Another alternative for implementing a signature is to use a binary string that is very unlikely to be randomly found on a hard file system.

After reading the file size and signature of the pause file, the next step is to verify in task 296 that the signature and file size are correct. If the signature is different to indicate that another program has modified the pause file, or if the file size is different to indicate that the pause file size has been modified, then at task 298, the pause routine initiates a fatal stop initiated at task 652 of FIG. Call the Fatal Suspend Error Routine. The program jumps from task 299 to task 506, where the user presses switch 17 to exit the fatal stop error routine.

On the other hand, if the signature is correct and the suspend file is large enough, the suspend routine may continue to write the state of the computer system to memory.

Before recording the state of the computer system 10 to the hard drive (long), the CPU 40 instructs the microcontroller U2 at task 296 to restart (reset) the failsafe timer C2. Then, the microcontroller U2 is queried to determine whether the switch 21 is pressed again. If the switch 21 is not pressed again, the stop must be continued.

On the other hand, if the switch 21 is pressed again, the pause is abandoned. A test is made for the closure of the switch 21 at a number of points in the pause routine. Task 297 is merely illustrative. One of ordinary skill in the art of applicable art will be able to determine the number of times and the allowable time between restarts of the failsafe timer. The stop routine must reset the fail safe timer before the fail safe timer expires and the power supply 17 is turned off by the microcontroller U2. Likewise, switch 21 should be checked from time to time. When the switch 21 is pressed again, it indicates that the user wants to give up the stop, so the code jumps to the appropriate point in the resume routine to un-suspend what has already been stopped by the stop routine. Recover from partial suspension

Similarly, the key operation of Ctrl-Alt-Del at task 350 aborts abort. Pressing the Ctr1-Alt-Del keys (ie, pressing the Ctrl, Alt and Delete keys simultaneously) is a well-known way to reset a typical computer system based on the IBM BIOS and the Intel 80X86 CPU family. As is well known in the art, the computer system 10 manages Ctr1-Alt-De1 with a BIOS interrupt 1 handler. Computer system 10 includes a slightly modified interrupt 1 processor at task 350 to clear the suspend flag in CMOS memory 96 at task 352 and then to reset the boot-up at task 354. Jump to the routine

In the computer system 10 of the present invention, pressing Ctrl-Alt-Del while the pause routine is executing causes the computer system 10 to enter the off state 156. This means that pressing Ctrl-Alt-Del after the switch 21 is closed will invoke the boot-up routine, which will cause the microcontroller U2 to fail and the fail-safe timer has expired and the switch is still off / off. Occurs because it is initialized to Thus, pressing Ctrl-Alt-Del while in the pause routine causes the computer system 10 to enter the off state 156. Referring now to task 300, the pause file is repositioned on hard drive 31. In task 300, the signature phrase is written to the first byte of the pause file. Next, at task 302, the entire 64 kilobytes of data in segment E000H are written to the pause file. This 64K copy of the E000H will substantially function as a place holder and will be rewritten to the same place at the end of the pause routine.

The state of video controller 56 is then stored at task 303. Video controller 56 registers are well known in the art. All registers are directly readable by the CPU 40, and their values are written directly to the data structure in E000H.

Then, the system memory is written to the pause file. This is accomplished by a twin-buffer system reading data from system memory, compressing the data and writing it to segment E000H, and finally writing the data compressed from segment E000H to the pause file. do. Two routines operate in a time-multiplexed arrangement. One compresses the data and writes it to segment C000H. The other writes to the pause file. The former is an interrupt-driven routine that runs in the foreground and the latter runs in the background. Obviously, there is only one CPU 40 so only one routine is executable within a given time. However, since the latter routine is an interrupt-driven scheme, it is possible to interrupt the execution of the former routine as needed to optimize the data transfer speed of the pause file. The two buffers are each 8 kilobytes long, and the length is thought to optimize the transfer time to the hard drive 31.

This process begins at task 304, after reading and compressing data, writes enough data to segment E000H to fill the beginning of the 8K buffer. The data is compressed using a run length encoding method. However, other suitable compression methods may be used. At this time, the write routine from the buffer shown in task 307 is started. The write routine 307 from the buffer is an interrupt-driven routine that runs in the backtown and consists of tasks 308-310. The compression routine represented by task 311 consists of tasks 312-318 and is a foreground routine. First, the write routine 307 from the buffer at task 308 is now blocked by task 304 to write to the buffer stop file. Write routine from buffer 307 Write buffer contents to stop file

In the meantime, at task 312, the compression routine 311 continues to read and compress the next byte from system memory, and then writes this compressed data to the other of these two 8K buffers. Once the compression routine 311 fills the buffer with compressed data, the next step, task 314, determines whether the entire system memory has been compressed.

The IDE controller 86 cannot write data to the hard drive 31 very quickly. As a result, the compression routine 311 is not being written to the hard drive 31 before the write from buffer buffer 307 finishes writing the buffer to the hard drive 81. You will finish filling the 8K buffer.

Thus, the compression routine 311 must wait for the write routine from the buffer to finish writing the buffer to the hard drive 31. If the compression routine 311 fails to finish compressing and writing all system memory, the compression routine 311 waits for the write routine 307 from the buffer at task 316. The compression routine 311 and the write routine 307 from the buffer communicate via a set of flags. When the write routine 307 from the buffer finishes writing the current buffer to the pause file, the routine switches the buffer flag so that the compression routine 307 can begin filling the buffer written to the pause file with compressed data. Indicates that it can. Next, as described with reference to task 297, the failsafe timer C2 is reset and the switch 21 is checked for a closure event.

In task 310, the write to buffer routine 307 now determines whether the buffer just written to the pause file is the last buffer to be written. If it is not the last buffer, the write routine from the buffer writes the buffer filled by the compression routine 311 to the pause file. In the meantime, the compression routine 311 examines the buffer flag to determine whether the buffer is ready to receive further compressed system memory. That is, at task 316, the compression routine waits until the write routine from the buffer finishes the current buffer and then continues with the compression routine at task 312.

Note that video memory 58 is compressed if linear frame buffering is supported, but not for VESA page access. Instead, as described in more detail above, the VESA page access video memory is read through video controller 56 using VESA calls and written without compression using a twin-buffer system.

Once the compression routine 311 finishes compressing all system memory, it waits for the task 318 to write from the buffer to the write routine 307 to write the last buffer to the pause file. Once the write routine from the buffer is complete, the write routine from the buffer branches off from task 310 to task 318 and disappears. This background, no background routine is running, and the main program continues at task 320.

Next, at task 320 the states of DMA device 71 (DMA controller 72 and central arbiter 82), 82077 diskette controller 84, and RS-232 UART 94 are stored. . These devices have registers well known in the art. All registers in diskette controller 84 and UART 94 are directly readable by CPU 40, and these read values are written directly to the data structure in E000H. The DMA device does not have readable registers. Instead, read-only registers are typically set up before each DMA transfer operation. For this reason, the stop routine stops stopping when a DMA transfer is in progress.

Next, in task 978 the abort routine tasks whether the interrupt driven modem state routine described with reference to task 976 has completed. If it's not done, wait for it to complete.

Once computer system 10 enters suspend state 150, it is desirable to be able to detect any tampering on the suspend file. For example, it is possible for a person to create a modified pause file, move it to the hard drive 31, and then attempt to recover the computer system 10 to a state different from the previously stored state. For this purpose, pseudo-random values are placed in the segment E000H data structure. As shown in task 328, a 16-bit time-stamp is read from one of the fast timers 102 after the interrupt drive modem state preservation routine is completed. This timestamp is then recorded in the segment E000H data structure.

Next, a 16-bit checksum for the entire E000H segment is calculated by adding each 16-bit word in segment E000H without considering the carry bit. At check 330 this checksum is written to the segment E000H data structure and at task 332 is written to CMOS NVRAM 96. After this process, at task 334, all working variables are written from the CPU 40 into the segment E000H data structure, and at task 336, the entire segment after the signature phrase of the pause file (just after the signature). E000H is rewritten as a pause file. Next, a stop flag is set in the CMOS NVRAM 96 to inform the system 10 that the state of the computer system 10 has been stored as a stop file at task 338.

Next, the abort routine determines if a checkpoint is being taken at task 980. If a checkpoint is being taken, the system should not be powered down; instead, the system should be resumed to the extent necessary to recover from the partial suspension just performed. Thus, if a checkpoint is being taken, the abort routine jumps from task 982 to task 484 of the resume routine and starts partial resume.

If no checkpoint is being taken, the CPU 40 turns off the power supply by instructing the microcontroller U2 to make the ON signal a logic 0, thereby causing the primary / regulation of the power supply 17 to be primary / regulation. unit) 172 stops providing regulating voltage along the ± 5 and ± 12 lines. Since it takes several seconds for the voltage to ramp down to almost zero, the CPU 40 can execute a number of commands. Thus, the CPU 40 enters an endless loop (spin) at task 342 when the system power voltage generated by the power supply 17 decreases and waits for the CPU 40 to stop functioning. Execute.

Referring now to FIG. 11, a boot-up routine is shown in detail. The boot process has been briefly described with reference to FIG. When the CPU 40 jumps to and executes the code indicated by the reset vector, the boot-up routine starts at task 380. This occurs every time the CPU 40 is powered up and every time the CPU 40 is reset by jumping to the code indicated by the reset vector. This reset procedure is well known in the art.

The first task, at task 382, is to test the CPU 40 and initialize the memory controller 46. The CPU is tested by the POST routine. Part of the CPU test is to determine whether the CPU 40 is the S portion with SMI. If so, a flag is set to indicate this fact. The memory controller 46 is initialized by the POST routine.

The bootup routine then tests whether task 986 has microcontroller U2 functioning. To do this, the CPU sequentially reads the status port of the power management circuit 106 and waits for a transition from high to low and low to high at this port. This transition is such that the hard bit of the microcontroller U2 is functioning, so that the CPU 40 can continue the booting process assuming that the microcontroller U2 is functioning as expected.

If the CPU does not detect a transition at the state port within a preset period, for example one or two seconds, the microcontroller U2 does not have a hard bit, and the CPU 40 is as described above in task 988. Command the first PAL U1 to reset the microcontroller U2. At task 990 CPU 40 again waits for a transition from high to low on the status port. If the CPU does not detect a transition on the status port again within one or two seconds, microcontroller U2 does not have a hard bit and CPU 40 assumes that microcontroller U2 cannot be reset. In task 992, the power managemeut features described herein are disabled.

On the other hand, if the microcontroller U2 is functioning, the CPU 40 refreshes the wake up minute alarm value in the microcontroller U2 at task 994. The time base of the RTC 98 is much more accurate than the time base of the microcontroller U2. Thus, to overcome this limitation without adding a more accurate and expensive time base to the microcontroller U2, the BIOS synchronizes the less accurate time base with the correct time base, and every time the system is booted, the microcontroller U2 The wakeup minute alarm value within is updated to a more accurate value obtained from the RTC 98. To accomplish this, the CPU 40 reads the absolute alarm date and time from the CMOS memory 96, calculates the wake-up minute alarm value and writes it to the microcontroller U2.

Thereafter, if the microcontroller U2 is also not functioning and the power management feature is disabled, then the boot routine determines whether the system has booted by applying power to the power source 17 at task 996. Preferably, power source 17 always allows AC power to be applied to its main / regulator 17, and the regulation of power at the ± 5 and ± 12 lines is controlled by the ON # input. In this way, the power source 17 provides the AUX5 necessary to power the power management circuit 106 and can be controlled by the power management circuit 106 without switching AC power by itself.

However, as is well known to those skilled in the art, some users use switched power strips (not shown) to power their computer systems, and turn off AC power to the entire system by a single switch. And to turn on. This poses a problem for the power management circuit 106 because the microcontroller U2 and other devices are configured to be powered continuously by the AUX5 power line. Thus, the system must include a method of determining that the system is powered by and acting upon the application of AC power.

However, the AUX5 line is also prone to black out and brown out as described above. After blackout or brownout, reset subcircuit 920 resets microcontroller U2 to prevent microcontroller U2 from malfunctioning due to voltages outside the tolerances. Thus, the system should be able to further determine if the microcontroller has been woken up after blackout or after application of AC power.

As a result, at task 996, the CPU queries microcontroller U2 about the event that caused power source 17 to turn on. The microcontroller has any one of four responses, i.e. (1) the microcontroller has been reset so that the power supply 17 has begun to supply regulating power at ± 5 and ± 12 lines, and (2) May expire, either (3) ring has occurred at the RS-232 ring input or at the ring input from opto-isolator (OPT01), and / or (4) switch 21 has been pressed. The reason the system is powered on can be read directly by the microcontroller U2 by an application program, such as a scheduler, to run a given program in response to the specific reason the system is powered on. Alternatively, the reason for powering up the system can be obtained through one or more BI0S calls.

Except for being reset by the CPU 40, the microcontroller U2 is reset only by the reset subcircuit 920. This reset subcircuit 920 resets the microcontroller each time the AUX5 line is applied or glitched. Thus, if the microcontroller U2 is reset or if the microcontroller returns an invalid wakeup code that is tested at task 997, the CPU 40 has a power supply of ± 5 and at task 998. It should be determined whether power regulation should be maintained at the ± 12 line. For this purpose, a flag in CMOS NVRAM called DEFAULT_ON is used. If this flag is set, the power supply 17 must continue to supply regulating power after the microcontroller U2 is reset. On the other hand, if the DEEAULT_ON is not set, the power supply 17 must stop supplying the regulated power after the microcontroller U2 is reset, so that the CPU 40 may perform the microcontroller U2 at the task 1000. ) Stops the power supply 17 supplying regulated power at the ± 5 and ± 12 lines. After that, it takes several seconds for the voltage to ramp down to approximately 0 volts, so that the CPU 40 can execute a number of commands in between. CPU 40 then executes an infinite loop (spin) in task 1002 when waiting for task 1004 to decrease the system power supply voltage generated by power supply 17 until the CPU ceases to function. do. As mentioned above, the microcontroller U2 is preferably continuously powered by the AUX5 line and continuously executes its programmed routine.

Thereafter, if the microcontroller has returned a valid wakeup code at task 997 or if the microcontroller U2 has been reset at task 998 but the system is still powered up, then the CPU 40 ) Commands microcontroller U2 at task 1004 so that microcontroller U2 determines that power should be turned off and stops power supply 17 from supplying regulating power at ± 5 and ± 12 lines. Prior to this, the CPU 40 generates the SMI again. Also, at task 1004, the CPU sets the DEFAULT_ON bit in the CMOS NVRAM so that if AC power is lost, the system will turn itself on after AC power is reapplied.

The boot routine then performs a first Plug and play resource allocation pass at task 1006, as is well known to those skilled in the art.

The shadow memory is then tested and the BIOS copied from the ROM 88 to the shadow memory portion of the RAM 53. The flow of executed code depends on whether or not the stop flag is set in the CMOS NVRAM 96.

If the stop flag is set, the computer system 10 is in the suspended state 150 and the computer system 10 should be restored to the state it was in when it was stopped. The system RAM53 in the segments E000H and F000H is subjected to a shortened test. To reduce the time it takes for the computer to resume, the memory is only checked for the appropriate size and zeroed (000H is written to each location).

On the other hand, when the stop flag is cleared in the CMOS NVRAM 96, the system RAM 53 in the segments E000H and E000H includes (1) sticky-bit test and (2) double. A standard, in-depth memory test is performed, including a double-bit memory test, and (3) a crossed address line test.

After the segments E000H and E000H have been tested, the BIOS can be shadowed by copying the contents of the ROM BIOS 88 into the system RAM 53 and configuring the memory controller to run the BIOS in the RAM. BIOS shadows increase system speed. The BIOS runs on fast system RAM 53 (typical access speed of 80 nanoseconds) rather than on slow ROM 88 (typical access speed of 250 nanoseconds), thereby improving system performance. Shadowing of the BIOS loads the BIOS copier into an address in lower memory, copies the BIOS from ROM 88 to segments E000H and F000 of system RAM 53, and shadows RAM It includes enabling.

Next, at task 384, video controller 56 is tested and initialized, and video memory 58 is tested. Such testing and initialization is well known in the art.

The boot routine then performs a second plug and play resource allocation pass, which is well known to those skilled in the art, at task 1008. At task 386, the flow of executable code depends on whether the stop flag is set in CMOS NVRAM 96. If the stop flag is set, the remaining system RAM 53 is only checked in size and zeroed, as in task 383. However, if the stop flag is cleared in CMOS NVRAM 96, then at task 398, the remaining system RAM 53 is tested using a three-step in-depth test, as described with reference to task 383. do.

After the memory is tested, auxiliary devices--8259, UART, 8042, and others--are tested and initialized in task 400. At task 408, the fixed disk controller is initialized.

At task 409, the flow of executable code depends on whether or not a stop flag is set in CM0S NVRAM 96. If the stop flag is set to indicate that the state of the system was successfully saved when power was last removed, the boot-up routine skips testing the hard drive controller 86 and the hard drive 31. On the other hand, if the stop flag in the CMOS NVRAM is cleared to indicate that the state of the system was not saved when power was last removed, then the boot-up routine at task 410 may indicate that the fixed disk controller 86 and hard drive A complete test of (31) is performed, which is well known in the art.

In the next task 412, the floppy drive controller 84 is tested and initialized.

At this point, all devices are initialized and the vector points to known locations, and all interrupt routines will work as expected. Thus, at task 414, the boot-up routine snapshots the BIOS data area and vector table, writing a copy of the BIOS data area and vector table to the data structure in segment E000H. This copy of the BIOS data area and vector table is used by the stop routine in task 274 to place computer system 10 in a known state and to ensure that all interrupts operate as expected.

Next, BIOS extensions in task 416 are scanned and initialized as is well known in the art. BIOS extensions are blocks of BIOS code added to the system by peripheral adapters, such as network adapters. The BIOS extension is typically located on segments C000H and D000H on the ISA bus 76 and has an associated signature to identify the BIOS extension. If a BIOS extension is detected, the length is checked and the checksum is calculated and checked. If all of the signatures, lengths, and checksums indicate that a valid BIOS extension exists, program control is passed to an instruction located three bytes past the signature, and the BIOS extension can perform any necessary tasks, such as initializing the peripheral adapter. Can be. Once the extension has finished executing, control passes back to the boot-up routine, which searches for more BIOS extensions. Subsequent BIOS extensions are treated like the BI0S extension described above. If no more BIOS extensions are detected, the boot-up routine moves to task 417.

Next, at task 1010, the CPU reads the system power-on hours delta and adds it to the value stored on the special partition of the hard drive 31, and the new full power. The on time is rewritten to a special partition on the hard drive 31. As shown in FIG. As described elsewhere herein, before the microcontroller U2 powers down the system, the microcontroller interrupts the CPU 40 by applying an SMI line. As a result, the CPU performs certain tasks on the assumption that the system will power down soon. Preferably, the method includes storing predetermined information in the CMOS NVRAM, such as a power-on delta measured by an elapsed power-on hours timer. The CPU 40 then allows the microcontroller U2 to power down the system.

At task 417, the boot-up routine searches for a partition on hard drive 31, which is believed to have been specifically assigned to that pause file. If a partition with PS / 1 identifier (FE) or hibernation partion with identifier 84 is found in the partition table and this partition is large enough to accommodate the suspend file of this particular system, the suspend file Is determined as the partition for. As a result, the pause file signature is written to the first byte of the file, and the start head, sector, and cylinder of the file are written to CMOS NVRAM 96.

Thereafter, the flow of executable code branches at task 418 depending on whether or not a stop flag is set in CMOS NVRAM 96. If the suspend flag is cleared, the boot-up routine transfers control to the PBOOT routine at task 420. PBOOT is well known in the art and is responsible for loading command interpreters and operating systems (OS) from floppy disks or hard drives 31. If no partition for the stop file is found in task 417, the OS runs an OS-specific driver that checks whether the partition has been found (described with reference to FIG. 16), and if not found, a contiguous sector in the FAT. It allocates a file of contiguous sectors, writes a signature to the first byte of the pause file, and writes the start head, sector, and cylinder of the pause file to CMOS NVRAM 96.

Regardless of when a pause file is assigned, the file must be a continuous sector, allowing for fast writing to and reading from the disc during pause and resume.

The OS then configures the system based on the instructions found in the CONFIG.SYS file. Finally, the OS runs the AUTOEXEC.BAT file, and the AUTOEXEC. The BAT file eventually passes execution control back to the operating system. If the stop flag is cleared in CMOS NVRAM to indicate that the state of the system was not saved when power was last removed, the RESUME. Described in detail with reference to task 421. EXE is ignored.

Referring back to task 418, if the stop flag is set in CMOS NVRAM 96, indicating that the state of the system was saved when power was last removed, then the flow of executable code is lost at task 419. Branching is made depending on whether or not a Reinitialize Adapter Flag is set in the CMOS NVRAM 96. If the reinitialization adapter flag is set, the boot-up routine transfers control to the PBOOT routine of task 421. Like conventional PBOOT routines, the PBOOT routines of the present invention configure the system in instructions in the CONFIG.SYS and AUTOEXEC.BAT files that load the drivers and configure the system, as is well known in the art.

Commands in CONFIG.SYS and AUTOEXEC.BAT can initialize the adapter card in the system. This application assumes that there are three types of adapter carts. Type I adapters do not require initialization. Type II adapters require initialization but are placed in a known working state by a driver or BIOS extension loaded in the CONFIG.SYS or AUTOEXEC.BAT file.

Type III adapters are modified by code execution on the system. Systems with Type I and Type II adapters can be stopped and recovered. However, a system with a Type III adapter that includes a number of networking adapters may be associated with the associated APM recognition that causes these cards to reinitialize this adapter after certain conditions, such as system power being removed. It cannot be recovered unless it is equipped. The system may suspend a Type III card with an APM-aware device driver.

In the preferred embodiment, the RESUME.EXE file is added to the AUTOEXEC.BAT file and is responsible for transferring program control from the PBOOT to the resume routine. At task 420, the OS ignores the presence of RESUME.EXE. However, the OS of task 421 executes RESUME.EXE to transfer control to the resume routine after the Type II adapter is initialized by the device driver loaded by the OS from CONFIG.SYS and AUTOEXEC.BAT.

Referring back to task 419, if the reinitialization adapter flag is cleared in CMOS 96, the OS transfers execution control to the resume routine via RESUME.EXE.

The resume routine recovers the system state from the pause file on the hard drive, which will be described in more detail with reference to FIG.

Referring now to FIG. 12, a resume routine consisting of tasks 450-530 is shown in detail. First, if CPU 40 has SMI in task 451, a CPU resume SMI is generated that places the CPU in SMM mode and jumps to the code of task 454. If the CPU does not have SMI, a resume shutdown occurs, which causes a reset and the reset handler jumps to the coat of task 454.

During the configuration process, BIOS data areas and vector tables can be modified in an unknown state. Therefore, the default BIOS routines may or may not work as expected. Thus, at task 454, the resume routine enables segment E000H to read / write, and at task 456 calls the swap BIOS data area and vector table routine. This routine swaps the known good BIOS data area and vector table that was copied to segment E000H at task 414 with the modified BIOS data area and vector table currently active at segment 0000H. When the routine is complete, the known BIOS data area and vector table will be active in segment E000H, the modified BIOS data area and vector table will be in segment E000H and the BIOS routine will work as expected.

The resume routine at task 458 then disables all interrupts except those supporting the hard drive and keyboard. The resume routine at task 460 then places the pause file on the hard drive and reads the non-suspended file size and the signature, which is a multi-byte identifier as described above. The flow of executable code in task 462 branches according to whether the pause file has the correct size and signature. If the suspend file does not have the correct size and signature, then branch to task 464 and clear the suspend flag in CMOS memory 96, then at task 466 the program control returns to the code in the location indicated by the reset vector. It is forwarded to boot this system as if the system was not stopped. On the other hand, if the pause file has the correct size and signature, the resume routine may cause task 468 to read 64K blocks (part of the pause file corresponding to segment E000H information) in the pause file located after the signature and write to segment 1000H. Continue to resume the system.

Next, at task 470 the checksum of the block in 1000H is calculated, at task 472 the checksum previously stored from CMOS nonvolatile memory 96 is read, and at task 474 the flow of executable code is passed to task 470. Branch based on whether or not the checksum computed in < RTI ID = 0.0 > If the checksum calculated at task 470 is different from the checksum calculated at task 330, the stop file is somewhat defective (for example, may be forged), and control passes to task 464, As described with reference to tasks 464 and 466, clear the stop flag and reset the system. If the checksum calculated in task 470 and the checksum calculated in task 330 are the same, the pause file in task 476 is considered to be the same as that recorded by the pause routine, so that the data in segment 1000H is copied to segment E000H. .

At task 478, the resume routine now records on the screen a specific signal indicating to the user that the system is recovering and that the user must press Ctrl-Alt-Del to abandon the resume. As in the suspend routine, pressing Ctrl-Alt-Del clears the suspend flag in task 526 and reboots the system in task 528. Thus, when Ctrl-Alt-Del is pressed and a resume routine is running, the system reboots normally.

In the next tasks 480 and 482, the 82077 diskette controller 84, the DMA device 71, and the UART 94 are recovered by writing the values of the segment E000H data structure into their respective registers.

Then, at task 1020 an interrupt-driven parallel thread is started to recover the state of any modem from the E000H data structure. Similar to the routine in task 976, the modem recovery routine / detects the interrupt corresponding to the COMM port associated with the particular modem, reads the value from the E000H data structure, and sends the command and value to the modem to cause the modem to Restore the register of. This routine sends the first command to the modem and then responds in an interrupt-driven manner, receiving the modem's response and responding to each COMM port interrupt until the modem's registers have been recovered. send.

As with the modem storage routine, if not run as a parallel thread, this routine can take a few seconds longer to resume the system. Since this is an interrupt driven parallel thread, it will add little or no time to resume if the system state is fully executed before being read from the hard drive 31.

After the interrupt driven parallel thread modem recovery routine is initiated, at tasks 486-500, the system memory is suspended using a twin-buffer routine similar to the routine described in the description with reference to tasks 304-318. Recover from a file

The twin-buffer system reads the compressed data from the pause file, writes this read data to segment E000H, decompresses it again and writes it to system memory. These two routines work in time division. One routine reads data from the pause file, writes the read segment to E000H, and the other routine decompresses the data and writes this decompressed data to system memory. The latter runs in the foreground, while the former is an interrupt-driven routine that runs in the background. Clearly, since only one CPU 40 exists, only one routine can be executed at a given time. However, since the former routine is an interrupt-driven routine, it is possible to interrupt the execution of the latter routine as needed to optimize the data transfer rate from the pause file. The length of each of the two buffers is 8K bytes long, which is considered to optimize transfer time.

This process begins at task 486, reads from the pause file, and writes to data segment E000H sufficient to fill the beginning of the 8K buffer. At this point, the Read from Buffer Routine 489 begins at task 306. The read routine 489 from the buffer is an interrupt-driven routine that runs in the background and consists of tasks 490-492. Decompression routine 493 consists of tasks 494-498 and is a foreground routine. First, at task 490, the read routine 489 from the buffer begins reading the next 8K bytes of the pause file, and starts writing this read data to another buffer that is now the current buffer. While the read routine from the buffer reads the next 8K bytes of the pause file and writes it to the current buffer, at task 494, the decompression routine 493 reads the buffer filled by task 486 and then decompresses it. Decompresses data and writes it to system memory.

Once the decompression routine 498 decompresses all the data in the buffer, the next step 496 determines whether the entire system memory has been decompressed.

The IDE controller 86 cannot read data from the hard drive 31 quickly. Thus, the decompression routine 493 always decompresses an 8K buffer that is not being written to the hard drive 31 before the read routine from the buffer completes reading data from the hard drive 81 into the current buffer. Will complete. Thus, the decompression routine 493 must wait until the read routine 489 from the buffer completes reading the data from the hard drive 31. If the decompression routine 493 did not finish compressing and writing the entire system memory, then at task 498 the decompression routine 493 must wait for the read routine 489 from the buffer. Decompression routine 493 and read routine 489 from the buffer communicate via a set of flags. When read routine 489 from buffer finishes reading data from the pause file to the current buffer, at task 490 the routine 489 switches the buffer flag so that the decompression routine 493 reads from the pause file. The decompression routine 493 indicates that the decompression of the data within can be started. Then at 492 read routine 489 from buffer determines if there are 8K blocks left to be read from the pause file. If there are no blocks left to read, at task 502 the read routine from the buffer reads the remaining data from the pause file and writes this read data to the current buffer. The read routine from the buffer at task 500 then stops executing in the background, in effect waiting for the decompression routine to finish decompressing the last memory.

In the meantime, the decompression routine 493 examines the buffer flag to determine whether the buffer is ready to be decompressed into system memory. That is, the decompression routine waits at task 598 until the read routine from the buffer completes for the current buffer, and the decompression loop at completion continues at task 494.

Once the decompression routine 493 completes decompression for all system memory, the only background routine running is the interrupt-driven modem recovery routine described with reference to task 1020, and the main program continues at task 504. do.

Next, at task 504 and 506 video controller 56 and IDE controller 86 are recovered by writing a value from the E000H data structure into registers of their respective devices. Task 504 is also a point indicating that the stop routine should jump (see task 1024) if a checkpoint is being taken.

Next, at task 1022, the resume routine tests whether the interrupt drive modem recovery routine described with reference to task 1020 has completed. If the test does not complete the routine, the resume routine waits for the routine to complete.

As shown in task 508, after the interrupt driven modem state recovery routine is completed, the CPU cache 41 and system cache 60 write the appropriate values to the CPU 40 and the cache controller 62, respectively, to print out. Is enabled. The resume routine then writes the values from the segment E000H data structure to the registers in each device at tasks 510 through 514 to the timer controller 102, 8042 keyboard interface microprocessor 104, and 8259 interrupt controller 92. To restore the state of

Next, at task 484, the UART 94 is recovered by writing the values from the segment E000H data structure into their respective registers.

The resume routine at task 516 then calls the swap BIOS data area and vector table routine. Before this routine is called, the known BIOS data area and vector table are active in segment 0000H, and the BIOS data area and vector table read from the pause file are inactive in segment E000H. After exchange, the known BIOS data area and vector table are inactive in segment D000H and the BIOS data area and vector table kept by the suspend routine are active in segment 0000H.

Finally, in task 518 the resume routine jumps to the CPU recovery routine, so that the CPU 40 returns to the state before it was stopped. The CPU recovery routine will be described in more detail with reference to FIG. The CPU recovery routine eventually passes execution control back to APM.

Finally, the CPU 40 executes a RETURN instruction, causing the system to return to the APM. The system now continues executing code as if the system had not stopped at all. In practice, the system is not affected by the suspend / resume procedure.

Referring now to FIG. 13, a Save CPU State Routine is shown. In task 600, the stop routine jumps to the save CPU state routine.

Note that the APM enables to read / write the segments E000H and E000H where these routines are executed. Also, in task 602, EFLAGS and eight general purpose registers are stored by the APM. At task 604, the archiving CPU state routine first waits for any DMA operation to finish and synchronizes the mouse 13 data packet so that this routine is executed between the mouse packet and the transmission. DMA can be terminated and synchronized to a mouse packet by the following steps: (1) enable interrupts, (2) wait 7 milliseconds for any DMA to complete, and (3) Disable the interrupt, (4) wait 5 milliseconds until the mouse packet boundary, (5) enable the interrupt, (6) wait 5 milliseconds further until the mouse packet arrives, (7) Disable the interrupt. After these steps, the code runs safely between mouse packets.

In the next task 606, the state of the address line 20 (I / O port 92H) is pushed onto the stack.

The flow of execution code branches at task 1030 depending on whether CPU 40 is an S portion with SMI. If it is the S portion, the CPU 40 instructs the microcontroller U2 in the task 1032 to generate the SMI back to the CPU 40. In response to the SMI, the microcode in the CPU 40 keeps the state of the CPU 40 at task 1034 as E000: FE00H in the E000H data structure. CPU 40 then maintains the state of the floating point coprocessor at task 1036 and invokes a stop routine (FIG. 10) at task 1038. As described elsewhere herein, the abort routine returns from task 1040 and likewise recovers the state of the floating point coprocessor in task 1040. Then, at task 1042, the resume (RSM) instruction recovers the CPU state and then branches to task 732.

On the other hand, if the CPU 40 does not have SMI, the CPU state must be kept using the remainder of the FIG. 13 code, and the state of the numerical coprocessor 44 is pushed onto the stack in task 608. . Next, at task 610, a flag is set or cleared to indicate whether the CPU is running in 32-bit mode or 16-bit mode, respectively.

The flow of execution code branches at task 612 depending on whether the CPU 40 is running in a protected mode. If the CPU 40 is not running in a protected mode, it is clear that it is running in a real mode, and the registers can be stored in a straight forward manner. First, at task 614 the value in the machine status word and the value in CR3 are written to the segment E000H data structure. Further, in task 614, since TR and LDTR are zero in real mode, zero is recorded in the segment E000H data structure, which is an area corresponding to TR and LDTR.

The code then merges with the common code path at task 616 so that the values stored in the GDTR and LDTR are written to the segment E000H data structure. The flow of execution code then proceeds to task 618, branching according to whether or not CPU 40 is running in virtual 8086 mode. If the CPU 40 is not running in the virtual 8086 mode, the code proceeds to task 620 along a common path where the debug registers DR7, DR6, DR3, DR2, DR1 and DR0 are pushed onto the stack. . These registers are used by debuggers or other routines. Next, at task 622, DS, ES, FS, and GS are pushed onto the stack. The values in CS, SS and ESP are then written to the segment E000H data structure.

At this point, all the values that should be written to the segment E000H data structure have been written, so that, at task 626, shadow RAM segments E000H and F000H can be changed to read-only. Next, at task 628 the CPU cache 41 is flushed using the Write Back and Invalidate Cache command.

Ultimately, at task 630 a unique Shutdowu Flag is set in CMOS non-volatile memory 96. Finally, the save CPU state routine actually returns to the stop routine. In code, a return is actually a branch following a RESET. The CPU 40 is reset by jumping to the code indicated by the reset vector. Resetting the CPU 40 enters the CPU in real mode, where all devices and memory areas can be accessed without fear of occurrence of a protection fault.

After this point, the CPU state is saved and the stop routine must save the rest of the system.

In the code indicated by the reset vector, program control branches depending on whether or not a shutdown flag is set in the CMOS 96. If the shutdown flag is cleared, the system boots normally. On the other hand, if the shutdown flag is set, the code branches to the rest of the stop routine. In other words, execution control jumps to task 253 shown in FIG. 10 in the suspend routine to complete suspend of system 10. Thus, at task 632 the save CPU state routine effectively returns to the suspend routine.

Referring back to task 612, if the CPU is in protected mode, the code branches at task 634 depending on whether the CPU is in virtual 8086 mode. If the CPU is not in virtual 8086 mode, the code branches back to task 636 depending on whether the current privilege level is zero or not. If the current privilege is not zero, then a routine without proper privilege is executing a stored CPU state routine, and a Fatal Suspend Error Routine (starting at task 652) is called. Fatal stop error routines will be described below. If program control returns from the fatal stop error routine, the CPU must return to the state it was in before the stored CPU state routine was invoked, so that program execution branches to task 794 in FIG. 14 to partially recover the CPU. restore). Only partial recovery is needed because only a very small portion of the CPU has been modified.

Referring back to task 636, if the calling code has the appropriate privilege level, archiving continues in task 642 so that the values of CR0, CR3, TR, and LDTR are stored in the segment E000H data structure. Then, as described above, in task 616 this code is combined with the common code path so that the values of GDTR and IDTR are stored in the E0000H data structure. From there, the code follows the path of tasks 6B-632 described above, resulting in a return (RESET + branch) to the rest of the abort routine code.

Referring back to task 634, if CPU 40 is in virtual 8086 mode, execution continues at task 644 such that the value of machine status word (lower 16 bits of CR0) is stored in the E000H data structure. The flag in the segment E000H data structure is set to indicate that the CPU is in virtual 8086 mode. This code is then merged with common code in task 616 via transfer tasks 646 and 648. At task 618, when the CPU is in virtual 8086 mode, control branches to task 650 where the values of DE, ES, FS, and GS are stored in the segment E000H data structure. This code is merged back with the common code at task 624. From here, the code follows the paths 624 through 632 described above, resulting in a return (RESET + branch) to the remaining stop routine code.

The fatal stop error routine consists of tasks 652 through 664, which are called in task 638 when code with an inappropriate privilege level wishes to keep the state of the CPU. First, at task 654, the failsafe timer is reset. In task 656, the speaker then beeps several times at home frequency. For example, beep 3 times at 886 Hz for 0.25 seconds at 1/6 second intervals. Three beeps warn the user that no attempted outage has occurred. After the beep, the failsafe timer is reset again at task 658 to provide the user with 15 to 18 seconds before the failsafe timer is complete and power supply 17 shuts down.

Next, at tasks 660-662 the fatal stop error routine checks if the user presses the switch 21 and wants to give up the stop. The closing of the switch is checked by the CPU 40 querying the microcontroller U2 whether a closing event has occurred. When the user presses the button 21, execution control returns to the task 640 described above. In contrast, if the user does not press the button 21 within 15 to 18 seconds, the fail-safe timer is completed and the power is turned off by the microcontroller, and all code execution by the CPU 40 causes the system voltage to be Abort as the tolerance goes out.

Referring now to FIG. 14, a CPU restore routine starting from task 700 is shown. This routine is called by the resume routine after the rest of the hardware and memory has recovered from the state before the suspension.

First, if segment E000H is not yet read / write, segment E000H should be read / write at task 702.

Execution code then proceeds to task 704 and branches depending on whether it was running in virtual 8086 mode when CPU 40 was stopped. If the CPU 40 was running in the virtual 8086 mode when the system 10 was stopped, the execution code proceeds to tasks 706-728 that are specific to the virtual 8086 CPU restore.

The code then merges with the common path of tasks 730-748.

If the CPU was in virtual 8086 mode when state was archived, CR3, LDTR, and TR were accessed by the archive CPU state routine so that their values could not be stored in the E000H data structure. Thus, CR3, LDTR and TR must be estimated at tasks 706,708 and 710, respectively. In general, they are estimated by searching the system RAM 53 for the structure pointed to by CR3, LDTR, and TR. For example, LDTR can be determined by finding an LDT entry in the GDT.

CR3 is estimated at task 706. CR3 holds the Page Directory Base Register (PDTR), which is the directory's page frame address, the Page-Level Cache Disable (PCD) bit, and the page-level write-through. Page-Level Write Through: PWT) bit. The PDBR estimates that the page directory must start at the 4K boundary within the system RAM 53, knows the values of IDTR and GDTR stored in the segment E000H data structure by the archive CPU state routine, It is performed on the assumption that it is running from segment E000H. This assumption is valid because the BIOS code is already shadowed into shadow RAM to improve speed. If the operating system copies the BIOS code to another area, the estimation of CR3 may fail.

With the above knowledge and assumptions, every 4K pages of physical memory are tested to see if there is a page translation table corresponding to the BIOS code segment.

That is, an offset of 0380H to the page will contain the values 000F0XX, 000F1XXX, 000F2XXX, ... 000FEXXX. Once the location of the page is known, the system RAM 53 is searched to populate the page directory with the first entry corresponding to the physical address of the locationd page table. The physical address of the page directory is a good PDTR estimate.

The hypothetical PDBR is then verified by verifying that the PDBR correctly translates the addresses of the GDTR and LDTR. That is, PDBR is used to translate the linear address of the GDTR, and the first entry of the GDT is checked to be null (the first 8 bytes of the GDT are always 00H in all CPU modes). Then, it is checked whether the returned physical address is within the range of the physical memory. In order to achieve a linear to physical translation, a subroutine that mimics the CPU's translation method is used. The translated address is returned in the ESI, the carry flag CF is cleared if the physical page is in physical memory, and the CF is set if the physical page is not in memory. Using this conversion routine, the first byte of the GDT is read from the memory 53. If the first entry of the GDT is null, the hypothetical PDBR passes the first test and is therefore tested again.

The PDBR is then used to convert the IDTR to find the IDT using a conversion routine. Then, the returned physical address is checked to be within the range of the physical memory. If the first location of the IDT is in physical memory, the PDTR passes the second test.

If the hypothesis PDBR is correctly converted to GDTR and IDTR, the value is presumed as PDBR and recorded in the CR3 region in the segment E000H data structure. On the other hand, if hypothesis CR3 fails any of the tests, the routine is restarted to find another BIOS code segment page conversion table that may search the system memory and lead to a valid CR3.

PCD and PWT are always assumed to be fixed at 00H during normal planar operation. These values are set to zero and are recorded in the segment E000H data structure together with the PDBR of the CR3 area.

Once CR3 has been estimated, LDTR is estimated at task 708. Knowing that the LDT is somewhere in the GDT and knowing that the LDT should be in memory, the LDTR can be estimated when CR3 is estimated. To estimate the LDTR, the GDT is searched to find an LDT marked as present (tested using the conversion routine described with reference to task 706) and the first LDT marked as present is the LDTR. Is assumed to be the table pointed to by. The physical address of the beginning of this table is stored in the LDTR area in the segment E000H data structure.

Although under OS / 2, one or more LDTs may be marked as present and present in physical memory, it is believed that the above-described LDTR estimation method is sufficiently useful. EMM386 is a common Virtual 8086 Mode routine and, therefore, may appear to cause problems. However, since EMM386 has only one CR3 and one LDTR, the CR3 and LDTR of EMM386 are easy to estimate.

Once CR3 and LDTR are estimated, TR is estimated at task 710. Inevitably, each task selector entry in the GDT and LDT is searched to find a task state selector with a busy bit set. The type field of each entry is tested to determine whether it is a busy 80286 task state selector or a busy 80486 task state selector. The first entry with busy 286 TSS or busy 486 TSS is assumed to be the address indicated by TR. The physical address of an entry with a busy 286 or 486 TSS is stored in the TR field in the segment E000H data structure.

If no entry has a busy 286 or 486 TSS, 0 is stored in the TR field in the segment E000H data structure.

After estimating CR3, LDTR, and TR, the code continues at task 712. If the TR indicates a valid TSS at the task 714, the busy bit of the TSS indicated by the TR at task 714 is cleared. In either case, the code proceeds to task 716 where the DS, ES, FS and GS are loaded with valid selectors for the GDT. Then at task 718, CR3 and CR0 are loaded with values from the segment E000H data structure. Paging is then enabled at task 720 so that the only area where the linear address is equal to the physical address is the area within segments E000H and F000H. Then, in task 722, IDTR, GDTR, LDTR, and TR are loaded with the values stored in the segment E000H data structure.

Finally, in tasks 724 and 726, pushing the values corresponding to GS, FS, DS, ES, SS, ESP, EFLAGS and CS (after setting the W bit) from the segment E000H data structure (on the stack) by pushing a virtual 8086 interrupt stack. In addition, at task 726 a return address corresponding to the code of task 730 is pushed onto the stack. Finally, the IRETD instruction is executed to reposition the CPU 40 in virtual 8086 mode, and send execution to code corresponding to task 730.

Task 730 starts a common path that the various paths of FIG. 14 use in common. At task 730 coprocessor 44 is recovered using the values stored in segment E000H data structure. Next, at task 732, the state of address line 20 (I / O port 92H) is popped from the stack. Task 732 is also where the SMI-based CPU save state routine has jumped (see task 1046). Then, at task 734, shadow RAM segment E000H is again read-only. At task 736 the APM is connected to the hardware by restarting the solid state safety timer as described with reference to FIGS. 6A and 19. Then, at task 738, shadow RAM segments E000H and F000H are again read-only.

Finally, at task 740, the CPU state recovery routine sets a flag indicating that normal resume has occurred. Tasks 742, 744, and 746 are not executed by the CPU state recovery routine, and at some point before the return to code that was interrupted by the stop event, eight general purpose registers are popped off the stack (the code is Maskable interrupts are enabled when interrupted) Maskable interrupts are enabled and used to indicate that a flag is popped off the stack. Finally, the CPU state recovery routine returns to the supervision routine, which returns control back to APM, which updates all stale system values and returns control back to the code that was interrupted. Return

Referring back to task 704, if the CPU 40 was not in virtual 8086 mode at the time of interruption, the code proceeds to paths 750-792 and merges with the common paths of tasks 730-748. In task 750, if the TR value in the segment E000H data structure indicates that TR indicates a valid TSS, then in task 752 the busy bit of this TSS is cleared. In either case, at task 754, GDTR and CR0 are loaded with the values of the segment E000H data structure.

In tasks 756-764, a dummy page directory table and a page translation table are loaded into segment E000H. First, at task 756 the shadow RAM segment C000H is read / write. Second, in task 758 a new page directory table is created at address 0E0000H. Third, in task 760 the first entry of this new page directory table is modified to point to 0E1000H. Fourth, addresses 0E0000 through 0FFFFF are provided in task 762, where linear addresses are created in the new page translation table 0C1000H to be identical to the physical addresses. Finally, the page directory base register in CR3 is loaded with 0E0000H so that address translation is done via the new dummy page directory and page translation table in 0E0000H.

Next, at task 766, shadow RAM segments E000H and F000H are read / write. Then, if the CPU 40 was running 16-bit code when it was stopped, the CPU 40 was in 16-bit mode and at task 770 an offset pointing to the 16-bit code path. ) Is stored in the segment X000H data structure. On the other hand, if CPU 40 was not in 16-bit mode, this 1 CPU 40 was in 32-bit mode, pointing to the 32-bit code path instead of the 16-bit offset in task 772. The offset is stored in the segment E000H data structure. In any case, these code paths are parallel, with no difference except that one uses 16-bit operands and the other uses 32-bit operands. Tasks 770 through 772 simply set the offset to any of these parallel paths. One of these paths (one corresponding to the offset) enters task 782, which will be described later.

Next, in task 774 the CR3 value from the segment E000H data structure is loaded into EDX, the SS value of the segment E000H data structure is loaded into CX, the ESP value from the segment E000H data structure is loaded into EBP and the segment E000H data TR values from the structure are loaded into the upper half of ESI, and also LDTR values from the segment E000H data structure are loaded into the lower half of ESI (SI). . These values are shifted to their appropriate positions below. Task 776 then loads GDTR, LDTR, and CR0 with their values from the segment E000H data structure. In task 778 the LDTR is loaded with the LDTR value stored in the SI.

The code then jumps far to the offset placed in task 770 or 772. Far jumps place opcodes directly into source code and are coded using offsets from task 770 or 772. Then, at task 782, the code continues in either the 16-bit opcode path or the 82-bit opcode path.

Next, in task 784, CR3 is loaded with the CR3 value stored in EDX, SS value is loaded with the SS value stored in CX, and ESP is loaded with the ESP value stored in EBP.

Then, in task 786, GS, FS, ES, and DS are popped off the stack. If the CPU 40 interrupted at task 788 was executing code in protected mode, then at task 790 the TR is loaded with the TR value stored in the upper half of the ESI. In either case, the code continues at task 792 so that debug registers DR0, DR1, DR2, DR3, DR6, and DR7 are popped off the stack.

At this point, this code path is combined with the common code path consisting of the tasks 730-748 described above. The error-recovery routine at task 794 also combines with the common code path from task 640 of the archive CPU state routine.

Referring now to FIG. 15, a flow diagram of a archiving 8259 state routine beginning at task 800 is shown. The 8259 state preservation routine proceeds by storing the periodic interrupt value used by the real time clock 98 in task 802 and keeping all other readable registers in the segment E000H data structure in task 804. As is well known in the art, the structure of computer system 10 requires that certain 8259 read-only registers have a fixed value. These values are known and do not need to be determined. The hard-to-get 8259 values are the 8259 base address, the 8259 slave address, and whether the two 8259s are set to indicate an interrupt pending or in-service by the OS. Whether or not.

The four items described above are identified by the remaining code of FIG.

In task 806 8259 is interrupt masked, with the exception of the keyboard 12 and mouse 13 interrupts.

The interrupt vector table is then stored at task 808 by copying the bottom 1K of physical memory to the segment C000H data structure. Then, in task 810, by loading 256 unique cow dummy vectors pointing to 256 dummy interrupt service routines starting at segment C800H, a new dummy interrupt vector table is created. Loaded at base 1K. At task 812, 256 dummy interrupt service routines are generated in segment C800H.

The keyboard 12 and mouse 13 interrupts are then disabled at task 814. At task 816 all the unacknowledged keyboard 12 and mouse 13 interrupts are acknowledged.

Next, a keyboard interrupt occurs at task 818, and this interrupt at task 820 determines whether base 8259 is set to pending or in service.

This value is then written to the segment E000H data structure. In task 822, the code waits for the interrupt to be serviced. The interrupt is serviced by calling one of the dummy service routines in task 824. The call to the dummy service routine determines the 8259 base address and determines whether the 8259 is in the pending mode or in service mode. The base address and mode are stored in the segment E000H data structure.

Similar procedures are performed for slave 8259 in tasks 826, 828, 830, and 832.

At task 834, the interrupt vector table is recovered by copying the value of the E0000H data structure back to base 1K of physical memory. Thereafter, in task 836 segment C000H is read-only again, and all interrupts are masked in task 838 in preparation for return to the calling program in task 840.

Referring to FIG. 16, there is shown a routine used to dynamically allocate a pause file. As described in connection with task 1012, the pause file allocated in the FAT should allow for fast writes to and read from the disc during contiguous sectors followed by pause and resume. Also, as will be apparent to those skilled in the art, the pause file should be large enough to store the compressed contents of the overall system state.

For this purpose, a routine is initiated at task 1050 to dynamically allocate a pause file. This routine is executed by the OS whenever the system is booted without executing the resume routine, and must be executed after memory has been added to the system. First, the allocation routine shown in FIG. 16 tests at task 1052 whether a power management circuit exists by checking a flag in the CMOS NVRAM. If power management hardware 106 does not exist, the program exits at task 1054. If power management hardware 106 is present, the allocation routine checks at task 1056 whether the resume is pending. If resume is pending, the program exits at task 1058.

If not resumed, the allocation routine tests task 1060 whether a Save File Partition exists. If there is an archive file partition, at task 1062 the program exits assuming that this partition is large enough to hold the entire system state.

If the archive file partition does not exist, a file must be allocated in the FAT for the archive file. First, the task 1064 determines the file size. This is the size of the system RAM 53, the size of the video memory 58, the size of any other device having a large volatile memory capacity, and 64 for storing values in registers of various devices, such as the CPU 40. Calculated by adding the kilobyte area.

After the size of the required archive file is calculated, the allocation routine attempts to allocate the archive file in the FAT at task 1066. If there is not enough storage space available on hard drive 31, the allocation routine calls one routine at task 1070 to increase the amount of available space on hard drive 31 if possible.

DOS calls cannot guarantee that consecutive sectors are allocated in a file. Thus, if hard drive 31 has enough space to store the archive, the allocation routine determines at task 1072 whether this space is contiguous. If the archive file is fragmented (not contiguous), the allocation routine calls a routine in task 1074 to provide a continuous file to the archive file that is possible by defragmenting the hard drive.

If the archive is not fragmented, the allocation routine writes a signature (PS Power Management) to the first sector of the archive at task 1076. The allocation routine then converts the DOS handle of the file to the BIOS's physical cylinders, heads, and sectors in task 1078, and writes these values to the CMOS NWAM. The allocation routine exits at task 1080.

The routine called in task 1074 to serialize the hard drive 81 begins in task 1082 and continues through task 1094. First, at task 1084 it is determined whether the hard drive 31 is compressed using one of the hard drive compression routines well known to those skilled in the art.

If the hard drive 31 is not compressed, at task 1086 the entire hard drive 31 is serialized using a defragmentingg utility that is well known to those skilled in the art. This routine then returns from task 1088 to start a new portion of the allocation routine in task 1090.

If the hard drive 31 is compressed, then the compressed portion of the hard disk is minimized at task 1092. The uncompressed portion of hard drive 31 is then defragmented at task 1094 using a serialization utility that is well known to those skilled in the art.

This routine then returns from task 1088 to start a new portion of the allocation routine in task 1090.

The routine called in task 1070 to increase the available space on hard drive 31 begins in task 1100 and continues through task 1110. First, at task 1102 it is determined whether hard drive 31 is compressed using one of the hard drive compression routines well known to those skilled in the art.

If the hard drive 31 is not compressed, the hard drive 31 does not have enough space available for the archive, so a message is displayed at task 1104 to simultaneously use the suspend and resume feature. The user is informed that they need to add drive capacity or delete files from the hard drive 31.

If the hard drive 31 is compressed, the size of the uncompressed portion of the hard drive 31 is increased if possible at task 1108. This routine then returns from task 1110 and starts a new allocation of assignment routines in task 1090.

Referring now to FIG. 17, a routine for exiting from a waiting state is shown starting at task 1120. Conceptually, when the system exits from the standby state 152, the system reverses the changes that were caused when the system transitioned from the normal operating state 150 to the standby state 152. In summary, when the system leaves the standby state 152, the system recovers the video signal, illuminates the LED 23, rotates the hard disk in the hard drive 31, recovers the system clock, and APM. Disable the CPU idle call so that the CPU idle call from the APM driver no longer stops the CPU 40 and clears the flag indicating that the system 10 is in standby state 152.

First, this routine tests at task 1122 if a checkpoint was generated when the system entered standby state 152. If a checkpoint has occurred, the checkpoint taken bit is cleared at task 1124 to indicate that the checkpoint is no longer valid. In this particular embodiment, the checkpoint is invalidated when the system leaves the standby state. Checkpoint data was only used to resume the system if it failed while the system was in standby (152) because most systems use virtual swap files on the hard drive and checkpoints Resuming from data may cause the system to be in a state where the exchange file is completely different than expected by the system state (stored as checkpoint data). As an alternative, the checkpoint data can be invalidated after the next disk access. As another alternative, the checkpoint data may be invalidated after disk access to the file, which may cause system problems if the system is resumed from the checkpoint data. Alternatively, checkpoint data may always be available to the user, with the understanding that resumption from checkpoint data may result in the loss of some or all of the data on hard drive 31.

Then, if no checkpoint is taken, the CPU 40 instructs the microcontroller U2 at task 1126, which causes the microcontroller U2 to (i) cause the video controller 56 to replay the video signal. Occurs once, (ii) causes the clock synthesizer 906 to resume a higher frequency system clock (25 Hz or 33 Hz), and (iii) illuminates the LED 23. CPU 40 then rotates the hard disk in hard drive 31 by writing an appropriate value to fixed disk controller 86 at task 1128.

Next, in task 1130, the APM CPU idle call is disabled so that a CPU stop does not occur. Finally, the wait flag is cleared at task 1132 to indicate that system 10 is in a normal operating state 150. The routine returns to the calling program at task 1140.

Referring to FIG. 18, a routine for entering a standby state is shown starting at task 1140. In summary, when the system enters the standby state 152, the system blanks the video signal, flashes the LEDs 23, spins down the hard disk in the hard drive 31, and slows down the system clock. Enable the APM CPU idle call to cause the CPU idle call from the APM driver to stop the CPU 40, and set a flag indicating that the system 10 is in the standby state 152.

First, this routine tests whether a checkpoint is taken at task 1142. If a checkpoint is to be taken, most of the stop routines are executed in task 1144 such that the state of computer system 10 is stored on hard drive 31. In this embodiment, a checkpoint is taken when the system enters a standby state. Alternatively, under the precautions described with reference to FIG. 17, checkpoints can be taken periodically and used to restart the system. Then, at task 1146, the resume routine is sufficiently executed to recover from the partial suspension performed at task 1144.

Then, at task 1148, the Checkpoint Taken bit is set to indicate that a valid checkpoint has been taken. Recall that in this embodiment the checkpoint data is used only if the system fails while in standby state 152. In this case, as the system boots, the system resumes from an archived checkpoint.

Ideally, checkpoints should be completely transparent to the system. In this way, if a hardware interrupt occurs to prevent data loss, the checkpoint must be abandoned. As an alternative, all hardware interrupts can be ignored, as in the case of normal shutdown.

Then, if no checkpoint has also been taken, the CPU 40 instructs the microcontroller U2 at task 1150 so that the microcontroller U2 causes (i) the video controller 56 to output a video signal. Ceases to occur, (ii) causes the clock synthesizer 906 to lower the system clock from a higher frequency (25 MHz or 33 MHz) to a lower frequency (8 MHz), and (iii) turns the LED 23 on. Flash it. CPU 40 then writes the appropriate value to fixed disk controller 86 at task 1152 to stop rotation of the hard disk in hard drive 31. Next, in task 1154, the APM CPU idle call is enabled, causing the CPU idle call from the APM driver to stop the CPU 40. Finally, a wait flag is set in task 1156 to indicate that system 10 is in a wait state 152. This routine returns to the calling program at task 1158.

While the present invention has been illustrated by describing the embodiments, these embodiments have been described in considerable detail, but the applicant is not intended to limit the appended claims to the detailed description of the invention. Those skilled in the art will clearly recognize additional advantages and modifications. For example, as described above, the data may be compressed using a run length encoding technique before writing the data to the hard disk. Alternatively, any suitable compression method may be used or no compression method may be used at all. Therefore, the invention is not limited to the specific details, representative apparatus and methods, and examples illustrated and described. Accordingly, modifications may be made to these details without departing from the spirit and scope of Applicant's general inventive concept.

Claims (20)

In a computer system, (a) CPU for executing operating system code, application code, and BIOS code, the operating system code controlling power management state transitions and periodically causing power management supervision routines to be executed, wherein the BIOS code executes power management state transitions. And in normal operation, the operating system stops the power management supervision routine from running under certain conditions. (b) power management circuitry in circuit communication with the CPU and selectively changing a state of the computer system between a normal operating state and a suspended state in response to at least one preselected set of stop events; (c) an inactivity suspend timer in circuit communication with the CPU, the inactivity suspend timer being set to expire after a first preselected time period and tested for expiration by the power management supervision routine, wherein the first preselected time period is in the suspended state. Corresponds to the length of time of user inactivity that causes the transition of-and, (d) a backup stop timer in circuit communication with the CPU and configured to expire after a second preselected time interval and whose expiration is tested independent of the power management supervision routine, wherein the second preselected time interval is inactive Corresponds to the length of time since the stop timer has been tested for expiration-Wah, (e) an electromechanical non-volatile storage device in circuit communication with the CPU and not requiring electrical power to maintain data stored therein; (f) a volatile system memory in circuit communication with the CPU and storing memory data; (g) a volatile system register in circuit communication with the CPU and storing register data; (h) in circuit communication with the CPU and the power management circuitry and selectively system power from an external source to the CPU, the electromechanical nonvolatile storage, the volatile system memory, and the volatile system register in response to the power management circuitry. A power supply having a first power supply state and a second power supply state, and having a circuit for supplying auxiliary power to the power management circuitry, wherein the first power supply state is the power supply; Supplies system power to the CPU, the electromechanical nonvolatile storage, the volatile system memory, and the volatile system register from an external source, supplies auxiliary power to the power management circuitry, and wherein the second power state is such that Electromechanical non-volatile storage from the external source, the volatile System memory, the system does not supply the power to the volatile system registers, and an auxiliary power to said power management circuit is supplied from the external source, (1) the normal operating state is characterized in that the power source is in the first power state and the computer system executes code; (2) the suspended state is characterized in that the register data and the memory data have been transferred by the CPU to the electromechanical nonvolatile storage device, and the power source is in the second power state, (3) said transition from said normal operating state to said stopped state causes said CPU to copy memory data and register data from said system memory and said system register to said electromechanical nonvolatile storage device in response to said preselected stop event. Include, (4) the transition between the normal operating state and the suspended state each includes causing the control unit to switch between the first power state and the second power state in response to the preselected stop event; , (5) a first stop event of the preselected stop event includes completion of the backup stop timer; (6) a second stop event of the preselected stop event comprises completion of the inactivity timer. The method of claim 1, And a momentary pushbutton switch in circuit communication with the power management circuitry, the instantaneous pushbutton switch generating a closure event in response to being pressed, wherein the power management supervision routine tests for the closing event of the switch, and The other stop event selected includes a close event of the switch. The method of claim 1, The power management circuitry includes a power management processor, the power management processor having the backup stop timer located therein. The method of claim 1, An instantaneous pushbutton switch in circuit communication with the power management circuitry and generating a close event in response to being pressed, wherein the power management supervision routine tests for a close event of the switch and the first stop event is the backup stop timer; And expiration of and closing event of the switch. The method of claim 1, The power management circuitry includes a power management processor having a preprogrammed microcontroller. The method of claim 1, And the backup stop timer is resumed or otherwise reset in response to the power management portion of the operating system being executed. The method of claim 3, wherein The power management processor includes a preprogrammed microcontroller. The method of claim 1, The electromechanical nonvolatile storage device includes a fixed disk storage device. The method of claim 1, And the power source is directly connected through an electrical conductor to the CPU, the volatile system memory, the volatile system register, and the electromechanical nonvolatile storage device. According to claim 1, The power supply does not supply auxiliary power to the power management circuitry when power from an external source to the power supply is interrupted. At least two power management states: (i) a normal operating state in which code is normally executed by the computer system, and (ii) a power couservation that consumes less power than when the computer system is in the normal operating state. A method of managing power usage by a computer system in a computer system having a status of: (a) executing an operating system having a power management driver on the computer system, the operating system being configured to execute an application program. Interrupts execution periodically so that the power management supervision routine is executed, and in normal operation the operating system stops executing the power management supervision routine under certain conditions. (b) starting an inactivity timer that expires after a first preselected time interval; (c) starting a backup inactivity timer that expires after a second preselected time period; (d) operating the computer system in a normal operating state; (e) resuming an inactivity timer in response to user activity occurring while the computer system is in a normal operating state; (f) testing, by the power management supervision routine, whether the inactivity timer has completed, (g) resuming a backup inactivity timer in response to the execution of a power management oversight routine; (h) in response to expiration of the first time interval, transitioning the computer system to a power saving state by executing at least one of a power management driver and a power management supervision routine; (i) transitioning said computer system to a power saving state without at least partially responding to completion of a second time interval, without causing an operating system to execute a power management supervision routine. The method of claim 11, (a) responding to the expiration of a first time period during operation of the computer system by communicating, via an operating system's power management driver, that at least one peripheral device is in transition with a power management state to be imminent; (b) a second time during which the computer system is operating by transitioning the computer system to a power saving state without the operating system's power management driver communicating with at least one peripheral device that the transition from the power management state is imminent. And responding to the expiration of the interval. The method of claim 12, And the at least one peripheral device executes a task associated with transitioning from a power management state of the computer system in response to communication from a power management driver of an operating system. The method of claim 11, And wherein the second preselected time interval is longer than the longest interval between periodic executions of the power management supervision routine by the power management driver of the operating system. The method of claim 11, And the second preselected time interval is about 18 seconds. The method of claim 11, The computer system further includes a processing device, wherein code execution by the processing device is interrupted in the power saving state, the state of the computer system is stored in a nonvolatile memory, and the computer system is in the normal operating state. Multi power usage management method that consumes less electrical power. The method of claim 11, The computer system includes a central processing unit, a memory, a fixed disk storage device, a power source, wherein the power source selectively supplies system power to the central processing unit, the memory, the fixed disk storage device from an external source, and the computer The step of transitioning a system to a power saving state includes: identifying a system state of the computer system, storing the system state in the fixed disk storage device, and storing system power from a power source to the central processing unit and the memory. And stopping delivery to the fixed disk storage device. At least three power management states, i.e., a normal operating state in which code is normally executed by the computer system, and (ii) code execution by the computer system continues and the computer system is in the normal operating state. A standby state that consumes less electrical power, and (iii) code execution by the computer system is interrupted, the state of the computer system is stored in an electromechanical nonvolatile memory, and the computer system is in the standby state. A computer system having a suspended state that consumes less electrical power than the method of managing power usage by the computer system, the method comprising: (a) running an operating system on the computer system having a power management driver, the operating system periodically interrupting the execution of a given application, causing a power management supervision routine to run, and under the operating system specific conditions Stops the power management supervision routine from running-and, (b) starting an inactivity wait timer that expires after a first preselected time period; (c) starting an inactivity stop timer that expires after a second preselected time period; (d) starting a backup stop timer that expires after a third preselected time period; (e) operating the computer system in a normal operating state; (f) resuming the inactivity wait timer and the inactivity stop timer in response to user activity occurring while the computer system is in a normal operating state; (g) testing, by a power management oversight routine, whether the inactivity stop timer has expired; (h) resuming a backup stop timer in response to the execution of a power management oversight routine; (i) transitioning a state of the computer system from a standby state to a normal operating state in response to user activity occurring while the computer system is in a standby state; (j) transitioning the computer system to standby in response to expiration of the first time period during operation of the computer system; (k) in response to expiration of the second time interval, transitioning the computer system to a suspended state by executing at least one of a power management driver and a power management supervision routine; (l) transitioning the computer system to a stopped state, at least partially in response to expiration of the third time interval, without causing an operating system to execute a power management supervision routine. The method of claim 1, In response to the expiration of the backup suspend timer, the inactivity suspend timer is tested for expiration, and if the inactivity suspend timer has expired, the computer system transitions to the suspend state. At least two power management states: (i) a normal operating state in which code is normally executed by the computer system, and (ii) a power conservation that consumes less power than when the computer system is in the normal operating state. In a computer system having (a) means for running an operating system having a power management driver on the computer system, the operating system periodically interrupting the execution of a given application, causing a power management supervision routine to run, and operating the operating system in a normal operating state. The system ceases to allow the power management supervision routine to run under certain conditions. (b) means for starting an inactivity timer that expires after the first preselected time period; (c) means for starting a backup inactivity timer that expires after a second preselected time period; (d) means for operating the computer system in a normal operating state; (e) means for resuming an inactivity timer in response to user activity occurring while the computer system is in a normal operating state; (f) means for testing whether the inactivity timer has completed by the power management supervision routine, (g) means for resuming a backup inactivity timer in response to the execution of a power management oversight routine; (h) means for transitioning the computer system to a power saving state by execution of at least one of a power management driver and a power management supervision routine in response to expiration of the first time interval; (i) means for transitioning said computer system to a power saving state, at least partially in response to expiration of a second time interval, without causing an operating system to execute a power management supervision routine.