KR100190194B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100190194B1 KR100190194B1 KR1019950066016A KR19950066016A KR100190194B1 KR 100190194 B1 KR100190194 B1 KR 100190194B1 KR 1019950066016 A KR1019950066016 A KR 1019950066016A KR 19950066016 A KR19950066016 A KR 19950066016A KR 100190194 B1 KR100190194 B1 KR 100190194B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 소자분리 절연막의 단부를 선택적 에피택시 성장과 다결정 폴리실리콘 증착공정을 이용하여 전하저장 콘택형성시 콘택홀의 하부로부터 노출되는 것으로부터 보호함으로써 디램의 리플레쉬 특성 및 반도체 소자의 콘택 정션 리키지를 향상시킬 수 있는 방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein the end portion of the device isolation insulating film is protected from being exposed from the bottom of the contact hole during charge storage contact formation using selective epitaxy growth and polycrystalline polysilicon deposition. It is a method which can improve the characteristic and the contact junction package of a semiconductor element.
Description
제1a도는 종래의 기술에 따라 전자저장 콘택이 형성된 반도체 디램소자의 단면도.1A is a cross-sectional view of a semiconductor DRAM device in which an electron storage contact is formed in accordance with the prior art.
제1b도는 제1a도의 A부 상세도FIG. 1B is a detailed view of part A of FIG. 1A
제2a도와 제2b도는 본 발명의 제1 실시예에 따른 전하저장 콘택홀 제조공정 단면도.2A and 2B are cross-sectional views of a process for manufacturing a charge storage contact hole according to a first embodiment of the present invention.
제3a도 내지 제3c도는 본 발명의 제2 실시예에 따른 전하저장 콘택홀 제조공정 단면도.3A to 3C are cross-sectional views of a process for manufacturing a charge storage contact hole according to a second embodiment of the present invention.
제4a도와 제4b도는 본 발명의 제3 실시예에 따른 전하저장 콘택홀 제조공정 단면도.4A and 4B are cross-sectional views of a manufacturing process of a charge storage contact hole according to a third exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 소자분리 절연막1 semiconductor substrate 2 device isolation insulating film
3 : 게이트 산화막 4 : 게이트3: gate oxide film 4: gate
5 : 스페이서(Spacer) 6 : 소오스/드레인5: Spacer 6: Source / Drain
7 : 절연막 8 : 전하저장 콘택홀7 insulating film 8 charge storage contact hole
9 : 전하저장 전극 10 : 유전체9 charge storage electrode 10 dielectric
11 : 커패시터 프레이터 13 : 단결정층11 capacitor capacitor 13 single crystal layer
14 : 감광막14 photosensitive film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 소자분리 절연막의 단부를 선택적 에피택시 성장과 다결정 폴리실리콘 증착공정을 이용하여 전하저장 콘택형성시 콘택홀의 하부로부터 노출되는 것으로부터 보호함으로써 디램의 리프레쉬(Refresh) 특성 및 반도체 소자의 콘택정션 리키지(Juction Leakage)를 향상시킬 수 있는 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to protect the end of the device isolation insulating film from being exposed from the bottom of the contact hole during charge storage contact formation using selective epitaxy growth and polycrystalline polysilicon deposition process. The present invention relates to a semiconductor device manufacturing method capable of improving refresh characteristics and contact leakage of a semiconductor device.
반도체소자가 점점 고집적화되면서 소자의 리프레쉬 특성은 제품 특성을 결정하는 중요한 요소의 하나로서, 상기 리프레쉬 특성은 일반적으로 전하저장 부위의 콘택특성에 의해 결정된다.As semiconductor devices are increasingly integrated, the refresh characteristics of the devices are one of important factors for determining product characteristics. The refresh characteristics are generally determined by the contact characteristics of the charge storage region.
제1a도는 종래의 기술에 따라 형성된 DRAM의 단면도를 도시한 도면이다.1A is a diagram showing a cross-sectional view of a DRAM formed according to the prior art.
상기 제1a도를 참조하면, 반도체기판(1) 상부에 종래의 일반적인 공정을 따라 소자분리 절연막(2)을 형성한 후, 전체구조 상부에 절연막(7)을 형성한 다음, 콘택 마스크를 사용하여 하부 절연막(7)을 식각하여 콘택홀(8)을 형성한 다음, 상기 콘택홀(8)을 이용하여 전하저장전극(9)을 소오스/드레인 영역(6)의 상부에 형성한 상태를 도시하고 있다.Referring to FIG. 1A, after the device isolation insulating film 2 is formed on the semiconductor substrate 1 according to a conventional general process, the insulating film 7 is formed on the entire structure, and then using a contact mask. The lower insulating film 7 is etched to form the contact hole 8, and then the charge storage electrode 9 is formed on the source / drain region 6 using the contact hole 8. have.
이때, 상기 전하저장 전극(9)의 상부에는 유전체막(10)이 얇게 도포되고 그 상부의 전면에는 커패시터 프레이터(11)가 소정두께로 형성되어 있다.In this case, the dielectric film 10 is thinly coated on the charge storage electrode 9, and the capacitor prater 11 is formed to a predetermined thickness on the entire surface of the upper portion of the charge storage electrode 9.
제1b도는 상기 제1a도의 A부 상세도로서, 소자분리 절연막(2)의 단부에 형성된 콘택홀(8)의 상태를 도시한 도면이다.FIG. 1B is a detailed view of the portion A of FIG. 1A and shows the state of the contact hole 8 formed at the end of the device isolation insulating film 2.
DRAM이 점점 고집적화 될 수록 상기 제1b도 나타낸 것과 같이 전하저장콘택(8)이 소자분리 절연막 끝부위를 손상시킨다.As the DRAM becomes more highly integrated, as shown in FIG. 1B, the charge storage contact 8 damages the end portion of the isolation layer.
상기 소자분리 절연막(2)의 단부는 통상 결정 결함이 많이 존재하며 이 부위에 결정 결함을 유발시킬 수 있는 건식식각 공정이 일어나면 전기적으로 아주 취약하게 되어 DRAM에서의 리프레쉬 특성을 급격히 저하시키게 되는 문제점이 있다.In the end portion of the isolation layer 2, there are usually many crystal defects, and when the dry etching process that causes the crystal defects occurs at the end of the device isolation insulating film 2, it becomes electrically weak and causes a drastic reduction in the refresh characteristics of the DRAM. have.
따라서 본 발명은 상기의 문제점을 해결하기 위하여 소자분리 절연막의 단부를 선택적 에피텍시 성장과 다결정 폴리 실리콘 증착과 같은 기존의 공정을 이용하여 전하저장콘택 형성을 위한 건식식각으로부터 보호함으로써 디램의 리프레쉬 특성 및 반도체소자의 콘택 정션 리키지를 향상할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Therefore, in order to solve the above problems, the present invention protects the end of the device isolation insulating film from dry etching for forming a charge storage contact by using conventional processes such as selective epitaxial growth and polycrystalline polysilicon deposition. And to provide a method for manufacturing a semiconductor device that can improve the contact junction of the semiconductor device.
상기 목적을 달성하기 위한 본 발명의 특징은 반도체기판 상부에 공지의 기술로 소자분리 절연막을 형성하는 단계와, 노출된 반도체 기판의 상부에만 소정두께의 단결정 반도체 필름을 성장시키는 단계와, 전체구조 상부에 절연막을 형성하는 단계와, 콘택 마스크를 사용하여 하부의 절연막을 식각하여 콘택홀을 형성하는 단계와, 상기 노출된 큰택홀을 이용 전하저장 콘택을 형성하는 단계를 구비함에 있다.Features of the present invention for achieving the above object is the step of forming a device isolation insulating film on the semiconductor substrate by a known technique, the step of growing a single crystal semiconductor film of a predetermined thickness only on the exposed semiconductor substrate, Forming an insulating film on the substrate; forming a contact hole by etching the lower insulating film using a contact mask; and forming a charge storage contact using the exposed large contact hole.
상기 목적을 달성하기 위한 본 발명의 다른 특징은 반도체기판 상부에 공지의 기술로 소자분리 절연막을 형성하는 단계와, 전체구조 상부에 다결정 반도체 층을 증착하는 단계와, 상기 다결정 반도체 층을 고온 열처리로 단결정화하는 단계와, CMP 공정으로 상기 소자분리막 상부의 증착층을 제거하는 단계와, 전체구조 상부에 절연막을 형성하는 단계와, 콘택 마스크를 사용하여 하부의 절연막을 식각하여 콘택홀을 형성하는 단계와, 상기 노출된 콘택홀을 이용 전하저장 콘택을 형성하는 단계를 구비함에 있다.Another feature of the present invention for achieving the above object is the step of forming a device isolation insulating film on the semiconductor substrate by a known technique, the step of depositing a polycrystalline semiconductor layer on the entire structure, and the high temperature heat treatment of the polycrystalline semiconductor layer Single crystallization, removing the deposition layer on the device isolation layer by a CMP process, forming an insulating film on the entire structure, and forming a contact hole by etching the lower insulating film using a contact mask And forming a charge storage contact using the exposed contact hole.
이하 첨부된 도면을 참조하여 본 발명의 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a도 내지 제2b도는 본 발명의 제1 실시예를 도시한 것으로서, 제2a도는 반도체기판(1) 상부에 기존의 소자분리방법으로 소자분리 절연막(2)을 형성하고, 선택적 에피텍시 성장법으로 일정두께의 단결정 반도체 필름(12)을 반도체기판(1) 위에만 성장시킨 상태의 단면도이다.2a to 2b show a first embodiment of the present invention, and FIG. 2a shows a device isolation insulating film 2 formed over the semiconductor substrate 1 by a conventional device isolation method, and selective epitaxial growth. It is sectional drawing in the state in which the single crystal semiconductor film 12 of constant thickness was grown only on the semiconductor substrate 1 by the method.
제2b도는 상기 구조에서 기존의 디램 제조공정으로 전하저장콘택(8)을 형성한 상태를 나타내고 있다.2b shows a state in which the charge storage contact 8 is formed by the conventional DRAM manufacturing process in the above structure.
상기 제1b도와 비교하면 선택적 에피텍시 성장과 단결정 성장에 의해서 소자분리 절연막(2)의 단부가 콘택 건식식각에 노출되지 않고 보호될 수 있는 것을 알 수 있다.Compared with FIG. 1b, it can be seen that the end of the isolation layer 2 can be protected without being exposed to contact dry etching by selective epitaxy growth and single crystal growth.
제3a도 내지 제3c도는 본 발명의 제2 실시예를 도시한 제조 공정도로서, 반도체기판(1) 상부에 선택적 에피텍시 성장법 혹은 다결정반도체 층을 증착한 후 고온 열처리로 단결정화 한 후, 화학적 물리적 마멸법(Chemical Mechanical Polishing; 이하 CMP 라 칭함.)으로 소자 활성화영역을 제거한 지역 즉, 소자 격리 절연막 상부의 성장층 혹은 증착층을 제거하는 제조공정을 나타낸 단면도이다.3A to 3C are manufacturing process diagrams illustrating a second embodiment of the present invention. After the selective epitaxial growth method or the polycrystalline semiconductor layer is deposited on the semiconductor substrate 1, it is subjected to monocrystallization by high temperature heat treatment. A cross-sectional view showing a manufacturing process of removing a growth layer or a deposition layer on an element isolation region, that is, a region in which an element activation region is removed by chemical mechanical polishing (hereinafter referred to as CMP).
제3a도는 반도체기판(1) 상부에 기존의 소자분리 방법으로 소자분리 절연막(2)을 일정부위에 형성하고 선택적 에피텍시 성장법으로 반도체 기판(1) 전면에 단결정층(13)을 증착시키거나 혹은 다결정층을 전면에 증착한 후 고온 열처리로 반도체기판(1)과 같은 결정 구조를 갖는 단결정막(13)을 형성한 상태의 단면도이다.3A illustrates a device isolation insulating film 2 formed on a predetermined portion of the semiconductor substrate 1 by a conventional device isolation method, and a single crystal layer 13 deposited on the entire surface of the semiconductor substrate 1 by a selective epitaxial growth method. Or a single crystal film 13 having a crystal structure similar to that of the semiconductor substrate 1 by a high temperature heat treatment after the polycrystalline layer is deposited on the entire surface.
제3b도는 상기 증착층(13)을 CMP 공정으로 소자분리 절연막(2) 위의 단결정층(13)만 제거한 상태의 단면도이다.3B is a cross-sectional view of the deposition layer 13 in a state where only the single crystal layer 13 on the device isolation insulating film 2 is removed by the CMP process.
제3c도는 전체구조 상부에 절연막(7)을 형성한 후, 마스크 공정을 통해 상기 절연막(7)을 식각하여 전하저장 콘택(8)을 형성한 상태의 단면도이다.3C is a cross-sectional view of a state in which the charge storage contact 8 is formed by etching the insulating film 7 after the insulating film 7 is formed over the entire structure.
상기 제3c도에는 상기 공정을 통해 소자분리 절연막(2)의 끝부위가 콘택(8) 건식식각에 노출되지 않고 보호되는 것을 알 수 있다.In FIG. 3C, it can be seen that the end portion of the isolation layer 2 is protected without being exposed to the dry etching of the contact 8 through the above process.
제4a와 제4b도는 본 발명의 제3 실시예를 도시한 제조 공정도 이다.4A and 4B are manufacturing process diagrams showing a third embodiment of the present invention.
제4a도를 참조하면, 상기 제3a도에 도시된 공정을 통해서 반도체 기판(1) 전면에 증착된 단결정층(13)을 포토 감광막(14)을 사용하여 건식식각으로 소자분리 절연막(2) 상부의 단결정층(13)을 제거한 상태의 단면도이다.Referring to FIG. 4A, the single crystal layer 13 deposited on the entire surface of the semiconductor substrate 1 through the process shown in FIG. 3A is dry-etched using the photosensitive film 14 to form an upper portion of the isolation layer 2 It is sectional drawing of the state which removed the single crystal layer 13 of.
제4b도는 전체구조 상부에 소정두께의 절연막(7)을 형성한 다음, 콘택 마스크를 이용 상기 절연막(7)을 식각하여 전하저장 콘택(8)을 형성한 상태의 단면도이다.4B is a cross-sectional view of a state in which a charge storage contact 8 is formed by forming an insulating film 7 having a predetermined thickness on the entire structure and then etching the insulating film 7 using a contact mask.
상기의 경우에 있어서도 상기 제2b도와 제3c도와 마찬가지로 소자분리 절연막 끝부위가 콘택(8) 건식식각에 노출되지 않고 보호되는 것을 알 수 있다.Also in the above case, it can be seen that the end of the device isolation insulating film is protected without being exposed to the dry etching of the contact 8, similarly to the above-described second and third embodiments.
따라서 소자분리 절연막(7)의 단부를 반도체 단결정으로 보호함으로써 콘택 건식식각에 의한 반도체소자의 전기적 특성 저하를 방지할 수 있다.Therefore, by protecting the end portion of the device isolation insulating film 7 with a semiconductor single crystal, it is possible to prevent the electrical characteristics of the semiconductor device from deteriorating by contact dry etching.
이상 상술한 바와 같이 본 발명에 따른 반도체 소자의 제조방법은 소자분리 절연막의 단부를 반도체 단결정으로 보호함으로써 콘택이 소자 분리막의 끝부위에 형성될 경우 콘택이 형성된 부위의 전기적 특성을 저하시키게 되는 문제를 해결할 수 있다.As described above, the method of manufacturing a semiconductor device according to the present invention protects the end of the device isolation insulating film with a semiconductor single crystal, thereby reducing the electrical characteristics of the contact formed portion when the contact is formed at the end of the device isolation film. I can solve it.
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KR102105267B1 (en) | 2019-07-23 | 2020-04-27 | 김정식 | Golf clubs with reference system for improved accuracy for address |
KR102279116B1 (en) | 2021-04-08 | 2021-07-19 | 김정식 | Golf club base system |
-
1995
- 1995-12-29 KR KR1019950066016A patent/KR100190194B1/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102105267B1 (en) | 2019-07-23 | 2020-04-27 | 김정식 | Golf clubs with reference system for improved accuracy for address |
KR102279116B1 (en) | 2021-04-08 | 2021-07-19 | 김정식 | Golf club base system |
Also Published As
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KR970054110A (en) | 1997-07-31 |
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