KR100188093B1 - High speed bicmos transistor and manufactruing method thereof - Google Patents

Abstract

The present invention relates to a high-speed BiCMOS transistor and a method of manufacturing the same, wherein a second conductivity type bipolar region, a first conductivity type first MOS region, a second conductivity type second MOS region, and an isolation portion to isolate the regions are formed. A first process of forming two base electrodes separated from each other by a first conductivity type polycrystalline silicon and an oxide film thereon on a semiconductor substrate, and diffusing impurities of the base electrode to a substrate of the bipolar region to form an outer base diffusion layer A second step, a third step of forming a gate oxide film in the MOS region, polycrystalline silicon is deposited on the entire surface of the semiconductor substrate, and selectively etched to protect the gate oxide film of the MOS region, and to form a polycrystalline silicon sidewall of the bipolar region A fourth step of forming a base region by implanting ions into the substrate between the two base electrodes Step 5 After laminating polycrystalline silicon on the entire surface of the semiconductor substrate, the doped and etched electrode is insulated with an oxide film formed on the base electrode between the two base electrodes and the collector electrode insulated from the emitter electrode. And a sixth step of forming respective gate electrodes in the gate oxide films of the first MOS region and the second MOS region so as to be insulated from each other and forming an emitter diffusion layer and a source-drain diffusion layer. By forming a base electrode sidewall using polycrystalline silicon for gate oxide film protection without using a separate insulating film, and simultaneously producing an emitter electrode and a gate electrode, by forming an electrode composed of polycrystalline silicon and silicide on the collector region surface, Simplify the process, improve cohesion and collect A BiCMOS transistor having an effect of reducing resistance and a method of manufacturing the same.

Description

High Speed BiCMOS Transistors and Manufacturing Method Thereof

1 is a cross-sectional view showing the structure of a bipolar region of a conventional BiCMOS transistor,

2A to 2L are cross-sectional views illustrating a method of manufacturing a BiMOS transistor according to an embodiment of the present invention, in the order of the steps thereof.

3 is a cross-sectional view showing the structure of a BiCMOS transistor according to the present invention.

* Explanation of symbols for main parts of the drawings

DESCRIPTION OF SYMBOLS 1 Single-crystal silicon substrate 2: First thermal oxide film

3: first nitride film 4: P-type buried layer

5: Selective oxide film 6: N-type buried layer

7: N-type single crystal silicon layer (epi layer) 8: Second thermal oxide film

9: second nitride film 10: first CVD dioxide film

11: trench 12: trench internal thermal oxide film

13 P-type impurity region 14 first polycrystalline silicon film

15: third thermal oxide film 16: third nitride film

17: bipolar region 18: NMOS region

19: PMOS region 20: field oxide film

21 collector region 22 collector diffusion layer

23: P type diffusion layer 24: base-emitter region

25: second polycrystalline silicon film 26: second CVD oxide film

27: fourth thermal oxide film 28: outer base diffusion layer

29 gate oxide film 30 third polycrystalline silicon film

31 polycrystalline silicon sidewall 32 P-type internal base diffusion layer

33: fourth polycrystalline silicon film 34: silicide film

35 LDD diffusion layer 36 oxide film sidewall

37 source-drain diffusion layer 38 emitter diffusion layer

39 base electrode 40 gate electrode

41 emitter electrode 42 collector electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiCMOS transistor and a method of manufacturing the same, and more particularly, to a BiCMOS and a method of manufacturing the same, which simultaneously form a high-speed bipolar device, an NMOS device, and a PMOS device.

In general, components such as computers and communication devices that require high-speed processing require integrated circuits that operate at high speed, and as the system itself becomes more complex, high integration of components is required. To satisfy this requirement, bipolar devices with high-speed characteristics and CMOS devices with high-density characteristics must be integrated on a chip.

Due to this need, BiCMOS transistors are devices in which bipolar transistor devices and CMOS transistor devices are integrated in one chip to improve electrical characteristics.

Therefore, in order to make BiCMOS transistors practical, the manufacturing process should be simplified and integrated at the same time, and in order to have high-speed bipolar characteristics, low base resistance and reduction of parasitic capacitance should be simultaneously realized.

In order to achieve this purpose, generally, emitters using polycrystalline silicon, self-aligning methods of base regions, and methods of forming emitters, base and gate electrodes from two layers of polycrystalline silicon have emerged.

Next, a conventional BiCMOS transistor will be described in more detail with reference to the accompanying drawings.

1 is a cross-sectional view showing the structure of a bipolar region of a conventional BiCMOS transistor.

As shown in FIG. 1, the conventional BiCMOS transistor has a field oxide film 113 on a semiconductor substrate in which an N-type buried layer 111 and an N-well 112 are formed on a P-type substrate 110. FIG. It is formed at this interval. The first oxide film 117 is thinly formed at one interval between the field oxide films 113 to connect two field oxide films 113, and is formed under the first oxide film 117 and the N type well 112 at the N type well 112. The collector region 114 is deeply formed in contact with the N-type buried layer 111. N ⁻ regions 134 and N ⁺ regions 142 are formed under the first oxide film 117 on the N-type collector region 114.

Next, the P-type outer base region 128 is formed on the semiconductor substrate between the field oxide films 113 on the other side, and the P-type outer base region 128 is divided into the inner base region 131 formed at the center. divided. A second polycrystalline silicon film 119 is covered on the P-type outer base region 128 and a part of the field oxide film 113, and the second oxide film 123 is covered again. The third oxide film 127 is thinly formed on a part of the field oxide film 113 that is in contact with the collector region 114 and on the side surface of the second polycrystalline silicon film 119 that covers the field oxide film 113. The first polycrystalline silicon film 118 is thinly formed between the other field oxide film 113 and the second polycrystalline silicon film 119.

An emitter region 139 is formed in the P-type inner base region 131, a third oxide film 127 on the side of the second polycrystalline silicon film 119 on the P-type outer base region 128, and A nitride sidewall 136 is formed thereon and is connected to the side surface of the second oxide film 123 on the second polycrystalline silicon film 119. The portion surrounded by the nitride sidewall 136, the third oxide film 127, and the emitter region 139 is called an emitter window.

A third polycrystalline silicon film 138 is formed in the emitter window, and a part of the third polycrystalline silicon film 138 covers the second oxide film 123 and is attached to the nitride oxide sidewall 123. 136 is covering. The silicide layer 140 is formed on the third polycrystalline silicon film 138.

In order to form such a conventional BiCMOS transistor, a field oxide film 113 is formed on a P-type semiconductor substrate 110 on which an N-type buried layer 111 and an N-type well 112 are formed, and between two field oxide films 113. An N-type collector region 114 is formed in the trench. The first oxide film 117 is grown on this surface. Thereafter, the first polycrystalline silicon film 118 is laminated thinly to protect the first oxide film 117, and the first polycrystalline silicon film 118 and the first oxide film 117 on the bipolar region are removed. After stacking the second polycrystalline silicon film 119 and the insulating film 123, the CMOS region is implanted into the N-type and the bipolar region is implanted into the P-type by a photo and ion implantation method.

Photo-etch the insulating film 123 and the second polycrystalline silicon film 119 to form a base and a gate electrode, grow the third oxide film 127 thinly and diffuse the outer base region 128, and then photograph and ion implantation. The inner base region 131 is formed by the method. The nitride layer is stacked on the surface, and photo-etched and dry-etched to expose the emitter region, thereby forming the nitride sidewall 136 of the base electrode and wet etching the third oxide layer 127 on the surface of the emitter region.

The third polycrystalline silicon is stacked and ion-implanted to form an emitter region 139. Finally, the silicide layer 140 is formed and the emitter electrode is formed by photolithography to complete the device.

However, the conventional method for manufacturing the BiCMOS transistor requires a separate photo and ion implantation process to distinguish the base electrode and the gate electrode, and additional nitride film stacking process is required for insulation and self-alignment between the emitter and the base electrode. In addition to being necessary, the stresses on the nitride sidewalls affect the emitter and base regions. In addition, since the collector area must be increased in order to further reduce the resistance of the collector region, there is a problem in that the integration degree of the device is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem. The base electrode is first formed, and the base electrode sidewalls are formed using polycrystalline silicon for gate oxide film protection without using a separate insulating film, and the emitter electrode and the gate electrode are simultaneously formed. In this case, an electrode composed of polycrystalline silicon and silicide is formed on the surface of the collector region, thereby simplifying the manufacturing process, improving the integration, and reducing the collector resistance.

In addition, the base electrode in the present invention can also be utilized as a resistance element on the field oxide film.

A method of manufacturing a BiCMOS transistor according to the present invention for achieving this object includes a second conductivity type bipolar region, a first conductivity type first MOS region, a second conductivity type second MOS region, and isolation to isolate the regions. A first process of forming two base electrodes separated from each other by a first conductivity type polycrystalline silicon and an oxide film thereon on an additionally formed semiconductor substrate. An impurity of the base electrode is diffused to a substrate of the bipolar region to form an external base. A second step of forming a diffusion layer, a third step of forming a gate oxide film in the MOS region, a polycrystalline silicon is laminated on the entire surface of the semiconductor substrate, and selectively etched to protect the gate oxide film of the MOS region, and to protect the gate oxide film in the bipolar region A fourth step of forming a silicon sidewall, by implanting ions into a substrate between the two base electrodes In the fifth step of forming a semiconductor, polycrystalline silicon is laminated on the entire surface of the semiconductor substrate, and then doped and etched to insulate the emitter electrode and the emitter electrode which are insulated with an oxide film formed on the base electrode between the two base electrodes. And a sixth step of forming the emitter diffusion layer and the source-drain diffusion layer in the collector electrode, the gate oxide film of the first MOS region and the second MOS region so as to insulate each gate electrode from each other.

Next, an embodiment of a method for manufacturing a high speed BiCMOS transistor according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

2A to 2L are cross-sectional views illustrating a method of manufacturing a high speed BiCMOS transistor according to an embodiment of the present invention in the order of their processes.

As shown in FIG. 2A, the first thermal oxide film 2 is thinly grown on the surface of the single crystal silicon substrate 1, and the first nitride film 3 is laminated thereon by the CVD method. Next, the first nitride film 3 is selectively removed by photolithography, and P-type ions are implanted to form a plurality of P-type buried layers 4 that are separated from each other.

As shown in (b) of FIG. 2, the selective oxide film 5 is grown by the conventional selective oxidation method using the first nitride film 3 remaining on the surface of the substrate 1, and then the P-type mask is used as a mask for ion implantation. An N type buried layer 6 is formed between the buried layers 4, and the first nitride film 3 is removed by a wet etching method.

As shown in (c) of FIG. 2, after removing both the first oxide film 2 and the selective oxide film 5 on the surface of the substrate 1 by wet etching, an N-type single crystal silicon layer (epitaxial) is subjected to a conventional silicon epitaxy method. After the layer 7 is formed, the second thermal oxide film 8 is grown. At this time, the buried layers 4 and 6 of the P-type and N-type also grow together. The second nitride film 9 and the first CVD oxide film 10 are sequentially stacked thereon by the CVD method.

As shown in (d) of FIG. 2, the trench 11 is formed at the boundary between the P-type buried layer 4 and the N-type buried layer 6 by photolithography, and the first CVD oxide film 10 is wet-etched. After removal, a trench internal thermal oxide film 12 is grown in the trench 11 and a P-type impurity region 13 is formed in the bottom of the trench 11 by an ion implantation method. Then, the NMOS region 18 in which the P-type buried layer 4 is formed, the bipolar region 17 in which the N-type buried layer is formed, and the PMOS region 19 are separated from each other by the trench 11.

As shown in (e) of FIG. 2, the first polycrystalline silicon film 14 is thickly stacked on the surface of the substrate 1, and then the trench 11 is filled with polycrystalline silicon by polishing and dry isotropic etching. (1) The first polycrystalline silicon film 14 is removed and planarized on the surface. Then, the second nitride film 9 is removed again by wet etching, and the third thermal oxide film 15 is grown.

In FIG. 2F, a portion of the bipolar region 17 is ion implanted with an N-type impurity, and a P-type impurity is implanted into a region where the P-type buried layer 4 is formed, for example, an NMOS region. Subsequently, when the third nitride film 16 is stacked on the surface of the substrate 1 and etched by a conventional photolithography method, the entire surface of the substrate 1 is oxidized to be selectively oxidized to form the field oxide film 20. The portion where the field oxide film 20 is formed is formed on the upper part of the polycrystalline silicon filled in each trench, the boundary between the BiCMOS devices, that is, the left side of the bipolar region 17 and the right side region of the PMOS region 19 in FIG. In the bipolar region 17, an N-type impurity is between an ion implanted portion and another portion. At this time, impurities implanted during the growth of the field oxide film 20 are diffused into the epi layer, so that the collector diffusion layer 22 is formed in the bipolar region 17, and the P type buried layer 4 is formed in the region implanted with other P-type impurities. Together, the P-type diffusion layer 23 is formed in the entire region.

In FIG. 2 (g), the collector diffusion layer 22 is formed by the bipolar base-emitter region, that is, the field oxide film 20, after the third nitride film 16 remaining on the surface of the substrate 1 is removed by a wet etching method. The third thermal oxide film 15 of the region 24 separated from the photoresist is removed by a photo and wet etching method.

In FIG. 2H, a second polycrystalline silicon film 25 is stacked on the surface of the substrate 1, ion-implanted with P-type impurities, and then a second CVD oxide film 26 is laminated. Next, the second polycrystalline silicon film 25 and the second CVD oxide film 26 are etched by photolithography to form base electrodes 39 at both ends of the base-emitter region. A fourth thermal oxide film 27 is grown on the exposed substrate. The fourth thermal oxide film 27 is grown to a predetermined thickness to insulate the base electrode 39 and the emitter electrode to be formed later. As the thermal oxide film 27 grows, impurities diffuse from the second polycrystalline silicon film 25 doped with P-type impurities into the epitaxial layer to form the outer base diffusion layer 28.

In (i) of FIG. 2, the third thermal oxide film 15 remaining on the surface of the MOS regions 18 and 19 of the substrate is removed by wet etching, the gate oxide film 29 is grown, and the third polycrystalline silicon film 30 ) And P-type impurities are implanted to control the threshold voltage of the MOS device. At this time, the wet etching of the third thermal oxide film 15 is controlled to maintain the fourth thermal oxide film 27 on the side of the base electrode by a predetermined thickness or more. The third polycrystalline silicon film 30 serves to protect the characteristics of the gate oxide film 29 in subsequent photographs and other processes, and simultaneously forms sidewalls 31 of the base electrode.

In (j) of FIG. 2, the third polycrystalline silicon film 30 on the bipolar region 17 on the surface of the substrate 1 is etched by photo and dry etching to form a polycrystalline silicon sidewall (on the side of the base electrode 39). 31). The fourth thermal oxide layer 27 is removed by wet etching to expose the portion where the emitter region of the bipolar region 17 and the collector diffusion layer 22 are exposed, and then ion implanted with low energy to form a P-type internal base diffusion layer. To form 32.

In FIG. 2 (k), the fourth polycrystalline silicon film 33 is laminated on the surface of the substrate 1 to a predetermined thickness necessary for the emitter and collector electrodes of the bipolar element, and ion implanted with N-type impurities. Thereafter, the silicide layer 34 is formed, and the fourth polycrystalline silicide and silicide layers are etched by photolithography to simultaneously form the gate electrode 40 of the NMOS and PMOS devices and the emitter and collector electrodes 41 and 42 of the bipolar device. Form. A photo and an ion implantation method has a low impurity concentration (N ^- or P ^-) by injecting the MOS region to form an LDD diffusion layer (35). In this way, the emitter, the collector, and the gate electrodes 41, 42, and 40 are simultaneously formed of one layer of the fourth polycrystalline silicon film 33, so that the manufacturing process can be simplified and integrated.

Finally, in FIG. 2 (l), an oxide film is deposited on the surface of the substrate 1 by CVD, and then oxide sidewalls 36 are formed on the gate, emitter and collector electrodes 41, 42, and 40 by dry anisotropic etching. And form the N ⁺ and P ⁺ source-drain diffusion layers 37 by photo, ion implantation, and diffusion again. At this time, the ions implanted into the emitter electrode 41 are diffused into the inner base diffusion layer 32 to form the emitter diffusion layer 38.

After that, an insulating film is stacked and BiCMOS having high speed and high reliability is completed by using a conventional contact and metal process.

In the process of the BiCMOS transistor fabrication method according to the present invention, the polycrystalline silicon sidewall 31 provides a self-aligned and uniform isolation of the emitter diffusion layer 37 and the outer base diffusion layer 28 to improve the characteristics and reliability of the device At the same time, the parasitic capacitance between the emitter and the base region is kept small to maintain high speed device characteristics. In addition, since the oxide film on the surface of the emitter region can be wet-etched by using the same, the damage to the surface is prevented, thereby improving device characteristics and reliability.

3 is a cross-sectional view showing the structure of a BiCMOS transistor according to the present invention.

As shown in FIG. 3, in the BiCMOS transistor according to the present invention, the N-type buried layers 6 are formed on the single crystal silicon substrate 1 having the P-type impurities diffused therebetween and are spaced apart from each other. The buried layer 6 includes an epitaxial layer 7 which is an N-type single crystal silicon layer, respectively, forming a bipolar region 17 and a PMOS region 19, respectively. An NMOS region 18 is formed between the bipolar region 17 and the PMOS region 19. Polycrystalline silicon is filled between the regions, and a trench 11 surrounded by a thermal oxide film 12 is formed on the inner wall, and a P-type impurity region 13 is formed below.

The bipolar region 17 is composed of a base-emitter region 24 and a collector region 21. A field oxide film 20 is formed around the two regions. A P-type outer base diffusion layer 28 and an inner base diffusion layer 32 are formed on the substrate of the base-emitter region 24, and an N-type emitter diffusion layer 38 is formed at the center thereof. A second polycrystalline silicon film 25 is formed on each of the outer base diffusion layer 28 and the field oxide film 20 on both sides, and a second CVD oxide film 26 is deposited thereon, and polycrystalline on both sides. Silicon sidewalls 31 are formed. A fourth polycrystalline silicon film 33 is formed on the emitter diffusion layer 38 to cover a portion of the second CVD oxide film 26. The silicide layer 34 is formed thereon. The amount of the polycrystalline silicon sidewall 31 formed on the outer side of the base regions 28 and 32, and the fourth polycrystalline silicon film 33 and the silicide layer 34 formed on the emitter diffusion layer 38, respectively. An oxide film sidewall 36 is formed on the side surface.

An N-type collector diffusion layer 22 is formed in the collector region 21, and a fourth polycrystalline silicon film 33 and a silicide layer 34 are sequentially formed thereon. Similar to the base-emitter region 24, oxide sidewalls 36 are formed on both sides of the fourth polycrystalline silicon film 33 and the silicide layer 34.

Source-drain diffusion layers 37 are formed on the substrates of the NMOS region 18 and the PMOS region 19 with a gap therebetween, and each includes an LDD diffusion layer 35. A gate oxide film 29 is formed on the surface of the substrate, and a third polycrystalline silicon film 30 and a fourth polycrystalline silicon film 33 are formed on the gate oxide film 29 above the gap between the source-drain diffusion layer 37. The silicide layer 34 is formed thereon. Oxide film sidewalls 36 are formed on both sides of the fourth polycrystalline silicon film 33 and the silicide layer 34 to be attached to the gate oxide film 29.

Therefore, in the method of manufacturing the high-speed BiCMOS transistor according to the present invention, the base electrode is first formed, the base electrode sidewalls are formed using polycrystalline silicon for gate oxide film protection without using a separate film, and the emitter electrode and the gate electrode are formed. At the same time, by forming the electrode formed of polycrystalline silicon and silicide on the surface of the collector region at the same time, there is an effect to simplify the manufacturing process, improve the degree of integration and reduce the collector resistance.

In addition, the base electrode in the present invention can also be utilized as a resistance element on the field oxide film.

Claims (4)

A first conductivity type polycrystalline silicon and a second conductivity type bipolar region, a first conductivity type first MOS region, a second conductivity type second MOS region, and an isolation portion to isolate the regions A first step of forming two base electrodes separated from each other by an oxide film, a second step of forming an external base diffusion layer by diffusing impurities of the base electrode onto a substrate of the bipolar region, and forming a gate oxide film in the MOS region A third step of laminating polycrystalline silicon on the entire surface of the semiconductor substrate, selectively etching to protect the gate oxide film of the MOS region, and forming a polycrystalline silocon sidewall of the bipolar region, on the substrate between the two base electrodes A fifth step of forming a base region by implanting ions, laminating polycrystalline silicon on the entire surface of the semiconductor substrate, and then doping Each gate in the gate oxide film of the emitter electrode and the collector electrode insulated from the emitter electrode and the gate electrode of the first MOS region and the second MOS region by high etching. And a sixth step of forming the electrodes to be insulated from each other and forming an emitter diffusion layer and a source-drain diffusion layer. The BiCMOS transistor of claim 1, further comprising: forming the gate oxide film by a thermal oxidation method in a third step of forming the gate oxide film, and removing the thermal oxide film formed on the substrate between the polycrystalline silicon sidewalls after the fourth step. Method of preparation. 2. The BiCMOS method of claim 1, further comprising forming the emitter electrode, the collector electrode, and the gate electrode by forming a polycrystalline silicon film in the sixth step, stacking a silicide layer on the polycrystalline silicon film, and etching the same. Method of manufacturing a transistor. The emitter and collector electrodes of claim 1, wherein, in the forming of the source-drain diffusion layer, after forming the gate electrode, an LDD diffusion layer is formed in the MOS region, an oxide layer is deposited on the surface of the substrate, and the etching is performed. And forming a sidewall of an oxide film on the gate electrode, and then forming a high concentration diffusion layer of impurities of a first conductivity type and a second conductivity type.