KR100187686B1 - Metal layer formation method of semiconductor device - Google Patents
Metal layer formation method of semiconductor device Download PDFInfo
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- KR100187686B1 KR100187686B1 KR1019960007103A KR19960007103A KR100187686B1 KR 100187686 B1 KR100187686 B1 KR 100187686B1 KR 1019960007103 A KR1019960007103 A KR 1019960007103A KR 19960007103 A KR19960007103 A KR 19960007103A KR 100187686 B1 KR100187686 B1 KR 100187686B1
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- metal
- layer
- contact hole
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 37
- 239000002184 metal Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- -1 aluminum ions Chemical class 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 37
- 239000011800 void material Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 금속층 형성 방법에 관한 것으로, 콘택 홀에서 금속의 층덮힘을 향상시키기 위하여 콘택 홀의 상부 모서리부를 제외한 측벽 및 하부에 금속 이온을 주입하여 시드층을 형성한 후 금속을 매립시키므로써 금속의 층덮힘이 향상된다. 따라서 보이드의 발생이 방지되고 금속층의 접속 불량 및 단선이 방지되어 소자의 전기적 특성 및 신뢰성이 향상될 수 있는 반도체 소자의 금속층 형성 방법에 관한 것이다.The present invention relates to a method of forming a metal layer of a semiconductor device, in order to improve the layer covering of the metal in the contact hole by implanting metal ions into the sidewall and the bottom except the upper edge of the contact hole to form a seed layer and then embedding the metal The layer covering of the metal is improved. Accordingly, the present invention relates to a method of forming a metal layer of a semiconductor device, in which voids are prevented, connection failure and disconnection of the metal layer are prevented, thereby improving electrical characteristics and reliability of the device.
Description
제1a 내지 1c도는 종래 반도체 소자의 금속층 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a metal layer of a conventional semiconductor device.
제2도는 제1c도의 X - X' 부분을 절취한 상태의 단면도.2 is a cross-sectional view of the state taken along the line X-X 'of FIG.
제3a 내지 제3d도는 본 발명에 따른 반도체 소자의 금속층 형성방법을 설명하기 위한 소자의 단면도.3A to 3D are cross-sectional views of a device for explaining a method of forming a metal layer of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 및 11 : 실리콘 기판 2 및 12 : 접합부1 and 11: silicon substrates 2 and 12 junctions
3 및 13 : 절연층 4 및 14 : 콘택 홀3 and 13: insulation layer 4 and 14: contact hole
5 및 15 : 금속 6 : 보이드5 and 15: metal 6: void
7 : 감광막 7 : 시드층7: photosensitive film 7: seed layer
본 발명은 반도체 소자의 금속층 형성 방법에 관한 것으로, 특히 금속의 층덮힘(Step coverage)을 향상시킬 수 있도록 한 반도체 소자의 금속층 형성 방법에 관한 것이다.The present invention relates to a method of forming a metal layer of a semiconductor device, and more particularly to a method of forming a metal layer of a semiconductor device to improve the step coverage of the metal.
일반적으로 반도체 소자의 제조 공정에서 접합부와 도전층 그리고 도전층간의 접속은 층간 절연막에 형성된 콘택 홀(Contact hole)을 통해 이루어진다. 그런데 반도체 소자가 고집적화됨에 따라 콘택 홀의 크기가 미세화되고, 이에 따라 콘택 홀내에서 금속의 층덮힘이 저하되기 때문에 도전층간의 접속 불량 또는 단선 등의 문제가 발생된다. 그러면 도전층으로 이용되는 종래 반도체 소자의 금속층 형성 방법을 제1a 내지 제1c도를 통해 설명하면 다음과 같다.In general, the connection between the junction portion, the conductive layer, and the conductive layer in the semiconductor device manufacturing process is made through a contact hole formed in the interlayer insulating film. However, as the semiconductor devices are highly integrated, the size of the contact holes becomes smaller, and thus, the layer covering of the metal in the contact holes is reduced, thereby causing problems such as poor connection or disconnection between the conductive layers. Next, a method of forming a metal layer of a conventional semiconductor device used as a conductive layer will be described with reference to FIGS. 1A through 1C.
제1a 내지 제1c도는 종래 반도체 소자의 금속층 형성 방법을 설명하기 위한 소자의 단면도로서, 제2도를 참조하여 설명하면 다음과 같다.1A to 1C are cross-sectional views of a device for describing a method of forming a metal layer of a conventional semiconductor device, which will be described below with reference to FIG. 2.
제1a도는 접합부(2)가 형성된 실리콘 기판(1)상에 절연층(3)을 형성하고, 상기 접합부(2)가 노출되도록 상기 절연층(3)을 패터닝하여 콘택 홀(4)을 형성한 상태의 단면도이다.In FIG. 1A, the insulating layer 3 is formed on the silicon substrate 1 on which the junction part 2 is formed, and the contact layer 4 is formed by patterning the insulating layer 3 so that the junction part 2 is exposed. It is a cross section of the condition.
제1b도는 스퍼터링(Sputtering) 증착 방법으로 상기 콘택 홀(4)이 매립되도록 전체 상부면에 알루미늄(Al)과 같은 금속(5)을 증착하는 상태의 단면도로서, 이때 상기 콘택 홀(4)의 단차로 인하여 상기 콘택 홀(4)의 측벽보다 모서리 부분에 상기 금속(5)이 빠르게 증착된다.FIG. 1B is a cross-sectional view of depositing a metal 5 such as aluminum (Al) on the entire upper surface of the contact hole 4 so as to fill the contact hole 4 by a sputtering deposition method, wherein the step of the contact hole 4 is Due to this, the metal 5 is deposited faster in the corner portion than in the sidewall of the contact hole 4.
제1c도는 상기 콘택 홀(4)이 완전히 매립되도록 상기 금속(5)을 증착한 상태의 단면도로서, 상기와 같은 증착 속도 차이로 인한 층덮힘 불량으로 상기 콘택 홀(4)내에 보이드(6)가 형성된다. 여기서 상기 제1c도의 A - A' 부분을 절취하면 제2도에도시된 바와 같이 상기 콘택 홀(4)내에 증착된 금속(5)의 중앙부가 비어있는 상태 즉, 보이드(6)가 발생됨을 알 수 있는데, 상기 보이드(6)는 상기 콘택 홀(4)내에서 상기 금속(5)이 차지하는 면적을 감소시킨다. 그러므로 상기 콘택 홀(4)을 통해 흐르는 전류의 밀도가 감소되어 소자의 전기적 특성이 저하되며, 더욱이 상기 보이드(6)가 심하게 발생되는 경우 상기 금속(5)과 상기 접합부(2)간의 접속 불량 및 단선이 유발되어 소자의 신뢰성이 저하된다. 그래서 이러한 문제를 해결하기 위하여 근래에는 상기 콘택 홀(4) 상부의 모서리 부분을 경사지게 형성하는 방법을 이용하고 있으나, 소자가 고집적화에 따른 공정의 제어가 어렵기 때문에 소자의 수율이 향상되지 못하는 단점이 있다.FIG. 1C is a cross-sectional view of the metal 5 deposited in such a manner that the contact hole 4 is completely buried, and voids 6 are formed in the contact hole 4 due to poor layer covering due to the deposition rate difference. Is formed. Here, it can be seen that when the portion A-A 'of FIG. 1c is cut, the void 6 is generated, as shown in FIG. 2, in which the central portion of the metal 5 deposited in the contact hole 4 is empty. The void 6 reduces the area occupied by the metal 5 in the contact hole 4. Therefore, the density of the current flowing through the contact hole 4 is reduced, so that the electrical characteristics of the device are degraded. Further, when the voids 6 are severely generated, poor connection between the metal 5 and the junction 2 and Disconnection is caused and the reliability of the device is degraded. Therefore, in order to solve this problem, the method of forming the inclined corner portion of the upper part of the contact hole 4 has been used in recent years. However, since the device is difficult to control the process due to high integration, the yield of the device is not improved. have.
따라서, 본 발명은 콘택 홀의 상부 모서리부를 제외한 측벽 및 하부에 금속 이온을 주입하여 시드(Seed)층을 형성한 후 금속을 매립시키므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속층 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method for forming a metal layer of a semiconductor device which can solve the above-mentioned disadvantages by forming a seed layer by implanting metal ions into sidewalls and a bottom of the contact hole except for the upper edge of the contact hole and then embedding the metal. Its purpose is to.
상기한 목적을 달성하기 위한 본 발명은 접합부가 형성된 실리콘 기판상에 절연층 및 감광막을 순차적으로 형성한 후 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 마스크로 이용한 식각 공정으로 노출된 부분의 상기 절연층을 식각하여 상기 접합부가 노출되도록 콘택 홀을 형성하는 단계와, 상기 단계로부터 상기 콘택 홀의 상부 모서리부를 제외한 측벽 및 하부에 시드층이 형성되도록 금속 이온을 주입하는 단계와, 상기 단계로부터 상기 감광막을 제거한 후 상기 콘택 홀이 매립되도록 전체 상부면에 금속을 증착하는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, an insulating layer and a photoresist layer are sequentially formed on a silicon substrate on which a junction part is formed, and then the patterned photoresist layer is exposed, and the etching process using the patterned photoresist layer as a mask is performed. Forming a contact hole to expose the junction by etching the insulating layer of the portion, and implanting metal ions such that a seed layer is formed on sidewalls and bottoms of the contact hole except the upper edge of the contact hole; After removing the photosensitive film from the step characterized in that the step of depositing a metal on the entire upper surface to fill the contact hole.
이하, 첨부된도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3a 내지 제3d도는 본 발명에 따른 반도체 소자의 금속층 형성방법을 설명하기 위한 소자의 단면도로서, 제3a도는 접합부(12)가 형성된 실리콘 기판(11)상에 절연층(13) 및 감광막(7)을 순차적으로 형성한 후 콘택 마스크(Mask)를 이용하여 상기 감광막(7)을 패터닝한다. 그리고 상기 패터닝된 감광막(7)을 마스크로 이용한 식각 공정으로 노출된 부분의 상기 절연층(13)을 식각하여 상기 접합부(12)가 노출되도록 콘택 홀(14)을 형성한 상태의 단면도이다.3A to 3D are cross-sectional views of a device for explaining a method of forming a metal layer of a semiconductor device according to the present invention. FIG. 3A is a view illustrating an insulating layer 13 and a photoresist film 7 on a silicon substrate 11 on which a junction part 12 is formed. ) Is sequentially formed and then patterned on the photoresist layer 7 using a contact mask. The contact layer 14 is formed by etching the insulating layer 13 of the exposed portion by the etching process using the patterned photoresist 7 as a mask to expose the junction 12.
제3b도는 알루미늄(Al) 이온과 같은 금속 이온을 주입하여 상기 콘택 홀(14)의 측벽 및 노출된 상기 실리콘 기판(11)에 시드(Seed)층 (8)을 형성한 상태의 단면도로서, 상기 금속 이온 주입시 최저 에너지 이온이 실리콘 표면에 물리적으로 주입되어 저온 열처리 효과를 얻게 되며, 이때 실리콘과 금속 이온(알루미늄 이온)의 결합이 표면에 나타나게 된다. 또한 상기 금속 이온 주입시 상기 콘택 홀(14)의 측벽 및 노출된 상기 실리콘 기판(11)이 상기 금속 이온에 의해 피해(Damage)를 입지 않도록 이온 주입 에너지를 조절하며, 상기 콘택 홀(14) 상부 모서리부에는 상기 금속 이온이 주입되지 않도록 한다.3B is a cross-sectional view of a state in which a seed layer 8 is formed on sidewalls of the contact hole 14 and the exposed silicon substrate 11 by implanting metal ions such as aluminum (Al) ions. In the metal ion implantation, the lowest energy ions are physically implanted on the silicon surface to obtain a low temperature heat treatment effect. At this time, the bond between silicon and metal ions (aluminum ions) appears on the surface. In addition, the ion implantation energy is adjusted so that the sidewall of the contact hole 14 and the exposed silicon substrate 11 are not damaged by the metal ions when the metal ion is implanted, and the upper portion of the contact hole 14 is The metal ions are not injected into the corners.
제3c도는 상기 감광막(7)을 제거한 후 상기 콘택 홀(14)이 매립되도록 전체 상부면에 알루미늄(Al)과 같은 금속(15)을 증착하는 상태의 단면도로서, 이때 상기 알루미늄은 연성(軟性)의 금속이므로 동일한 원자가 존재하는 상기 시드층(8)상에는 상기 금속(15)의 증착이 빠르게 이루어지는 반면, 상기 시드층(8)이 형성되지 않은 부분에서는 상기 금속(15)의 증착 속도가 느려져 상기 금속(15)의 층덮힘이 양호해진다.3C is a cross-sectional view of a metal 15 such as aluminum (Al) deposited on the entire upper surface of the contact hole 14 after the photosensitive film 7 is removed, wherein the aluminum is ductile. Since the metal 15 is rapidly deposited on the seed layer 8 having the same atom because it is a metal, the deposition rate of the metal 15 is slowed at the portion where the seed layer 8 is not formed. The layer covering of (15) becomes good.
제3d도는 상기 콘택 홀(14)이 완전히 매립되도록 상기 금속(15)을 증착한 상태의 단면도로서, 상기 금속(15)의 층덮힘이 양호하여 보이드가 발생되지 않는다.3d is a cross-sectional view of the metal 15 deposited in such a manner that the contact hole 14 is completely buried, and the layer 15 of the metal 15 is well covered, so that voids are not generated.
상술한 바와 같이 본 발명에 의하면 콘택 홀의 상부 모서리부를 제외한 측벽 및 하부에 금속 이온을 주입하여 시드층을 형성한 후 금속을 매립시키므로써 금속의 층덮힘이 양호해진다. 그러므로 금속층의 접속 불량 및 단선이 방지되어 소자의 전기적 특성 및 신뢰성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the seed layer is formed by implanting metal ions into the sidewalls and the bottom of the contact hole except the upper edge of the contact hole. Therefore, the connection failure and disconnection of the metal layer is prevented, and there is an excellent effect that the electrical characteristics and reliability of the device can be improved.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960007103A KR100187686B1 (en) | 1996-03-16 | 1996-03-16 | Metal layer formation method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960007103A KR100187686B1 (en) | 1996-03-16 | 1996-03-16 | Metal layer formation method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970067640A KR970067640A (en) | 1997-10-13 |
| KR100187686B1 true KR100187686B1 (en) | 1999-06-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019960007103A Expired - Fee Related KR100187686B1 (en) | 1996-03-16 | 1996-03-16 | Metal layer formation method of semiconductor device |
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| Country | Link |
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| KR (1) | KR100187686B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990057279A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Barrier layer formation method of contact hole using ion implantation |
| KR100429177B1 (en) * | 1997-06-30 | 2004-06-16 | 주식회사 하이닉스반도체 | Line manufacturing method of semiconductor device |
| US20230268442A1 (en) * | 2020-08-21 | 2023-08-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Device and Method of Manufacture |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100585063B1 (en) * | 1999-06-15 | 2006-05-30 | 삼성전자주식회사 | Metal layer formation method using selective electroplating process |
| KR100387257B1 (en) * | 1999-12-28 | 2003-06-11 | 주식회사 하이닉스반도체 | Method of forming a metal line in a semiconductor device |
| KR100451766B1 (en) * | 2001-12-22 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for forming interconnect structures of semiconductor device |
| KR100783274B1 (en) * | 2006-11-29 | 2007-12-06 | 동부일렉트로닉스 주식회사 | Method for manufacturing the semiconductor device |
| KR100825648B1 (en) * | 2006-11-29 | 2008-04-25 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method thereof |
-
1996
- 1996-03-16 KR KR1019960007103A patent/KR100187686B1/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100429177B1 (en) * | 1997-06-30 | 2004-06-16 | 주식회사 하이닉스반도체 | Line manufacturing method of semiconductor device |
| KR19990057279A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Barrier layer formation method of contact hole using ion implantation |
| US20230268442A1 (en) * | 2020-08-21 | 2023-08-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Device and Method of Manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970067640A (en) | 1997-10-13 |
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