KR0186082B1 - Device Separation Method of Semiconductor Devices - Google Patents
Device Separation Method of Semiconductor Devices Download PDFInfo
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- KR0186082B1 KR0186082B1 KR1019950024919A KR19950024919A KR0186082B1 KR 0186082 B1 KR0186082 B1 KR 0186082B1 KR 1019950024919 A KR1019950024919 A KR 1019950024919A KR 19950024919 A KR19950024919 A KR 19950024919A KR 0186082 B1 KR0186082 B1 KR 0186082B1
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- pad oxide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000926 separation method Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 27
- 150000004767 nitrides Chemical class 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 210000003323 beak Anatomy 0.000 abstract description 14
- 230000007547 defect Effects 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자의 소자분리방법에 관한 것으로, 반도체 기판의 액티브 영역에 패드 산화막 및 질화막을 형성하는 공정과; NH3분위기하에서 열처리하는 공정과; 상기 패드 산화막과 질화막 측벽에 측벽 스페이서를 형성하는 공정 및; 열산화 공정을 실시하는 공정을 구비하여 소자 제조를 완료하므로써, 기존 NSL(nitride sidewall LOCOS) 공정과 SILO(sealed-interface local oxidation) 공정의 장점인 버즈 비크 감소를 최대한 이용하면서도 상기 공정의 단점인 스트레스에 의한 액티브 영역의 결함 생성을 방지할 수 있는 고신뢰성의 반도체 소자를 구현할 수 있게 된다.The present invention relates to a device isolation method of a semiconductor device, comprising: forming a pad oxide film and a nitride film in an active region of a semiconductor substrate; Heat treatment under NH 3 atmosphere; Forming sidewall spacers on sidewalls of the pad oxide and nitride films; Comprising the process of performing the thermal oxidation process to complete the device manufacturing, the stress of the disadvantages of the process while maximizing the reduction of the buzz beak, which is the advantage of the conventional sidewall LOCOS (NSL) process and sealed-interface local oxidation (SILO) process It is possible to implement a highly reliable semiconductor device that can prevent the generation of defects in the active region.
Description
제1(a)도 내지 제1(c)도는 종래 기술에 따른 반도체 소자의 소자분리공정을 도시한 공정수순도,1 (a) to 1 (c) is a process flowchart showing a device isolation process of a semiconductor device according to the prior art,
제2(a)도 내지 제2(c)도는 본 발명에 따른 반도체 소자의 소자분리 공정을 도시한 공정수순도.2 (a) to 2 (c) is a process flowchart showing the device isolation process of the semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
100 : 반도체 기판 102 : 절연막100 semiconductor substrate 102 insulating film
104 : 질화막 106 : 질화된 산화막104: nitride film 106: nitrided oxide film
108 : 측벽 스페이서108: sidewall spacer
본 발명은 반도체 소자의 소자분리(isolation)방법에 관한 것으로, 특히 모스 소자와 버즈 비크(bird's beak)를 최소한으로 줄이면서도 액티브 영역의 스트레스에 의한 결함(defect) 생성을 억제할 수 있도록 한 반도체 소자의 소자분리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a semiconductor device capable of suppressing defect generation due to stress in an active region while minimizing a MOS device and a bird's beak. It relates to a device isolation method of.
종래 일반적으로 사용되어온 반도체 소자의 소자분리공정은 미국 특허 4,764,248호에 보고된 기술 내용에서 알 수 있듯이 먼저, 제1(a)도에 도시된 형태로 반도체 기판(10) 상에 얇은 패드 산화막(12)을 형성한 뒤, 상기 산화막(12)에 산소가 침투하는 것을 방지하기 위한 한 방법으로 NH3분위기하에서 상기 산화막을 열처리하여 질화시키고, 이후 제1(b)도에 도시된 바와 같이 상기 패드 산화막(12) 상에 질화막(14)을 증착한 후, 기판(10) 위의 필드 영역의 산화막(12) 및 질화막(14)을 제거하여 액티브 영역에만 질화막(14)이 남도록 패턴을 형성한 뒤, 열산화 공정(field oxidation)을 실시하여 제1(c)도에 도시된 바와 같이 필드 영역에 격리막(16)을 형성하고 있다.A device isolation process of a semiconductor device, which has been generally used in the related art, can be seen in the technical contents reported in US Pat. No. 4,764,248. First, a thin pad oxide film 12 on the semiconductor substrate 10 in the form shown in FIG. ) And then nitriding the oxide film under an NH 3 atmosphere in a manner of preventing oxygen from penetrating into the oxide film 12, and then, as shown in FIG. 1 (b), the pad oxide film After depositing the nitride film 14 on the substrate 12, the oxide film 12 and the nitride film 14 in the field region on the substrate 10 are removed to form a pattern such that the nitride film 14 remains only in the active region. The field oxidation is performed to form the isolation film 16 in the field region as shown in FIG. 1 (c).
즉, 상기 공정은 패드 산화막(12)을 NH3분위기하에서 질화시킴으로써 열산화 공정시 상기 산화막(12)으로의 산소 침투를 방지하여 버즈 비크를 줄이도록 한 것이다.In other words, the step is to reduce the buzz beak by preventing the oxygen oxide penetration into the oxide film 12 during the thermal oxidation process by nitriding the pad oxide film 12 in the NH 3 atmosphere.
그러나 이와 같이 공정을 진행할 경우에는 버즈 비크는 줄일 수 있으나, 이에 상응하여 스트레스에 의한 액티브 영역의 결함(A) 생성이 현저하게 커지게 되고, 또한 액티브 영역의 패드 산화막(12)이 지나치게 질화될 경우, 정션(junction) 특성이 악화될 수 있을 뿐 아니라 스트레스가 지나쳐 기판(10)상의 액티브 영역에 결함이 발생되는 문제가 야기하게 된다.However, when the process is performed in this way, the buzz bequee can be reduced, but correspondingly, the generation of a defect A in the active region due to stress is significantly increased, and the pad oxide film 12 in the active region is excessively nitrided. In addition, the junction property may be deteriorated, and the stress may be excessive to cause a problem in which a defect occurs in the active region on the substrate 10.
이외의 방법으로 SILO(sealed-interface local oxidation)을 이용한 소자분리공정도 있지만 이 또한 버즈 비크 측면에서는 유리하지만 스트레스로 인해 리키지/인터페이스(leackage/interface)가 발생되므로 소자의 특성을 저하시키는 단점을 가지게 된다.In addition, there is a device isolation process using sealed-interface local oxidation (SILO), but this is also advantageous in terms of buzz beak, but the disadvantage of deteriorating device characteristics due to the generation of leakage / interface due to stress. Have.
즉, 상기와 같은 종래의 소자분리공정을 이용하여 소자를 제조하게 될 경우에는 기 언급된 바와 같이 버즈 비크를 줄이기 위하여 질화막 두께를 증가시키고 패드 산화막의 두께를 줄이게 되면 스트레스에 의한 기판 결함이 발생하게 되고, 반대로 질화막 두께를 줄이고 패드 산화막의 두께를 증가시키면, 스트레스는 감소하는 반면 버즈 비크가 현저하게 커지게 되므로 버즈 비크와 스트레스에 의한 액티브 영역의 결함 생성을 동시에 줄일 수 없다는 문제점을 가지게 된다.That is, when the device is manufactured by using the conventional device separation process as described above, if the thickness of the nitride film is increased and the thickness of the pad oxide film is reduced to reduce the buzz beak, as described above, the substrate defect may be caused by stress. On the contrary, if the thickness of the nitride film is reduced and the thickness of the pad oxide film is increased, the stress is reduced, but the buzz beak becomes remarkably large, which causes a problem in that defect generation of the active area due to the buzz beak and the stress cannot be simultaneously reduced.
이에 본 발명은 상기와 같은 문제점을 해결하기 위하여 이루어진 것으로, 두꺼운 패드 산화막과 얇은 질화막을 이용하되, 그 측면만 열처리한 뒤 패드 산화막과 질화막 측벽에 측벽 스페이서를 형성함으로써 액티브 영역의 스트레스를 최소화하면서도 버즈 비크를 억제할 수 있도록 한 반도체 소자의 소자분리방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, but by using a thick pad oxide film and a thin nitride film, the side surface spacers are formed on the sidewalls of the pad oxide film and the nitride film after heat treatment only on the side surface to minimize the stress of the active area while the buzz It is an object of the present invention to provide a device isolation method for a semiconductor device capable of suppressing the beak.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자분리방법은 반도체 기판의 액티브 영역에 패드 산화막과 질화막을 형성하는 공정과; NH3분위기하에서 열처리하는 공정과; 상기 반도체 기판의 전면에 질화막을 증착한 후, 선택적으로 식각하여 상기 패드 산화막과 질화막 측벽에 측벽 스페이서를 형성하는 공정과; 열산화 공정을 실시하는 공정을 구비하여 형성되는 것을 특징으로 한다.The device isolation method of the semiconductor device according to the present invention for achieving the above object comprises the steps of forming a pad oxide film and a nitride film in the active region of the semiconductor substrate; Heat treatment under NH 3 atmosphere; Depositing a nitride film on the entire surface of the semiconductor substrate and selectively etching to form sidewall spacers on sidewalls of the pad oxide film and the nitride film; And a step of performing a thermal oxidation step.
상기 공정 결과, 버즈 비크와 스트레스로 인한 액티브 영역의 결함 발생을 동시에 줄일 수 있게 된다.As a result, the occurrence of defects in the active region due to the buzz beak and the stress can be simultaneously reduced.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
본 발명은 NSL(nitride sidewell LOCOS) 구조를 개선한 형태로서 두꺼운 패드 산화막과 얇은 질화막으로 액티브 영역의 스트레스를 최소화하고, 그 측면의 NH3열처리 공정 및 질화막으로 이루어진 측벽 스페이서(side wall spacer) 형성 공정을 통하여 버즈 비크의 성장을 억제하는데 주안점을 둔 것으로, 제2(a)도 내지 제2(c)도에 도시된 공정수순도를 이용하여 이를 구체적으로 살펴보면 다음과 같다.The present invention is a form of improved NSL (nitride sidewell LOCOS) structure to minimize the stress of the active region with a thick pad oxide film and a thin nitride film, the NH 3 heat treatment process of the side and the side wall spacer formation process consisting of a nitride film The focus is on suppressing the growth of the buzz beak through, and look at this in detail using the process flow shown in Figure 2 (a) to 2 (c) as follows.
먼저, 제2(a)도에 도시된 바와 같이 반도체 기판(100)상에 패드 산화막(102)을 약 500Å의 두께로 형성한 뒤, 상기 패드 산화막(102) 상에 절연막(104)을 약 1000Å의 두께로 형성한다. 이때, 언급된 바와 같이 상기 패드 산화막(102)과 질화막(104)의 두께비는 1:2 정도가 되도록 증착함에 유의한다.First, as shown in FIG. 2 (a), a pad oxide film 102 is formed on the semiconductor substrate 100 to a thickness of about 500 GPa, and then an insulating film 104 is formed on the pad oxide film 102 to about 1000 GPa. It is formed to the thickness of. At this time, as mentioned, the thickness ratio of the pad oxide film 102 and the nitride film 104 is deposited to be about 1: 2.
그후, 질화막(104) 상의 액티브가 될 영역 사진식각공정을 통하여 감광막 패턴을 형성하고, 이를 마스크로 상기 질화막(104) 및 패드 산화막(102)을 식각한 후, 상기 감광막 패턴을 제거하고 그 측면한 NH3분위기하에서 1000-1100℃의 온도로 30분 내지 180분 동안 열처리하여 질화(106)시키므로써 제2(b)도에 도시된 바와 같이 패턴을 형성한다.Thereafter, a photoresist pattern is formed through an area photolithography process to become active on the nitride film 104, and the nitride film 104 and the pad oxide film 102 are etched using a mask, and then the photoresist pattern is removed and the side surface thereof is removed. The substrate is heat-treated at a temperature of 1000-1100 ° C. for 30 minutes to 180 minutes under an NH 3 atmosphere to nitrate 106 to form a pattern as shown in FIG. 2 (b).
이어서, 상기 패턴 전면에 다시 질화막을 증착하고 건식각하여 상기 질화막(104)과 패드 산화막(102) 측벽에 질화막으로 이루어진 측벽 스페이서(108)를 형성하고, 열산화를 실시하여 제2(c)도에 도시된 바와 같이 필드 영역에 격리막(110)을 성장시킴으로써 본 공정을 완료한다. 그 결과, 기존 소자에 비해 B부분의 버즈 비크 성장이 억제되고, C부분의 결함 발생을 억제할 수 있게 된다.Subsequently, a nitride film is deposited on the entire surface of the pattern and dry-etched to form sidewall spacers 108 formed of a nitride film on the sidewalls of the nitride film 104 and the pad oxide film 102. The process is completed by growing the separator 110 in the field region as shown in FIG. As a result, it is possible to suppress the growth of the buzz beak in the B part and the occurrence of defects in the C part as compared with the existing device.
즉, 상기 공정은 버즈 비크와 스트레스에 의한 결함 생성을 동시에 줄이기 위해 액티브 영역에는 결함 생성을 줄이는 것에 촛점을 맞추고, 격리막 영역에는 버즈 비크 성장을 줄이는 것이 촛점을 맞추어, 스트레스에 의해 결함이 발생하는 영역을 LOCOS 주면부에만 국한시켜 버즈 비크의 성장을 줄이도록 하고, 결함이 발생하면 치명적인 영향을 받는 액티브 영역을 두꺼운 패드 산화막을 사용하여 스트레스를 최소화하도록 한 것이다.In other words, the process focuses on reducing defect generation in the active region in order to simultaneously reduce defect generation due to buzz beak and stress, and focusing on reducing buzz beak growth in the isolation region, where stress defects occur. It is limited to the LOCOS main surface to reduce the growth of the buzz beak and to minimize the stress by using a thick pad oxide film in the active area that is fatally affected if a defect occurs.
상술한 바와 같이 본 발명에 의하면, 기존 NSL 공정과 SILO 공정의 장점인 버즈 비크 감소를 최대한 이용하면서도 상기 공정의 단점인 스트레스에 의한 액티브 영역의 결함 생성을 두꺼운 패드 산화막과 얇은 질화막을 이용하여 방지할 수 있게 된다.As described above, according to the present invention, it is possible to prevent the generation of defects in the active region due to the stress, which is a disadvantage of the process by using a thick pad oxide film and a thin nitride film while maximizing the reduction of the buzz beak which is an advantage of the existing NSL process and the SILO process. It becomes possible.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950024919A KR0186082B1 (en) | 1995-08-12 | 1995-08-12 | Device Separation Method of Semiconductor Devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950024919A KR0186082B1 (en) | 1995-08-12 | 1995-08-12 | Device Separation Method of Semiconductor Devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970013187A KR970013187A (en) | 1997-03-29 |
| KR0186082B1 true KR0186082B1 (en) | 1999-04-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950024919A Expired - Fee Related KR0186082B1 (en) | 1995-08-12 | 1995-08-12 | Device Separation Method of Semiconductor Devices |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0186082B1 (en) |
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1995
- 1995-08-12 KR KR1019950024919A patent/KR0186082B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR970013187A (en) | 1997-03-29 |
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