KR0186019B1 - Method of processing trench capacitor cell - Google Patents
Method of processing trench capacitor cell Download PDFInfo
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- KR0186019B1 KR0186019B1 KR1019910000473A KR910000473A KR0186019B1 KR 0186019 B1 KR0186019 B1 KR 0186019B1 KR 1019910000473 A KR1019910000473 A KR 1019910000473A KR 910000473 A KR910000473 A KR 910000473A KR 0186019 B1 KR0186019 B1 KR 0186019B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000003860 storage Methods 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 4
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 4
- 239000001301 oxygen Substances 0.000 claims abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 238000003693 cell processing method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- -1 oxygen ions Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0147—Manufacturing their gate sidewall spacers
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 트랜치 캐패시터 셀을 형성하기 위한 트랜치 형성 공정에서 기판에 가해지는 손상을 줄이기 위한 것으로, 실리콘 기판의 뒷면에 열을 가한 상태에서 높은 이온 주입 에너지를 사용한 산소 이온 주입 및 어닐링 공정으로 실리콘 기판내의 중간 부분에 산화 영역(SiO2Rrgion)을 형성하는 공정과, 실리콘 기판의 소자 격리 영역에 필드 산화막을 형성하여 활성 영역을 정의하고 활성 영역상에 폴리 게이트, 캡 산화막층을 형성하는 공정과, 상기 폴리 게이트, 캡 산화막층을 마스크로하여 저농도의 n형 불순물 이온을 주입하고 폴리 게이트의 측면에 사이드윌 스페이서를 형성하는 공정과, 상기 사이드월 스페이서가 형성된 폴리 게이트를 마스크로하여 고농도의 불순물 이온을 주입하여 LDD 구조의 소오스/드레인 영역을 형성하는 공정과, 전면에 커패시터 고온 산화막(HTO)을 증착하고 산화막 마스크를 이용한 포토 에치 공정으로 측면 일부와 바닥면이 산화 영역내에 위치되는 트랜치를 형성하는 공정과, 상기 트렌치내에 스토리지 전극층, 커패시터 고유전막, 플레이트 전극층을 차례로 형성하는 공정으로 이루어진다.The present invention is to reduce the damage to the substrate in the trench formation process for forming a trench capacitor cell, and in the silicon substrate by the oxygen ion implantation and annealing process using a high ion implantation energy while applying heat to the back surface of the silicon substrate Forming an oxide region (SiO 2 Rrgion) in the middle portion, forming a field oxide film in the device isolation region of the silicon substrate to define an active region, and forming a poly gate and cap oxide layer on the active region; Implanting low-concentration n-type impurity ions using a poly gate and cap oxide layer as a mask and forming sidewall spacers on the side of the poly gate; Forming a source / drain region of the LDD structure by implantation; Depositing a sheeter high temperature oxide film (HTO) and forming a trench in which a portion of the side surface and a bottom surface are positioned in the oxidation region by a photo etch process using an oxide mask, and sequentially forming a storage electrode layer, a capacitor high dielectric film, and a plate electrode layer in the trench It is made by the process.
Description
제1도(a) 내지 (d)는 종래의 트랜치 커패시터 셀의 공정 단면도.1A to 1D are cross-sectional views of a conventional trench capacitor cell.
제2도(a) 내지 (g)는 본 발명의 트랜치 커패시터 셀의 공정 단면도.2 (a) to (g) are cross-sectional views of a trench capacitor cell of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘 기판 20 : 필드 산화막10 silicon substrate 20 field oxide film
30 : 트렌치 40 : 폴리 게이트30: trench 40: poly gate
50 : 플레이트 전극층 60 : 커패시터 고유전막50 plate electrode layer 60 capacitor high dielectric film
70 : 스토리지 전극층 80 : 캡 산화막70: storage electrode layer 80: cap oxide film
90 : 포토레지스트 100 : 사이트월 스페이서90: photoresist 100: site wall spacer
본 발명은 트랜치 캐패시터 셀(Trench Capacitor Cell)에 관한 것으로, 특히 실리콘 기판(Si-Substrate)을 에치(Etch)하여 트랜치를 형성할 때 발생되는 손상(Damage)으로 인하여 트랜치와 트랜치간의 누전(Leakage)이 발생하는 것을 감소시키는데 적당하도록한 트랜치 캐패시터 셀 공정 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench capacitor cell, and in particular, a leak between a trench and a trench due to damage generated when etching a silicon substrate to form a trench. It relates to a trench capacitor cell processing method which is adapted to reduce this occurrence.
이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 커패시터 제조 공정에 관하여 설명하면 다음과 같다.Hereinafter, a capacitor manufacturing process of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
제1도(a) 내지 (d)는 종래의 트랜치 커패시터 셀의 공정 단면도이다.1 (a) to (d) are cross-sectional views of a conventional trench capacitor cell.
먼저, 제1도(a)에서와 같이, LOCOS(Local Oxidation of Silicon)공정으로 소자간 분리(Isolation)을 위해 실리콘 기판(Silicon Substrate)(1)의 소자 격리 영역에 필드 산화막(Field Oxide)(2)을 형성한다.First, as shown in FIG. 1 (a), a field oxide film (Field Oxide) is formed in an isolation region of a silicon substrate 1 for isolation between devices by a local oxide of silicon (LOCOS) process. 2) form.
이어, 제1도(b)에서와 같이, 상기 필드 산화막(2)에 의해 정의된 활성 영역상에 폴리 게이트(4), 캡 산화막을 형성한후 이를 마스크로 하여 노출된 실리콘 기판(1)에 LDD(Lightly Doped Drain)를 형성하기 위한 저농도의 n형 불순물 이온을 주입한다.Subsequently, as shown in FIG. 1 (b), a poly gate 4 and a cap oxide film are formed on the active region defined by the field oxide film 2 and then exposed to the exposed silicon substrate 1 as a mask. Low concentration n-type impurity ions are implanted to form LDD (Lightly Doped Drain).
그리고 캐패시터 고온 산화막(High Temperature Oxidation; HTO)(8)을 증착하고 마스크없이 건식 식각을 하여 사이드월 스페이서(Side Wall Spacer)(100)을 형성한후 이를 마스크로하여 N+이온 주입을 하여 LDD 구조를 갖는 셀 트랜지스터의 소오스/드레인 영역을 형성한다.In addition, by depositing a high temperature oxide (HTO) (8) capacitor and dry etching without a mask to form a side wall spacer (100) to form a side wall spacer (Side Wall Spacer) (100) and implanted N + ion using a mask as an LDD structure A source / drain region of a cell transistor having is formed.
그리고 제3도(c)~(d)에 도시된 바와 같이, ONO 마스크/산화마스크(Oxide Mask)를 형성하여 실리콘 기판(1)을 에치하여 트랜치(3)를 형성한후 비소(As)이온 주입하여 트랜치(3)부위의 기판을 접점(스토리지 노드 역할을 하는)으로 하여 고유전막을 증착한후 플레이트 전극층(5)을 형성하여 트랜치 구조의 커패시터를 완성한다.As shown in FIGS. 3C to 3D, an ONO mask / oxide mask is formed to etch the silicon substrate 1 to form the trench 3, and then arsenic (As) ions are formed. After the injection, a high dielectric film is deposited using the substrate on the trench 3 as a contact point (which serves as a storage node), and then a plate electrode layer 5 is formed to complete the trench structure capacitor.
이와 같은 종래의 트랜치 커패시터 셀 공정 방법은 실리콘 기판(1)을 에치하여 트랜치를 형헝할 때 생기는 손상에 의해 트랜치간의 누전(Leakage)이 발생하는 문제점이 있다.The conventional trench capacitor cell processing method has a problem in that leakage occurs between trenches due to damage caused by etching the silicon substrate 1 to form the trench.
본 발명은 상기한 종래의 기술의 문제점을 해결하기 위한 것으로써, 실리콘 기판(Si-Substrate)을 에치(Etch)하여 트랜치를 형성할 때 발생되는 손상(Damage)으로 인하여 트랜치와 트랜치간의 누전(Leakage)이 발생하는 것을 감소시키는데 적당하도록한 트랜치 캐패시터 셀 공정 방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, the leakage (leakage) between the trench and the trench due to the damage (damage) generated when etching the silicon substrate (Si-Substrate) to form a trench It is an object of the present invention to provide a trench capacitor cell processing method that is suitable to reduce the occurrence of c).
이하, 첨부된 도면을 참고하여 본 발명의 트랜치 커패시터 셀 공정에 관하여 설명하면 다음과 같다.Hereinafter, a trench capacitor cell process of the present invention will be described with reference to the accompanying drawings.
제2도(a) 내지 (g)는 본 발명의 트랜치 커패시터 셀의 공정 단면도이다. 본 발명의 트랜치 커패시터 셀 공정 방법은 트랜치 부분에서 발생하는 기판 손상에 의한 누설 전류 증가의 문제를 해결하기 위하여 실리콘 기판(10)의 내부에 산화 영역(SiO2Region)을 형성하고 후속 공정을 진행한 것이다.2 (a) to (g) are process cross-sectional views of trench capacitor cells of the present invention. In the trench capacitor cell processing method of the present invention, an oxide region (SiO 2 region) is formed in the silicon substrate 10 and a subsequent process is performed in order to solve the problem of an increase in leakage current caused by damage to the substrate generated in the trench portion. will be.
먼저, 제2도(a)에 도시된 바와 같이, 실리콘 기판(10)의 뒷면에 약 600℃의 열을 가한 상태에서 높은 이온 주입 에너지로 산소 이온을 실리콘 기판(10)에 주입한후 어닐링 공정으로 이를 확산시켜 산화막 영역(SiO2Region)을 형성한다.First, as shown in FIG. 2 (a), an annealing process is performed after implanting oxygen ions into the silicon substrate 10 with high ion implantation energy while applying about 600 ° C. heat to the back surface of the silicon substrate 10. This is then diffused to form an oxide film region (SiO 2 region).
그리고 제2도(b)에서와 같이, LOCOS 공정으로 실리콘 기판(10)의 소자 격리 영역에 필드 산화막(20)을 형성하여 활성 영역을 정의한다.As shown in FIG. 2B, a field oxide film 20 is formed in the device isolation region of the silicon substrate 10 by the LOCOS process to define the active region.
이어, 제2도(c)에서와 같이, 상기 활성 영역성에 폴리 게이트(40), 캡 산화막(80)을 형성하기 위한 폴리 실리콘층과 캡 산화막을 형성하고 포토레지스트(90)를 증착한다.Subsequently, as shown in FIG. 2C, a polysilicon layer and a cap oxide layer for forming the poly gate 40 and the cap oxide layer 80 are formed in the active region, and the photoresist 90 is deposited.
상기 포토레지스트(90)층을 선택적으로 패터닝하여 그를 마스크로하여 제2도(d)에서와 같이, 상기 폴리 실리콘층과 캡 산화막을 선택적으로 식각하여 폴리 게이트(40), 캡 산화막(80)층을 형성한다.By selectively patterning the photoresist 90 layer and using it as a mask, the polysilicon layer and the cap oxide layer are selectively etched as shown in FIG. 2 (d) to form the poly gate 40 and the cap oxide layer 80 To form.
이어, 상기 폴리 게이트(40), 캡 산화막(80)층을 마스크로하여 저농도의 n형 불순물 이온을 주입한다.Subsequently, a low concentration of n-type impurity ions is implanted using the poly gate 40 and the cap oxide layer 80 as a mask.
그리고 제2도(e)에서와 같이, 전면에 게이트 측벽 형성용 물질층을 형성하고 에치백하여 폴리 게이트(40)의 측면에 사이드월 스페이서(100)를 형성한다.As shown in FIG. 2E, the sidewall spacer 100 is formed on the side of the poly gate 40 by forming and etching back the material layer for forming the gate sidewall.
이어, 상기 사이드월 스페이서(100)가 형성된 폴리 게이트(40)를 마스크로하여 고농도의 불순물 이온을 주입하여 LDD 구조의 소오스/드레인 영역을 형성한다.Subsequently, a high concentration of impurity ions are implanted using the poly gate 40 on which the sidewall spacers 100 are formed as a mask to form source / drain regions of the LDD structure.
이어, 제2도(f)에서와 같이, 전면에 커패시터 고온 산화막(HTO)을 증착하고 산화 마스크를 이용한 포토 에치 공정으로 트랜치(30)를 형성한다.Subsequently, as shown in FIG. 2F, a capacitor high temperature oxide film HTO is deposited on the entire surface, and a trench 30 is formed by a photo etch process using an oxide mask.
이때, 트렌치(30)의 측면 일부와 바닥면은 산화 영역내에 위치된다.At this time, a portion of the side surface and the bottom surface of the trench 30 are located in the oxidation region.
그리고 제2도(g)에서와 같이, 상기 트렌치(30)에 노드 폴리(Node Poly)를 증착하여 스토리지 전극층(70)을 형성한다.As shown in FIG. 2G, a node poly is deposited on the trench 30 to form a storage electrode layer 70.
이어, 스토리지 전극층(70)상에 고유전 물질(High Dielectric Material)을 사용하여 커패시터 고유전막(60)을 형성한다.Subsequently, the capacitor high dielectric film 60 is formed on the storage electrode layer 70 by using a high dielectric material.
그리고 플레이트 폴리(Plate Poly)를 증착하여 플레이트 전극층(50)을 형성하여 트랜치 커패시터 셀을 완성한다.Then, plate poly is deposited to form a plate electrode layer 50 to complete the trench capacitor cell.
이와 같이 본 발명의 트렌치 커패시터 셀은 실리콘 기판에 산소 이온을 주입시켜 어닐링하고 실리콘 기판(10)의 중간 부분에 산화 영역을 형성한후에 후속되는 공정을 진행하여 트랜치(30)를 형성하므로 트랜치(30)들간의 누전(Leakage)을 현저히 감소시키는 효과가 있다.As described above, the trench capacitor cell of the present invention implants annealing by implanting oxygen ions into the silicon substrate, forms an oxide region in the middle portion of the silicon substrate 10, and then proceeds to a subsequent process to form the trench 30. There is an effect of significantly reducing the leakage (leakage) between them.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000473A KR0186019B1 (en) | 1991-01-15 | 1991-01-15 | Method of processing trench capacitor cell |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000473A KR0186019B1 (en) | 1991-01-15 | 1991-01-15 | Method of processing trench capacitor cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920015431A KR920015431A (en) | 1992-08-26 |
| KR0186019B1 true KR0186019B1 (en) | 1999-03-20 |
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|---|---|---|---|
| KR1019910000473A KR0186019B1 (en) | 1991-01-15 | 1991-01-15 | Method of processing trench capacitor cell |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0186019B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970067767A (en) * | 1996-03-12 | 1997-10-13 | 문정환 | Method for forming a separation film of a semiconductor element |
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1991
- 1991-01-15 KR KR1019910000473A patent/KR0186019B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR920015431A (en) | 1992-08-26 |
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