KR0184154B1 - One chip micro-computer unit - Google Patents

Abstract

The present invention relates to a one-chip micro-computer unit having a CPU and a memory, and to be connected to an external device through a plurality of external connection pins including test pins. And an output signal selector. The first switch and the second switch are switched according to a signal input through a test pin to connect or disconnect an internal data bus and an internal address bus connected between the CPU and the memory. The third switch and the fourth switch are connected complementary to the first switch and the second switch according to a signal input through the test pin, and connect or disconnect the internal data bus and the internal address bus connected between the external connection pin and the memory. do. The output signal selector is controlled by a signal input through a test pin, and selects one of a signal generated from internal logic and a signal input through an external connection pin and outputs it as an operation control signal of a memory.

Description

One chip micro computer

1 is a schematic diagram showing the configuration of a typical one-chip microcomputer.

2 is a schematic diagram illustrating a simple configuration of a one-chip microcomputer according to the present invention.

* Explanation of symbols for main parts of the drawings

10: CPU 20: Memory (RAM)

SW1 ~ SW4: Switch MUX: Output Selector

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a one-chip microcomputer, and more particularly, to a one-chip microcomputer in which memory can be easily tested in a one-chip microcomputer with a large memory capacity.

One-chip microcomputer means a microcomputer provided with a central processing unit, a memory device, a clock generator, an input / output control unit, etc. on one silicon chip, and is widely used for a control device.

Referring to FIG. 1, the configuration and operation between an internal CPU and a memory in the one-chip microcomputer as described above are as follows.

The CPU 10 and the memory 20 are connected by an internal data bus DB and an address bus AB. The CPU 10 designates the address of the memory 20 through the internal address bus AB, and reads / writes specific data to the designated address area of the memory 20. At this time, the data is input and output through the data bus (DB).

In this case, when a malfunction occurs in the external device connected to the one-chip microcomputer or a specific system, the inspector or the user may not check or delete the contents of the memory provided in the one-chip microcomputer by randomly deleting, correcting, or accessing. Therefore, in this case, it is difficult to identify the cause of the malfunction in the current system.

Although checking the contents of data stored in the RAM is an essential process for error correction, a data error occurs because the conventional one-chip microcomputer cannot access the internal data through an operation from the outside. It is difficult to determine the cause of the malfunction because the cause of the malfunction is not usually at the source source but at the data error that occurs during the operation of the one-chip microcomputer.

Also, the larger the built-in memory, the larger the amount of I / O data to be tested. For example, a capacity of 16KB requires at least 16K test vectors for writing data, 16K for reading test vectors, and 32K test vectors for all. In addition, a test vector is needed to test the logic blocks of peripheral devices such as CPUs and timers other than memory, so the size of the entire test vector becomes very large.

However, not only the test vector storage capacity of the test device should be very large, but also the time required for the test increases, resulting in increased test costs.

Accordingly, the present invention includes a switch capable of cutting off or connecting an internal address bus and an internal data bus by a control signal input through a test pin, and controlling the above-described switch through a pin provided outside a chip such as an MCU to control the internal memory. Its purpose is to make it accessible.

One-chip microcomputer according to the present invention for this purpose has a CPU and a memory, and is connected to an external device through a plurality of external connection pins including a test pin, the first to fourth switch and the output signal This includes a selector.

The first switch and the second switch are switched according to a signal input through a test pin to connect or disconnect an internal data bus and an internal address bus connected between the CPU and the memory.

The third switch and the fourth switch are connected complementary to the first switch and the second switch according to a signal input through the test pin, and connect or disconnect the internal data bus and the internal address bus connected between the external connection pin and the memory. do.

The output signal selector is controlled by a signal input through a test pin, and selects one of a signal generated from internal logic and a signal input through an external connection pin and outputs it as an operation control signal of a memory.

A preferred embodiment of the present invention thus made will be described with reference to FIG. 2 is a diagram illustrating a configuration of a one-chip microcomputer according to the present invention, and illustrates a configuration of a switching part for connecting or disconnecting an internal address bus and a data bus according to a state of a signal input through a test pin.

The CPU 10 and the memory 20 are connected by a data bus DB and an address bus AB. The first switch SW1 is connected to the data bus DB, and the second switch SW2 is connected to the address bus AB. These two switches SW1 and SW2 are turned on / off by a control signal input through the test pin.

The memory 20, the first external pin, and the second external pin are connected to each other through the third switch SW3 and the fourth switch SW4. The third switch SW3 and the fourth switch SW4 are also turned on / off by a control signal input through the test pin, and are complementary to the above-described first switch SW1 and second switch SW2. do. That is, when the first switch SW1 and the second switch SW2 are turned on, the third switch SW3 and the fourth switch SW4 are turned off.

The signal input through the third external pin and the signal generated in the internal logic are input to the output signal selector MUX. One of the signals is selected and input to the memory 20 as a signal for controlling the operation of the memory 20. The output signal is selected by a signal input through the test pin.

The operation of the one-chip microcomputer according to the present invention configured as described above is as follows.

In the normal operation mode, when a logic 0 signal is input to the test pin, the third switch SW3 and the fourth switch SW4 are turned off so that the address bus and the data bus are disconnected from the first external pin and the second external pin. . However, at this time, the first switch SW1 and the second switch SW2 are turned on so that the CPU 10 and internal logic are connected to the memory 20 through an address bus and a data bus.

In this case, the output signal selector MUX outputs a signal input from internal logic and is transmitted to the memory 20. Therefore, data and address can be transferred between the CPU 10 and the internal logic and the memory 20, and the read / write operation of the memory is normally performed.

In test mode, a signal of logic 1 is input to the test pin. Accordingly, the third switch SW3 and the fourth switch SW4 are turned on so that the first external pin and the second external pin are connected to the internal address bus AB and the data bus DB. However, at this time, the first switch SWl and the second switch SW2 are turned off to block the address bus AB and the data bus DB between the CPU 10 and the memory 20.

In this case, the output signal selector MUX outputs a signal input from the external device through the third external pin and transmits the signal to the memory 20. Therefore, the read / write operation of the memory 20 is performed by a signal input through the third external pin, and the necessary address and data are turned on by the third input on which the inputs to the first external pin and the second external pin are turned on. The memory 20 is transferred to the memory 20 through the switch SW3 and the fourth switch SW4.

Therefore, in the test mode, the memory inside the one-chip microcomputer can be directly controlled from the outside.

When testing the built-in memory in the one-chip microcomputer according to the present invention, unlike the conventional case of storing and reading data in accordance with the instruction cycle of the CPU, since the control signal can be directly input through an external pin, the memory size is increased. Although very large, the size of the memory for storing the test vector is reduced, and the time required for the test is also greatly reduced.

Claims (1)

A one-chip microcomputer having a CPU and a memory and configured to be connected to an external device through a plurality of external connection pins including test pins, the one-chip microcomputer being switched according to a signal input through the test pins. A first switch and a second switch which connect or disconnect the connected internal data bus and the internal address bus; A third switch that is complementary to the first switch and the second switch according to a signal input through the test pin to connect or disconnect an internal data bus and an internal address bus connected between the external connection pin and the memory; A switch and a fourth switch; One-chip microcontroller including an output signal selector which is controlled according to a signal input through the test pin and selects one of a signal generated from internal logic and a signal input through the external connection pin and outputs the signal as an operation control signal of the memory. computer.