KR0179810B1 - Output buffer circuit of memory - Google Patents

Abstract

The present invention relates to a data output buffer circuit of a memory that reduces a slope of output data by reducing a slope of a drive signal of an output buffer when a high level power voltage is supplied. Means for achieving the power supply voltage level detection means for detecting the level of the power supply voltage supplied from the outside and outputs a detection signal of the high and low levels corresponding thereto; When the signal detected by the power supply voltage level detecting means is at a low level, the signal is disabled to output a power supply voltage and a ground voltage (hereinafter referred to as a first generation voltage), or when it is at a high level, it is enabled to prevent bouncing of the output stage. First and second voltage generating means for outputting a voltage dropped from the power supply voltage and an increased voltage from the ground voltage (hereinafter referred to as a second generation voltage); If the level of the inversion signal of the output enable signal input from the outside is low, the driving signal of low or high level is generated according to the level of the data signal input from the sense amplifier, and the first and second voltage generating means output the first and second voltages. When the output signal is output as it is or the level of the inverted signal of the output enable signal is high, the low and high level driving signals generated according to the level of the data signal input from the sense amplifier are output to the first and second voltages. Drive signal generation means for outputting a signal having a small slope by the second generation voltage output from the generation means; And an output buffer which is driven by the drive signal generated by the drive signal generation means and outputs data.

Description

Output buffer circuit of memory

1 is a data output buffer circuit diagram of a conventional memory.

2 is an input / output waveform diagram of each part of FIG.

3 is a data output buffer circuit diagram of a memory according to the present invention.

4 is a view showing characteristics of an output voltage of the voltage generator of FIG.

5 is an input / output waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

100: power supply voltage level detection unit 101: voltage generation unit

102: drive signal generator 103: output buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer circuit of a memory, and more particularly, to reduce bouncing of output data by reducing a slope of a drive signal of an output buffer when a high level power supply voltage is supplied. The present invention relates to an output buffer circuit.

As shown in FIG. 1, a data output buffer circuit of a conventional memory includes an output buffer driving signal OP corresponding to an inversion signal ODE of an output enable signal input from an external device and data output from a sense amplifier, A drive signal generator 1 for generating (ON), and an output buffer for driving output by the output buffer drive signals OP and (ON) output from the drive signal generator 1, and outputting output data ( It consists of 2).

The drive signal generator 1 may include an inverter I1 inverting and outputting an inversion signal ODE of an output enable signal input from the outside, and an inverter inverting and outputting data SA output from a sense amplifier ( Ia), a NOR gate NR for combining the signals output from the inverters I1 and I2, respectively, and an inverted signal of the signal output from the inverter I2 and the output enable signal input from the outside. A NAND gate ND for NAND, an inverter I3 for inverting a signal output from the NOR gate NR to output a driving signal OP, and a signal output from the NAND gate ND Inverter I4 is configured to invert V to output the driving signal ON.

The output buffer 2 includes a PMOS transistor MP having a source voltage VCC terminal connected to a source terminal, a driving signal OP line of the driving signal generator 1 connected to a gate terminal, and a drain. A drain terminal of the PMOS transistor MP is connected to a terminal thereof, an output data line is connected to the terminal, and a driving signal ON line of the driving signal generator 1 is connected to a gate terminal thereof. An NMOS transistor NP connected to a ground voltage VSS terminal, a resistor R1 connected between a source terminal of the PMOS transistor MP and an output data OUT line, and the NMOS transistor NP. ) And a resistor (R2) and a capacitor (C2) connected in parallel between the output data (OUT) line.

The operation of the data output buffer circuit of the conventional memory configured as described above will be described with reference to FIG.

First, when the inverted signal ODE of the output enable signal input from the outside is input at a low level, the input low signal ODE is inverted through the inverter I1 in the drive signal generator 1 and is high. It is output as a signal.

Subsequently, the NOR gate NR receives a high signal output from the inverter I1 at one input terminal and outputs a low signal regardless of the signal applied to the other input terminal, and the output high signal is the inverter I3. Inverted through) and output as a low-level drive signal (OP).

The NAND gate ND receives the low signal ODE input from the outside to the other input terminal and outputs a high signal regardless of the signal applied to the one input terminal, and the output high signal is the inverter I4. Inverted through to output the low-level drive signal (ON).

Accordingly, the PMOS transistor MP in the output buffer 2 is turned off by applying a high signal output from the inverter I3 to a gate terminal, and the NMOS transistor NP is turned off to the gate terminal. It is turned off by receiving the low signal output from I4).

Therefore, as shown in FIG. 2E, the output buffer 2 outputs the voltage obtained by dividing the power supply voltage VCC into the resistors R1 and R2 as data OUT.

On the other hand, when the external control signal ODE is input at a high level, the input high signal ODE is output as a low signal through the inverter I1.

At this time, when the data SA output from the sense amplifier is input at a high level, the input high signal SA is output as a low signal through the inverter I2.

Then, the NOR gate NR receives a low signal output from the inverter I1 to one terminal and a low signal output from the inverter I2 to the other input terminal to output the high signal. The output high signal is output as a low level driving signal OP via the inverter I3.

The NAND gate ND receives a low signal output from the inverter I2 at one input terminal and a NAND combination of a high signal ODE input from the outside to the other input terminal to generate a high signal. The output high signal is output as the low level drive signal ON via the inverter I4.

Accordingly, the PMOS transistor MP is turned on by receiving a low signal output from the inverter I3 to a gate terminal, and the NMOS transistor NP is output from the inverter I4 to a gate terminal. It is turned off by receiving a low signal.

Therefore, as shown in (e) of FIG. 4, the output buffer 2 outputs the high level data OUT.

On the other hand, when a low signal is input from the sense amplifier, the input low signal is output as a high signal through the inverter I2.

Then, the NOR gate NR receives a low signal outputted from the inverter I1 to one input terminal and a high signal outputted from the inverter I2 to the other input terminal. The low signal is output as a high signal OP via the inverter I3.

The NAND gate ND receives a high signal output from the inverter I2 to one input terminal, receives a high signal input from the outside to the other input terminal, and outputs a low signal. The output low signal is output as the high signal ON via the inverter I4.

Accordingly, the PMOS transistor MP is turned off by receiving a high signal OP output from the inverter I3 at a gate terminal thereof, and the NMOS transistor NP is turned off at the gate terminal of the inverter I4. The low level data OUT is output because the signal is turned on by receiving the high signal ON.

However, the data output buffer circuit of the conventional memory increases the slope of the output data by increasing the size of the driving signal generator in order to increase the data transfer rate when the low-level power supply voltage is supplied. When supplied, since the slope of the output data becomes larger, when the output data transitions, the bounce of the output stage is increased, thereby causing a malfunction.

Accordingly, an object of the present invention is to provide a data output buffer circuit of a memory that reduces the slope of output data by reducing the slope of a drive signal of the output buffer when a high level power voltage is supplied. .

Means for achieving the object of the present invention comprises a power supply voltage level detection means for detecting the level of the power supply voltage supplied from the outside and outputs a detection signal of the high and low level corresponding to; When the signal detected by the power supply voltage level detecting means is at a low level, the signal is disabled to output a power supply voltage and a ground voltage (hereinafter referred to as a first generation voltage), or when it is at a high level, it is enabled to prevent bouncing of the output stage. First and second voltage generating means for outputting a voltage dropped from the power supply voltage and an increased voltage from the ground voltage (hereinafter referred to as a second generation voltage); If the level of the inverted signal of the output enable signal input from the outside is low, the driving signal of the low or high level is generated according to the level of the data signal input from the sense amplifier, and the first and second voltage generating means output the first and second voltages. When the output signal is output as it is or the level of the inverted signal of the output enable signal is high, the low and high level driving signals generated according to the level of the data signal input from the sense amplifier are output to the first and second voltages. Drive signal generation means for outputting a signal having a small slope by the second generation voltage output from the generation means; And an output buffer which is driven by the drive signal generated by the drive signal generation means and outputs data.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the output buffer circuit of the memory according to the present invention detects the level of the power supply voltage VCC supplied from the outside and outputs the detection signals HP and HN of the corresponding levels, respectively. The voltage generator 11 to generate predetermined voltages TN and TP by the power supply voltage level detection unit 100 and the detection signals HP and HN output from the power supply voltage level detection unit 100, respectively. And a voltage generator 101 composed of (21), a signal (ODE) and a sense amplifier (not shown) input from the outside by the voltages TN and TP output from the voltage generator 101. To the drive signal generator 102 generating the output buffer drive signals OP and ON according to the output data, and to the drive signals OP and ON generated by the drive signal generator 102. It consists of an output buffer 103 which is driven by and outputs data OUT.

The power supply voltage level detection unit 100 includes an NMOS transistor N1 having a power supply voltage VCC terminal and its gate terminal commonly connected to a drain terminal, a source terminal of the NMOS transistor N1 and a drain terminal thereof. A NMOS transistor N2 having a gate terminal of which is commonly connected, a source terminal and an output line of the NMOS transistor N2 are commonly connected to a drain terminal thereof, and a power supply voltage VCC terminal is connected to a gate terminal thereof. An NMOS transistor N3 having a ground voltage VSS terminal connected to a source terminal, and an inverter I1-I3 having an output line and an input / output terminal of the NMOS transistor N3 sequentially connected.

In the voltage generator 11 of the voltage generator 101, a voltage voltage VCC terminal is connected to a source terminal, and a detection signal HP line of the power supply voltage level detection unit 100 is connected to a gate terminal. A MOS transistor P1, a drain terminal of the PMOS transistor P1, a drain terminal of the PMOS transistor P1, and an NMOS transistor N4 connected to a gate terminal thereof, a drain terminal of the NMOS transistor N4 of a source terminal, and The NMOS transistor N5 connected to its gate terminal, the source terminal of the NMOS transistor N5 and the output voltage TN line are commonly connected to the drain terminal, and the power supply voltage VCC terminal is connected to the gate terminal. An NMOS transistor N6 connected to the drain terminal, a source terminal of the NMOS transistor N6 is connected to a drain terminal, and a detection signal HN line of the power supply voltage level detection unit 100 is connected to a gate terminal of the NMOS transistor N6, Ground voltage at the source terminal An NMOS transistor N7 having a VSS terminal connected thereto, a power supply voltage VCC terminal connected to a source terminal, a ground voltage VSS terminal connected to a gate terminal, and the output voltage TN connected to a drain terminal. It consists of the PMOS transistor P2 with which a line is connected.

In addition, the voltage generator 21 of the voltage generator 101 is connected to a source voltage VCC terminal at a source terminal and connected to a detection signal HN line of the power supply voltage level detector 100 at a gate terminal. A PMOS transistor P3 to be connected, a drain terminal of the PMOS transistor P3 to a source terminal, a ground voltage VSS terminal to a gate terminal, and a PMOS transistor P4 connected to the source terminal. A PMOS transistor P5 having a common drain terminal and an output voltage TP line of the PMOS transistor P4 connected thereto, and a drain terminal thereof connected to a gate terminal thereof, and a PMOS transistor P5 connected to a source terminal thereof. PMOS transistor P6 having a drain terminal connected thereto and a drain terminal thereof connected to a gate terminal thereof, a drain terminal of the PMOS transistor P6 connected to a drain terminal thereof, and a power supply voltage level detector A detection signal (HN) line of 100 is connected, the NMOS transistor (N8) to which the ground voltage (VSS) terminal is connected to a source terminal, the drain terminal and the output voltage (TP) line is commonly connected, the gate terminal The NMOS transistor N9 is connected to a power supply voltage VCC terminal and a ground voltage VSS terminal is connected to a source terminal.

The driving signal generator 102 may include an inverter I4 for inverting an output enable signal input from the outside, an inverter I5 for inverting a data signal input from a sense amplifier, and the inverter ( NOR gate NOR for combining the signals output from I4) and I5 respectively, NAND gate NAND for NAND combining signals output from the inverters I4 and I5, and input from the outside It is enabled only when the signal ODE is low, and is enabled only when the inverters IN1 and IN3 respectively invert the outputs of the noble and NAND gates, and the signal ODE input from the outside is high. Inverters IN2 and IN4 that invert the outputs of the NOR and NAND gates and NAND, and signals output from the inverters IN2 and IN4 to the first and second voltage generators. It is turned on by the voltages (TN) and (TP) output from (101) and outputs as it is, or the slope is operated. And the transfer gates T1 and T2 for output.

Since the configuration of the output buffer 103 is the same as in the prior art, the same reference numerals are added, and the description of the configuration will be omitted.

The operation of the data output buffer circuit of the memory according to the present invention configured as described above will be described in detail with reference to FIGS. 4 and 5 as follows.

First, when the low level power supply voltage VCC is supplied, a low signal is output through the common output terminal of the NMOS transistors N2 and N3 in the power supply voltage level detection unit 100. A low level detection signal HN is output as shown by the solid line in FIG. 5B after sequentially passing through the inverters I1 and I2.

The low signal HN output from the inverter I2 is output as a high level detection signal HP as shown by solid lines in FIG. 5A through the inverter I3.

Therefore, the voltage generators 11 and 21 in the voltage generator 101 are disabled by the low signal HN and the high signal HP output from the inverters I2 and I3, respectively. As shown by solid lines in (c) and (d) of FIG. 5, a high voltage TN and a low voltage TP are generated and output, respectively.

At this time, when the inverted signal ODE of the output enable signal input from the outside is input at the low level, the input low signal ODE is inverted through the inverter I4 in the drive signal generator 102 to be high. It is output as a signal.

Accordingly, the inverters IN1 and IN3 are enabled by the low level external input signal ODE and the high signal output from the inverter I4, and the inverters IN2 and IN4 are low level. It is disabled by the external input signal ODE and the high signal output from the inverter I4.

The NOR gate NOR receives a high signal output from the inverter I4 at one pressure terminal and outputs a low signal regardless of the signal applied to the other input terminal, and the output high signal is the inverter IN1. Inverted through), it is output as a high level driving signal OP.

The NAND gate receives the low signal ODE input from the outside to the other input terminal and outputs a high signal regardless of the signal applied to the one input terminal, and the output high signal is the inverter IN3. The inverted signal is outputted through the low level driving signal ON.

Therefore, the PMOS transistor MP in the output buffer 103 is turned off by applying a high signal output from the inverter IN1 to the gate terminal, and the NMOS transistor NP is connected to the gate terminal. It is turned off by receiving a low signal output from IN3).

Therefore, as shown in FIG. 5 (i), the output buffer 103 outputs the voltage obtained by dividing the power supply voltage VCC into the resistors R1 and R2 as data OUT.

On the other hand, when the external control signal ODE is input at a high level, the input high signal ODE is output as a low signal through the inverter I4.

Accordingly, the inverters IN1 and IN3 are disabled by the high signal ODE and the low signal output from the inverter I4, and the inverters IN2 and IN4 are the high signal ODE. And the low signal output from the inverter I4.

At this time, when the data SA output from the sense amplifier is input at a high level, the input high signal SA is output as a low signal through the inverter IN5.

Then, the NOR gate NOR receives a low signal output from the inverter I4 to one input terminal, and receives a low signal output from the inverter I5 to the other input terminal to combine the NOR to generate a high signal. The output high signal is output as a low signal via the enabled inverter IN2.

The low signal output from the inverter IN2 passes through the transfer gate T1 which is turned on by the high voltages TN and TP generated by the voltage generators 11 and 21, respectively. The low level drive signal OP is output.

In addition, the NAND gate NAND receives a low signal output from the inverter I5 to one input terminal, and receives a high signal ODE input from the outside to the other input terminal. The high signal is output as a low signal via the inverter IN4.

The low signal output from the inverter IN4 is turned on by the high voltage TN and the low voltage TP generated by the voltage generators 11 and 21, respectively. It is output as a low level driving signal OP.

Accordingly, the PMOS transistor MP is turned on by receiving a low signal output from the transfer gate T1 to a gate terminal, and the NMOS transistor NP is connected to the gate terminal from the transfer gate T2. It is turned off by receiving the output low signal.

Therefore, as shown in (i) of FIG. 5, the output buffer 103 outputs high level data OUT.

On the other hand, when a low signal is input from the sense amplifier, the input low signal is output as a high signal through the inverter I5.

Then, the NOR gate NOR receives a low signal output from the inverter I4 to one input terminal and a high signal output from the inverter I5 to the other input terminal to combine the NOR to generate a low signal. The output low signal is sequentially output through the inverter IN2 and the transfer gate T1 as a high signal OP.

The NAND gate ND receives a high signal output from the inverter I5 to one input terminal, receives a high signal input from the outside to the other input terminal, and outputs a low signal by NAND combining. The output low signal is sequentially outputted through the inverter IN4 and the transfer gate T2 as a high signal ON.

Accordingly, the PMOS transistor MP is turned off by receiving a high signal OP output from the transfer gate T1 to a gate terminal, and the NMOS transistor NP is connected to the transfer gate at a gate terminal thereof. Since the high signal ON output from T2 is turned on, the low level data OUT is output.

On the other hand, when the high level power supply voltage VCC is supplied, a high signal is output through the common output terminal of the NMOS transistors N2 and N3 in the power supply voltage level detection unit 100, and the output high signal is A high level detection signal HN is output as shown by the dotted line in FIG. 5B after sequentially passing through the inverters I1 and I2.

The high signal HN output from the inverter I2 is output as a low level detection signal HP as shown by a dotted line in FIG. 5A through the inverter I3.

Accordingly, the voltage generators 11 and 12 are enabled by the high signal HN and the low signal HP output from the inverters I2 and I3, respectively. As shown by the dotted lines in c) and (d), a voltage TN that is greatly dropped from the power supply voltage VCC and a voltage TP that is greatly increased in the ground voltage VSS are generated.

At this time, when the inverted signal ODE of the output enable signal input from the outside is input at the low level, as described above, the inverters IN1 and IN3 are enabled to enable the noah gate NOR and the NAND gate ( The low and high signals respectively output from the NAND are inverted through the enabled inverters IN1 and IN3 and output as high signals OP and low signals ON.

Therefore, the PMOS transistor MP in the output buffer 103 is turned off by applying a high signal output from the inverter IN1 to the gate terminal, and the NMOS transistor NP is connected to the gate terminal. It is turned off by receiving a low signal output from IN3).

Therefore, as shown in FIG. 5 (i), the output buffer 103 outputs the voltage obtained by dividing the power supply voltage VCC into the resistors R1 and R2 as data OUT.

On the other hand, when the external control signal (ODE) is input at a high level, as described above, the inverters IN2 and IN4 are enabled.

At this time, when the data SA output from the sense amplifier is input at a high level, the input high signal SA is output as a low signal through the inverter IN5.

Then, the NOR gate NOR receives a low signal output from the inverter I4 to one input terminal, and receives a low signal output from the inverter I5 to the other input terminal to combine the NOR to generate a high signal. The output high signal is output as a low signal via the enabled inverter IN2.

On the other hand, the transfer gates T1 and T2 increase turn-on resistances to voltages TN and TP generated from the voltage generators I1 and I2, respectively.

Since the low signal output from the inverter IN2 passes through the transfer gate T1 in which the turn-on resistance is greatly increased, a low level driving signal having a small slope as shown by a solid line in FIG. OP).

In addition, the NAND gate NAND receives a low signal output from the inverter I5 to one input terminal, and receives a high signal ODE input from the outside to the other input terminal to perform a NAND combination to generate a high signal. The high signal is output as a low signal via the inverter IN4.

Since the low signal output from the inverter IN4 passes through the transfer gate T2, the low signal is output as the low level driving signal ON as shown in FIG.

Accordingly, the PMOS transistor MP is turned on by receiving a low signal output from the transfer gate T1 to a gate terminal, and the NMOS transistor NP is connected to the gate terminal from the transfer gate T2. It is turned off by receiving the output low signal.

Therefore, as shown in FIG. 5 (j), the output buffer 103 outputs high level data OUT.

On the other hand, when a low signal is input from the sense amplifier, the input low signal is output as a high signal through the inverter I5.

Then, the NOR gate NOR receives a low signal output from the inverter I4 to one input terminal and a high signal output from the inverter I5 to the other input terminal to combine the NOR to generate a low signal. The output low signal is sequentially output through the inverter IN2 and the transfer gate T1 as a high signal OP.

The NAND gate ND receives a high signal output from the inverter I5 to one input terminal, receives a high signal input from the outside to the other input terminal, and outputs a low signal by NAND combining. The output low signal is sequentially outputted through the inverter IN4 and the transfer gate T2 as a high signal ON.

Accordingly, the PMOS transistor MP is turned off by receiving a high signal OP output from the transfer gate T1 to a gate terminal, and the NMOS transistor NP is turned on to transmit a data to the gate terminal. Since the high signal ON output from T2 is turned on, the low level data OUT is output.

As described in detail above, the output buffer circuit of the memory according to the present invention reduces the bounce of the output stage by increasing the transition time of the output data by reducing the slope of the output buffer driving signal when supplied with a high level power supply voltage. There is an effect that can prevent the malfunction.

Claims (5)

Power supply voltage level detection means for detecting a level of a power supply voltage supplied from the outside and outputting high and low detection signals corresponding thereto; When the signal detected by the power supply voltage level detecting means is at a low level, the signal is disabled to output a power supply voltage and a ground voltage (hereinafter referred to as a first generation voltage), or when it is at a high level, it is enabled to prevent bouncing of the output stage. First and second voltage generating means for outputting a voltage dropped from the power supply voltage and an increased voltage from the ground voltage (hereinafter referred to as a second generation voltage); If the level of the inverted signal of the output enable signal input from the outside is low, the driving signal of the low or high level is generated according to the level of the data signal input from the sense amplifier, and the first and second voltage generating means output the first and second voltages. When the output signal is output as it is or the level of the inverted signal of the output enable signal is high, the low and high level driving signals generated according to the level of the data signal input from the sense amplifier are output to the first and second voltages. Drive signal generation means for outputting a signal having a small slope by the second generation voltage output from the generation means; And an output buffer which is driven by a drive signal generated by the drive signal generating means and outputs data. The method of claim 1, wherein the power supply voltage level detecting means comprises: a first NMOS transistor having a power supply voltage terminal and its gate terminal commonly connected to a drain terminal, and a source terminal of the first NMOS transistor and a drain terminal thereof; A second NMOS transistor having a gate terminal connected in common; a source terminal and an output line of the second NMOS transistor connected to a drain terminal in common; and a power voltage terminal connected to a gate terminal; and a ground voltage terminal connected to a source terminal. And a third NMOS transistor connected to the first NMOS transistor, and a first to third inverter in which an output line and an input / output terminal of the third NMOS transistor are sequentially connected to each other. The first PMOS transistor of claim 1, wherein the first voltage generating means comprises: a first PMOS transistor having a power supply voltage terminal connected to a source terminal, and a first detection signal line of the power supply voltage level detecting means connected to a gate terminal; A first NMOS transistor coupled to a drain terminal of the first PMOS transistor and a gate terminal thereof, and a second NMOS transistor coupled to a source terminal of the first NMOS transistor and its gate terminal connected to a drain terminal thereof. And a third NMOS transistor connected to a drain terminal of the source terminal and the first output voltage line of the second NMOS transistor, and to a gate terminal connected to a power supply voltage terminal, and to the drain terminal of the third NMOS transistor. The source terminal of is connected, the second detection signal line of the power supply voltage level detecting means is connected to the gate terminal, the ground voltage terminal is connected to the source terminal And a fourth PMOS transistor, a second PMOS transistor having a source voltage terminal connected to a source terminal, a ground voltage terminal connected to a gate terminal, and a second output voltage line connected to a drain terminal. Memory output buffer circuit. The method of claim 1, wherein the second voltage generating means comprises: a first PMOS transistor connected to a source voltage terminal at a source terminal, and to a second detection signal line of the power supply voltage level detecting means at a gate terminal, and a source terminal; A second PMOS transistor having a drain terminal connected to the first PMOS transistor, a ground voltage terminal connected to a gate terminal, and a drain terminal and a second output voltage line of the second PMOS transistor connected to a source terminal; A third PMOS transistor connected to the drain terminal of the third PMOS transistor, a drain terminal of the third PMOS transistor is connected to a source terminal, and a fourth PMOS transistor of which a drain terminal thereof is connected to the gate terminal thereof; A transistor, a drain terminal of the fourth PMOS transistor is connected to a drain terminal, and a second detection signal line of the power supply voltage level detecting means to a gate terminal; The first NMOS transistor is connected to the source terminal, and the second output voltage line is connected to the drain terminal, the power supply voltage terminal is connected to the gate terminal, and the ground voltage terminal is connected to the source terminal. And a second NMOS transistor connected to the output buffer circuit of the memory. 2. The apparatus of claim 1, wherein the drive signal generating means comprises: a first inverter for inverting an inverted signal of an output enable signal input from an external device; A second inverter for inverting the data signal input from the sense amplifier; A NOR gate for NOR combining the signals output from the first and second inverters; A NAND gate NAND combining the signals output from the first and second inverters; Third and fifth inverters that are enabled only when the inverted signal of the output enable signal is low to invert the outputs of the NOR gate and the NAND gate, respectively; Fourth and sixth inverters which are enabled only when the inverted signal of the output enable signal is high to invert the outputs of the NOR and NAND gates; The signals output from the fourth and sixth inverters are turned on by the first and second generated voltages output from the first and second voltage generating means, and are output as they are, or output of the output signals. An output buffer circuit of a memory, characterized by comprising first and second transfer gates that output a smaller slope.