KR0172440B1 - Nonvolatile Semiconductor Memory Devices Reduce Test Time - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a nonvolatile semiconductor memory device.

2. The technical problem to be solved by the invention

The present invention provides a nonvolatile semiconductor memory device capable of reducing test time by generating various test patterns.

3. Summary of Solution to Invention

A plurality of NAND cell units arranged in a matrix number of rows and columns and having a floating gate type connected in series; a plurality of bit lines connected to one end of the NAND cell units arranged in a same column; Bit lines include a first page buffer including a plurality of unit page buffers connected to bit line groups extending in the first column direction and extending in the first column direction and the second column direction alternately opposite each other; And simultaneously or differently initialize voltage levels of a second page buffer including bit line groups extending in the second column direction and unit page buffers connected to each other, and data latches in the first and second page buffers. By providing a control means capable of generating a variety of data patterns.

4. Important uses of the invention

It is suitably used for high speed semiconductor memory devices.

Description

Nonvolatile Semiconductor Memory Devices Reduce Test Time

1 is a schematic block diagram of a nonvolatile semiconductor memory device according to the prior art.

2 is a diagram illustrating a connection relationship between bit lines and page buffers according to the related art.

3 is a circuit diagram for performing a data loading operation in accordance with the present invention.

4 is a timing diagram of signals used in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to non-volatile semiconductor memory devices that are electrically erasable and programmable.

Non-volatile semiconductor memory is becoming more and more dense, and its performance and operation speed are also improving. In general, a nonvolatile semiconductor memory uses a floating gate transistor having a floating gate, a control gate, a source, and a drain as a memory cell. These memory cells are arranged in a matrix of rows and columns, control gates of memory cells arranged in the same rows are connected to a plurality of word lines, and drains of cells arranged in the same columns are connected to a plurality of bit lines. have. The memory cells, the plurality of word lines and the plurality of bit lines constitute a memory cell array. In such a nonvolatile semiconductor memory, data stored in memory cells connected to one selected word line of a plurality of word lines is read out temporarily through the plurality of bit lines in order to improve an operation speed. Such a read operation is called a page read operation. Read data on the plurality of bit lines is temporarily stored in data latches called page buffers. On the other hand, a write or program operation is performed by sequentially storing data input through a data input / output pad or terminals in the page buffer and then temporarily programming the data stored in the page buffer into memory cells connected to one selected word line. Is done. Such a program operation is called a page program operation. The page reading operation and the page program operation are disclosed in Korean Patent Laid-Open No. 94-18870, which is assigned to the applicant and published on August 19, 1994.

The page programming method necessarily requires a means for sequentially writing data to be programmed prior to the program into each designated page buffer. That is, the above method requires pattern verification such as a short or open check between the bit line and the bit line and the check of the signal line on the page buffer, which may occur due to the miniaturization of the line width due to the large capacity of the memory chip. It takes time to load data sequentially into the buffer, which increases the test time, which is a problem during testing.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device which can reduce an increase in test time caused by sequentially loading data into a page buffer when a pattern is checked by a program.

Another object of the present invention is to provide a nonvolatile semiconductor memory device capable of reducing test time by generating various test patterns.

According to the technical idea of the present invention for achieving the above objects, a plurality of NAND cell units arranged in a row of columns and a plurality of floating gate type memory cells connected in series, and NAND cells arranged in the same column A plurality of bit lines connected to one end of the units, and the plurality of bit lines alternately extend with the bit line groups extending in the first column direction while extending in opposite first and second column directions, respectively. A first page buffer composed of a plurality of connected unit page buffers, a second page buffer composed of bit line groups extending in the second column direction and unit page buffers connected respectively, and the first and second It has control means to generate various data patterns by initializing voltage latch of data latch in page buffer at the same time or differently. And a teuksing.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

The NAND type flash memory cell array configuration and read / write operations of an electrically programmable and erasable nonvolatile semiconductor memory device are disclosed in detail in a nonvolatile semiconductor memory device filed December 22, 1993 in the United States.

1 is a schematic and schematic peripheral circuit diagram of a memory cell array for generating various test patterns in accordance with the present invention.

The memory cell array has 8,192 rows and 32 megabyte (4,096 × 8,192) bits of memory cells arranged in a matrix of 4,096 columns. The control gates of the memory cells arranged in the same rows are connected to 4,096 word lines, and the drains of the memory cells arranged in the same columns are connected to 8,192 bit lines.

A portion of the memory cell array is shown as a memory cell array connected to one row block B1 for convenience of illustration. Each NAND cell unit of the array of memory cells in the row block B1 includes 16 memory cells M0 to M15 connected in series between a source of the first select transistor ST1 and a drain of the second select transistor ST2. The drain of the first select transistor ST1 of each NAND cell unit is connected to the corresponding bit line through a resistance connection. The source of the second select transistor ST2 of each NAND cell unit is connected to a common source line CSL. The common source line CSLs connected to the NAND cell units are insulated from the bit lines and the word lines and connected to the common source line control circuit 12. Each row block B1 to B512 is composed of NAND cell units arranged in the same row. The control gates of the first selection transistors ST1, the control gates of the memory cells M1 to M16 and the control gates of the second selection transistors ST2 arranged in the same row in each row block B1 to B512 are the first selection line SSL. And word lines WL0 to WL15 and second selection lines GSL, respectively. The first selection lines SSL in the memory cell array are connected to a first row decoder 10 and the second selection lines GSL are connected to a second row decoder 11. In each row block, the odd-numbered word lines WLO, WL2, ..., WL14 and the even-numbered word lines WL1, WL3, ..., WL15 are the first row decoder 10 and the second row decoder, respectively. It is connected with (11). The structure and planar layout of the NANDSOL units constituting the memory cell array are disclosed in the above-mentioned Korean Patent Publication No. 94-18870, which is incorporated herein by reference.

2 is a diagram illustrating a connection relationship between bit lines and page buffers.

Referring to FIG. 2, the bit lines BL0 to BL4095 are alternately connected to the upper page buffer 13 and the lower page buffer 14. The upper and lower page buffers 13 and 14 are arranged to face each other with respect to almost parallel bit lines BL0 to BL4095. Therefore, even-numbered bit lines BL1, BL3, ...,-BL4095 forming the first group connected to the upper page buffer 13 are odd-numbered forming the second group connected to the lower page buffer 14. Are sandwiched by the bit lines BL0, BL2, ..., ... BL4094.

Referring back to FIG. 1, the upper and lower page buffers 13 and 14 are connected to corresponding data lines DLt0 to DLt7 and DLb0 to DLb7 through column decoders 15 and 16 connected to each other.

3 is a part of the bit line and upper and lower page buffers 13 and 14 as an embodiment of the present invention.

Only the lower page buffer 14 is shown among the upper and lower page buffers 13 and 14 connected to the bit line BL. First, referring to the configuration of the unit page buffer 43 in the lower page buffer 14, the lower page buffer 14 is a drain of the D-type transistor 33 to prevent high voltage transfer generated on the bit line BL The bit line control signal? BLSH is connected to the bit line BL and is applied to the gate of the transistor 33. The source of the transistor 33 is connected to the drain of the N-type transistor 34 for setting the precharge level on the bit line BL during a read operation, and the bit line precharge control is performed through the gate of the transistor 34. The signal BLSHF is applied. The source of the N-type transistor 34 has a function of sensing and latching data stored in the selected memory transistor, the N-type transistor 35 having a drain source passage connected between the nodes N1 and N2, and the node N1 and the ground voltage VSS. The drain source passages are connected in series between the transistor 31 having a drain source passage connected therebetween, and the interconnectors 44 and 45 cross-connected between the nodes N2 and N3 and the node N3 and the ground voltage VSS. N-type transistors 36 and 37 connected to each other, a n-type transistor 40 having a drain source passage connected between a gate of the n-type transistor 36 and a power supply voltage VCC, the node N2 and the lower column decoder ( 16 and a tristate inverter 39 connected in series between the tristate inverter 39 and the enMOS transistor 38 connected in parallel with the tristate inverter 39. Inverters 44 and 45 cross-connected between the nodes N2 and N3 provide a data latch circuit 30. The gate of the N-type transistor 31 is connected to the first initialization control signal DCB0, and the gate of the N-type transistor 35 is connected to the separation control signal SBL. The gate of the N-type transistor 35 serves to separate between the nodes N1 and N2 in response to the separation control signal SBL. The gate of the N-type transistor 37 is connected to the data latch control signal? Latch. The n-type transistors 31 and 35 serve to initialize the node N3 to the H level in response to the control signals DCB0 and SBL. The tristate inverter 39 outputs a sense amplifier output signal? SAC and its inverted signal upon completion of the data sensing operation during a read operation. Enabled by The NMOS transistor 38 is turned on by the data loading enable signal SPB during the program operation.

The unit page buffers 42 and 43 are alternately connected to bit lines, respectively, and the unit page buffer 42 is controlled by the first initialization control signal DCB0 in the unit page buffer 43. (31) Instead, it is replaced by the NMOS transistor 32 controlled by the second initialization control signal DCB1. The first and second initialization control signals DCB0 and DCB1 are controlled by third and fourth initialization control signals DCB2 and DCB3 in the upper page buffer 13, respectively. The unit page buffers 41, which consist of the unit page buffers 43 and 42, are continuously arranged to form the upper and lower page buffers 13 and 14. As shown in FIG. A detailed operation description of FIG. 3 will be described with the timing diagram shown in FIG. 4 to be described later.

4 is a diagram illustrating a timing relationship diagram of various control signals used in FIG. 3.

Referring to FIG. 4, a pattern generation process during programming is performed. The initialization operation of the upper and lower page buffers 13 and 14 between time t0 and t1, which is a page buffer initialization period, is performed using the bit line precharge control signal BLSHF, and the first operation. The sense amplifier enable signal when the first to fourth initialization control signals DCB0 to DCB3 are all at a low level. Transitions to a low level to precharge the node N1, enables the NMOS transistor 36 by a high level voltage applied to the node N1, and then shifts the data latch control signal? Latch to a high level. The data latch 30 is initialized by enabling the NMOS transistor 37 to set the node N3 to the low level. Subsequently, the pattern generation operation is performed between the time t1 and t2 which are data pattern generation periods. When the initialization control signals DCB0 to DCB3 transition from the low level to the high level, the node N1 goes low and the data is set while the node N3 goes high. That is, all or part of the initialization control signals DCB0 to DCB3 may be transitioned to a high level to generate a desired data pattern.

Therefore, since the data pattern is generated using the initialization control signals DCB0 to DCB3, the section for the conventional data loading is unnecessary, thereby reducing the test time during the program pattern test.

As described above, the present invention has an effect of reducing an increase in test time caused by sequentially loading data into a page buffer when checking a pattern by a program. In addition, the present invention has the effect of reducing the test time by generating a variety of test patterns.

Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (3)

A plurality of NAND cell units arranged in a row and column matrix and having a plurality of floating gate type memory cells connected in series; a plurality of bit lines connected to one end of the NAND cell units arranged in the same column; The first bit buffer is composed of a plurality of unit page buffers each connected to the bit line groups extending in the first column direction while alternately extending in opposite first and second column directions. A nonvolatile semiconductor memory device having a second page buffer configured with bit line groups extending in the second column direction and unit page buffers connected to each other, wherein voltage levels of data latches in the first and second page buffers are simultaneously controlled. Characterized in that it has a control means capable of initializing or initializing differently to generate various data patterns. Nonvolatile Semiconductor Memory Device. The method of claim 1, wherein the control means applies different control signals to the gates of the transistors for determining the initialization level in the plurality of unit page buffers adjacent to adjust the voltage level of the data latch. Nonvolatile Semiconductor Memory Device. The nonvolatile semiconductor memory device of claim 2, wherein the transistor is an enMOS transistor.