KR0172367B1 - Semiconductor memory redundancy circuit - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

Redundancy circuit in semiconductor memory.

2. The technical problem the invention is trying to solve:

The present invention provides a redundancy circuit that improves a fail recovery rate in a semiconductor memory employing a redundancy memory cell.

3. Summary of the Solution of the Invention:

A semiconductor memory device including a memory cell array having a plurality of rows and columns of a matrix-type normal memory and a plurality of columns of redundancy column memory cells, is a master column control to which redundancy column memory cells in the memory cell array are applied. A redundancy column decoder for selecting in response to the signal; A fail row that outputs a fail low signal as a first level when a row address of a defective normal memory cell in a single bit form is applied and outputs a fail low signal as a second level when a row address of a defect-free normal memory cell is applied. Detecting means; Redundancy column pre-decoding means for outputting a fail column signal as the first level when the defective address of the defective normal memory cell is applied and outputting the fail column signal as the second level when the column address of the defective normal memory cell is applied; ; The master column control signal is generated when the fuse has an internal cutoff and all or one of the signal level of the fail low detecting means and the column pre decoding means is the first level, and generates the master column control signal to the redundancy column decoder. And providing the control means to select the redundancy column memory cells.

4. Important uses of the invention:

It is used in semiconductor memories employing redundancy memory cells.

Description

Redundancy Circuit of Semiconductor Memory with Improved Fail Recovery

1 is a configuration diagram of an entire redundancy circuit of a semiconductor memory to which the present invention is applied.

2 is a specific circuit diagram of a conventional general redundancy circuit,

3 and 4 are schematic diagrams of the column redundancy circuit according to the present invention, and

5 and 6 are configuration diagrams of a low redundancy circuit according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a redundancy circuit of a semiconductor memory capable of improving a fail recovery rate.

In general, as semiconductor memory devices are increasingly integrated and miniaturized, productivity is emphasized. In particular, memory cells are the most vulnerable part of the production, and thus the yield decrease is a big problem. Various methods have been proposed to solve this problem, but the most common method is to replace defective cells with redundant cells to improve the yield of production. In the case of such a repair scheme, a fail cell is usually replaced by a row or a column. This will be described with reference to FIGS. 1 and 2.

1 shows the structure of a column redundancy circuit that is generally used. In the memory cell array 100 arranged in rows and columns corresponding to eight input / output blocks, normal column cells and redundancy column cells are included. In FIG. 1, the number of columns per I / O block is 16 normal columns and 1 redundancy column. The memory cell array 100 is connected to the normal column decoder 200 and the redundancy column decoder 201 corresponding to the number of input / output blocks, respectively, and the normal column decoder 200 and the redundancy kalim decoder 201 are the normal column predecoder 300 and the redundancy column, respectively. Respectively connected to the predecoder 600. The address buffer 500 is commonly connected to the normal column free decoder 300 and the redundancy column free decoder 600. The eight input / output circuits 400 are respectively connected to the eight blocks in the memory cell array 100 through data buses.

In the configuration of FIG. 1 described above, a process of replacing the redundancy column corresponding to the defect of the normal memory cell 102 in the memory cell array 100 is as follows. When a column address designating a defective cell in the normal memory cell 102 is input to the address buffer 500, the redundancy column predecoder 600 uses the fuses F1, F11,... As shown in FIG. , The signals R-EN and N-DIS for disabling the defective normal cell column and enabling the corresponding redundancy cell column by the pre-cutting program of F4 and F44, respectively. The cutting of the fuse is performed by irradiating a fuse with a laser beam in the wafer state of the memory. The normal disable signal N-DIS is applied to the normal column decoder 200 through the normal column free decoder 300, and the decoder 200 disables the normal column in response. As a result, the defective normal cell row is placed in an inoperable state when the memory is read or written.

Meanwhile, the redundancy enable signal R-EN is applied to the redundancy column decoder 201 through the redundancy column predecoder 600. As a result, the columns of the redundancy cells are enabled so that the defective normal cell rows are replaced with the extra rows of redundant cells.

FIG. 2 shows a conventional concrete circuit diagram of the components of FIG. 1.

FIG. 2A shows a configuration example of the first buffer address buffer 500 and FIG. 2B shows a configuration example of the redundancy column predecoder 600 and the redundancy column decoder 201 in the first diagram. 2c shows a configuration example of a normal column free decoder 300 and 2d shows a configuration example of a normal column decoder 200.

On the other hand, the operation of replacing the defect of the memory cells in the row direction with the redundancy low cells is performed in units of rows as in the column redundancy operation.

As described above, conventionally, defective memory cells are collectively replaced by row or block units regardless of a defect type such as a column and a row direction fail or a single bit fail. Therefore, the redundancy rescue method has a disadvantage in that the fail rescue rate is lowered and the chip size is relatively large because the cells in the redundancy block must be sufficiently secured. That is, since a corresponding redundancy block in a row or column unit is used to repair a single bit defective cell, if one of the redundant memory cells in the redundancy block has a defect, the replacement probability is lowered. will be. In addition, replacing single-bit defective cells by block of rows or columns increases the area of the entire memory cell array, resulting in increased cost.

Accordingly, an object of the present invention is to provide a redundancy circuit of a semiconductor memory capable of improving the fail recovery rate.

Another object of the present invention is to provide a redundancy circuit which can reduce a memory chip size in a semiconductor memory employing a redundant memory cell.

It is still another object of the present invention to provide a redundancy circuit that can be replaced with some cells of a redundancy memory cell block arranged in units of bits or bits or rows when a plurality of single bit failures occur in a semiconductor memory.

According to the present invention for achieving the above object, a column redundancy circuit of a semiconductor memory device comprising a memory cell array having a plurality of columns and a redundancy column memory cells arranged in a matrix form of a plurality of rows and columns A redundancy column decoder for selecting redundancy column memory cells in the memory cell array in response to an applied master column control signal; A fail row that outputs a fail low signal as a first level when a row address of a defective normal memory cell in a single bit form is applied and outputs a fail low signal as a second level when a row address of a defect-free normal memory cell is applied. Detecting means; Redundancy column pre-decoding means for outputting a fail column signal as the first level when the column address of the defective normal memory cell is applied and outputting the fail column signal as the second level when the column address of the defective normal memory cell is applied; ; The master column control signal is generated in the redundancy column decoder when all or one of the signal levels of the fail low detecting means and the column pre decoding means are at the first level. And providing the control means to select the redundancy column memory cells. Here, the fail row detecting means and the redundancy column pre decoding means may exist in the column redundancy circuit to remedy at least two or more single bit fail, in this case the control means is the fail row detecting means. And a master control unit configured to logically combine the column control signals applied from the column control unit with a column control unit for outputting a plurality of column control signals by combining the signal levels of the redundancy column pre-decoding means, respectively. It is divided into control parts. The fail low detecting means outputs the fail low signal as the logic high as the first level when the row address of the defective normal memory cell in the form of the single bit is applied by cutting the fuse provided therein. . The redundancy column pre decoding means also cuts the fuse provided therein, thereby outputting the fail column signal as a logic high when the column address of the defective normal memory cell is applied. Preferably, the control means includes a NOR gate internally to generate the master column control signal when the signal levels of the fail low detecting means and the column pre decoding means are all or one of the first levels. Do.

On the other hand, a low redundancy circuit of a semiconductor memory device including a memory cell array having a plurality of rows and columns of a normal memory arranged in a matrix form and a plurality of rows of redundant row memory cells is a redundancy row memory in the memory cell array. A redundancy row decoder for selecting cells in response to an applied master row control signal; Fail to output the fail column signal as the first level when the column address of a defective normal memory cell in a single bit form is applied and output the fail column signal as the second level when the column address of a defect-free normal memory cell is applied Column detecting means; Redundancy row free decoding means for outputting a fail low signal as a first level when the row address of a defective normal memory cell is applied and outputting a fail low signal as a second level when the row address of a defective normal memory cell is applied; ; The master row control signal is generated in the redundant row decoder when both or one of the signal levels of the fail column detecting means and the row free decoding means is the first level. And controlling the redundancy row memory cells to be selected.

According to the technical idea of the present invention described above, when a plurality of single bit fail occurs, it may be replaced by some cells of a redundancy memory cell block arranged in bit-by-bit or row or column units.

Hereinafter, with reference to the accompanying drawings for a thorough understanding of the present invention will be described in detail the configuration and operation of the present invention.

The configuration of the embodiment according to the present invention is largely composed of a third diagram representing a column redundancy circuit and a fifth diagram representing a low redundancy circuit. In FIGS. 4 and 6, specific circuits of FIGS. Is shown in this context. In FIG. 3, for convenience of understanding, the same or similar parts as those shown in FIG. 1 are provided as the same reference numerals. FIG. 5 may be located around the memory cell array 100 in relation to FIG. As can be seen, the memory block configuration of FIG. 1 is applied to the present invention as it is, and the detailed circuit of the block is substantially implemented as 3, 4, 5, and 6 degrees unlike the conventional second embodiment.

Referring to FIG. 3, the column redundancy circuit includes a redundancy column decoder 201 for selecting redundancy column memory cells in the memory cell array in response to a master column control signal applied from an output terminal A, a fail row detector 601, and a redundancy column predecessor. The decoder 602, the column control unit 610, and the master column control unit 620. The fail row detector 601 outputs a fail low signal as a first level, for example, a logic high when a low address of a defective normal memory cell is applied in a single bit form and fails when a row address of a defective normal memory cell is applied. Output the low signal as a logic low. The redundancy column predecoder 602 outputs a fail column signal as a first level, for example, a logic high when the column address of the defective normal memory cell is applied, and outputs a fail column signal when the column address of the defective normal memory cell is applied. Output as logic low. A detailed circuit of the fail row detector 601 and the redundancy column free decoder 602 is shown in FIG. 4, the configuration of which is the same as the fuse and the plurality of transistors as in the configuration of FIG. The column controller 610 and the master column controller 620 included in the control means have a cuttable fuse therein, and when all or one of the signal levels of the fail low detecting means and the column pre decoding means are the first level. The master column control signal is outputted to the output terminal A, and provided to the redundancy column decoder 201. Accordingly, the redundancy column decoder 201 causes the redundancy column memory cells to be selected. In addition, the master calim control signal is also applied to the normal column predecoder 300 to disable the normal cell when the redundancy column memory cells are selected.

A detailed operation of replacing column redundancy will be described with reference to FIGS. 3 and 4. When one address is input to the row address buffers 501 and 502 of FIG. 4, the buffered addresses A1-Ai are output to the output terminal thereof. The buffered address is sequentially applied to the input terminals of the fail row detector 601. The fail low detector 601 is a single-bit type of fuses F1, F11,... In FIG. 4 so that a fail low signal can be output as a logic high when a low address of a defective normal memory cell is applied. , F4, F44 are selected and already cut. Thus, a logic high is provided to the input of the inverter 615 of the column controller 610. In addition, the redundancy column predecoder 602 can output the fail column signal as logic high when the column address of the defective normal memory cell is applied. , F4, F44 are selected and already cut. Thus, a logic high is provided to the input of the inverter 619 of the column control 610. Therefore, the column controller 610 outputs a logic high in the above case by providing a noah gate 618. The high signal is applied to the master column controller 620. The master column controller 620 outputs a low when at least one of the three inputs is high, which is eventually output as a logic high by the inverter 622. This logic high signal becomes the master column control signal and is provided to the redundancy column decoder 201. Accordingly, the decoder 201 enables the column redundancy memory block to be replaced instead of the normal cell. In this case, the normal column free decoder 300 which receives the master column control signal is disabled so that the normal memory cell is unselected. Thus, a single bite fail is specified. In the present exemplary embodiment, three fail-row detectors 601 and three redundancy column predecoders 602 each having a fuse element therein are provided to remedy three single bit fail. On the other hand, when the column address or row address is an address specifying a cell that is not a fail, the master column control signal is output at a low level. In this case, the redundancy column memory block is disabled as opposed to the above description, and the normal cell is enabled. In this case, when a single bit fail is replaced by a part of the column redundancy without replacing the fail cell with bits to bits, the buffering address applied to the fail row detector 601 is removed. For example, when only the MSB of the row address is applied, half of the column redundancy memory cells are correspondingly replaced.

Therefore, according to the above configuration, since all of the single bite failure or the columnar failure can be saved, there is an effect of improving the fail recovery rate.

Similar to the above description, a low redundancy circuit is shown in FIGS. 5 and 6. The low redundancy circuit includes a redundancy row decoder 211 for selecting redundancy row memory cells in the memory cell array in response to a master row control signal applied from an output terminal B, a fail column detector 801, a redundancy row free decoder 802, a row control unit 810, And a master row controller 820. The fail column detector 801 outputs a fail column signal as a first level, for example, a logic high when a column address of a defective normal memory cell in a single bit form is applied, and fails when a column address of a defective normal memory cell is applied. Output the column signal as logic low. The redundancy low free decoder 602 outputs a fail low signal as a first level, for example, a logic high when a low address of a defective normal memory cell is applied, and a fail low signal when a row address of a defective normal memory cell is applied. Output as logic low. A detailed circuit of the fail column detector 801 and the redundancy low free decoder 802 is shown in FIG. 6, the configuration of which is the same as the fuse and the plurality of transistors as in the configuration of FIG. The row control unit 810 and the master row control unit 820 included in the control unit have a cuttable fuse therein, and all or one of the signal levels of the fail column detecting unit and the redundancy row free decoding unit may be the first level. In this case, the master row control signal is output to the output terminal B and provided to the redundancy row decoder 211. Accordingly, the redundancy row decoder 211 causes the redundancy row memory cells to be selected. In addition, the master row control signal is also applied to the normal low predecoder 310, in order to disable the normal cell when redundancy row memory cells are selected.

The operations of FIGS. 5 and 6 described above are the same as those of FIGS. 3 and 4 described above, except that the alternate direction of the redundant cells is performed in the row direction.

According to the present invention as described above, in the semiconductor memory employing the redundancy memory cell has the effect of improving the fail recovery rate, there is an advantage that can reduce the memory chip size.

Claims (10)

A semiconductor memory device comprising: a memory cell array having a normal memory arranged in a matrix form of a plurality of rows and columns and a redundancy column memory cells arranged in a plurality of columns; A redundancy column decoder for selecting redundancy column memory cells in the memory cell array in response to an applied master column control signal; A fail row that outputs a fail low signal as a first level when a row address of a defective normal memory cell in a single bit form is applied and outputs a fail low signal as a second level when a row address of a defect-free normal memory cell is applied. Detecting means; Redundancy column pre-decoding means for outputting a fail column signal as the first level when the column address of the defective normal memory cell is applied and outputting the fail column signal as the second level when the column address of the defective normal memory cell is applied; ; The master column control signal is generated in the redundancy column decoder when all or one of the signal levels of the fail low detecting means and the column pre decoding means are at the first level. And redundancy column memory cells selected by providing control means. 2. The method of claim 1, wherein the plurality of fail row detecting means and redundancy column pre decoding means exist in the column redundancy circuit to remedy at least two or more single bit failures. A master for generating the master column control signal by logically combining the column control signals applied from the column control unit with a column control unit for combining the signal levels of the means and the redundancy column pre-decoding unit, respectively; A column redundancy circuit of a semiconductor memory device, characterized in that the column control unit. The method of claim 1, wherein the fail-row detecting means cuts the fuse provided therein to output the fail-low signal as logic high when the defective normal memory cell and the row address are applied in the single-bit form. And a column redundancy circuit of the semiconductor memory device. 2. The redundancy column pre-decoding means according to claim 1, wherein the redundancy column pre-decoding means outputs the fail column signal as logic high when the trim address of the defective normal memory cell is applied by cutting a fuse provided therein. A column redundancy circuit of a semiconductor memory device. The method of claim 1, wherein the control means is configured to generate a noah gate to generate the master column control signal when the signal levels of the fail low detecting means and the column pre decoding means are all or one of the first level. A column redundancy circuit of a semiconductor memory device, characterized in that provided internally. A semiconductor memory device comprising: a memory cell array having a plurality of rows of normal memory arranged in a matrix form of rows and columns and redundancy row memory cells arranged in a plurality of rows; A redundancy row decoder for selecting redundancy row memory cells in the memory cell array in response to an applied master row control signal; Fail to output the fail column signal as the first level when the column address of a defective normal memory cell in a single bit form is applied and output the fail column signal as the second level when the column address of a defect-free normal memory cell is applied Column detecting means; Redundancy row free decoding means for outputting a fail low signal as a first level when the row address of a defective normal memory cell is applied and outputting a fail low signal as a second level when the row address of a defective normal memory cell is applied; ; The master row control signal is generated in the redundant row decoder when both or one of the signal levels of the fail column detecting means and the row free decoding means is the first level. And providing redundancy row memory cells so as to provide a control means for providing the redundancy circuit. 10. The fail column detecting apparatus of claim 6, wherein the failing column detecting means and the redundancy row free decoding means are present in the low redundancy circuit to remedy at least two or more single bit failures. A master for generating the master row control signal by logically combining a row control signal outputting a plurality of row control signals by combining the signal levels of the means and the redundancy row free decoding means with each other; A low redundancy circuit of a semiconductor memory device, characterized in that the row control unit. The method of claim 6, wherein the fail column detecting means cuts the fuse provided therein, thereby outputting the fail column signal as logic high when the column address of the defective normal memory cell in the form of the single bit is applied. And a low redundancy circuit of the semiconductor memory device. 7. The method of claim 6, wherein the redundancy row free decoding means cuts the fuse provided therein to output the fail low signal as a logic high when the row address of the defective normal memory cell is applied. Low redundancy circuit of a semiconductor memory device. 7. The method of claim 6, wherein the control means or the node for generating the master low control signal when the signal level of the fail column detecting means and the row free decoding means is all or one of the first level. A low redundancy circuit of a semiconductor memory device, characterized in that provided internally.