KR0171015B1 - Fault Tolerant Traffic Distributed Control Node Device for High Performance IPC Networks - Google Patents

Abstract

The present invention relates to a fault tolerant traffic distributed control node device for providing a communication path between a frame source and a destination in a high performance IPC network. A traffic distribution control node device for distributing traffic for multiple U-links to the same network through a link switch controller, an input switching matrix device for grouping U-links for the same destination network, and an output link among links in each same group A round robin link arbitration apparatus for determining a network, an output switching matrix apparatus for reconfiguring U-links for each group in an input order, a link group management apparatus for managing U-link group information, and a grouping of U-links for the same destination network To control and arbitrate link paths within a group Since the present invention includes a switch switching control device, the present invention eliminates a bit area for link division from a destination address area of a frame in a multi-link system configuration between the same networks considering a real-time data service configured in a CDMA system network. As a result, the node capacity of the network is increased, and even traffic distribution between multiple links is possible regardless of the destination address of the frame, maximizing the overall data rate, and in case of a specific link failure, the hardware circuit alone isolates the link. The fault-tolerant function can be implemented by distributing traffic over other normal links.

Description

Fault Tolerant Traffic Distributed Control Node Device in High Performance IPC Networks

1 is a structural diagram of a control station and a base station network of a CDMA system to which the present invention is applied.

2 is a structural diagram of a fault tolerant traffic distribution control node device according to the present invention;

3 is a detailed structural diagram of a link switching controller according to the present invention.

4 illustrates an embodiment of a link switching controller operation in accordance with the present invention.

The present invention relates to a fault tolerant traffic distributed control node device of a high performance IPC network, and more particularly to a fault tolerant traffic distributed control node device for providing a communication path between a frame source and a destination in a high performance IPC network.

In other words, the present invention relates to a node module of a high performance interprocessor communication network in a code division multiple access (CDMA) mobile communication system network structure (see also FIG. 1 of patent application No. 141348). Although the traffic imbalance on multiple links between the same networks may occur due to the application of No. 138872), and if one link fails, the packet is not routed due to hardware self-routing despite the presence of another redundant link. The present invention relates to a node device capable of resolving a failing state.

The conventional node structure has a structure of simply transmitting a frame reception permission signal output from the frame address checker to the node buffer control unit without the link switching control unit of the present invention. Thus, traffic load balancing for multiple links for a frame destined for the same destination is performed by dividing only the corresponding link address assigned to the address area of the frame. Therefore, when a link failure occurs during operation, a problem occurs that the frame transmission with the address of the link is stopped.

The conventional node module has a node buffer controller representing a plurality of nodes in one mode module, and the node buffer controller is connected to other networks through respective link matching units and U-links. And two different network connections are configured by linking one node pair from each network. However, if the transceiving traffic between the inter-networks exceeds the single link rate, a multi-link configuration is required, and thus multiple node pairs are allocated for the same inter-network connection. In this case, the number of node pairs is equal to the number of links that can accommodate the maximum transceiving traffic between networks.

In such a network configuration, there can be two methods to perform hardware self-routing in the output buffered node module.

First, by assigning a unique address to each node constituting each node pair and specifying this address in the packet header, even if there are multiple nodes connecting the same network, only one node is allowed to receive the packet and thus the destination. Packet multiplication to the network does not occur. However, this method must be preceded by further expansion of the destination address field constituting the packet header. The reason is that in hardware self-routing method, the address fields referred to by nodes of each network should be different according to the network hierarchy. In this case, the address bit field can distinguish the pair of nodes connecting the same mutual network. This is because the number of bits required = the number of log ₂ node pairs.

In addition, in order to maximize the efficiency of the system network, that is, the transmission rate, this method needs to know in advance the traffic conditions of the node pairs of the multi-link group to be used by all terminals which wish to transmit packets through the multi-link. The reason is that the destination address should already be assigned at the time of generating the packet in the terminal. In this case, the node address of the node pair to be used is also allocated. In this case, each node on the system network generates the address independently of each other. This is because even if there is no traffic in other node pairs forming a group, congestion such as packet buffer overflow may occur in the node pair that has been previously assigned an address. Second, the node apparatus described in the present invention is applied as a method of managing a node pair in a node module without assigning a separate additional address to a node constituting each node pair.

Functional features of the node device are as follows.

First, no additional unique address assignment is required for each node in each node pair that constitutes a multilink group. That is, each node forming the multilink group has the same address, and thus, when generating a packet in the terminal, it is not necessary to separately specify a node pair of a link to transmit the packet. Second, when a link failure occurs, the packet is routed to another link of the same link group so that it has a fault tolerant function.

An object of the present invention for solving the above problems is to implement a high-speed traffic transmission function by implementing only the hardware circuits in each node according to the CDMA characteristics of the multi-link traffic distribution between the base station and the control station to enable high-speed frame transmission and normal operation when a specific link failure occurs It is to provide a fault tolerant traffic distributed control node device of a high-performance IPC network to bypass the traffic to other links of the same group to support the fault tolerant function.

A feature of the present invention for achieving the above object is a traffic distribution control node device for a fault-tolerant traffic distribution control node of a high performance IPC network, comprising: a traffic distribution control node device for distributing traffic for multiple U-links to the same network through a link switching controller; An input switching matrix device for grouping U-links destined for the same destination network, a round robin link arbitration device for determining an output link among the links in the same group, and an output switching for reconfiguring the U-links per group in order of input links It includes a matrix device, a link group management device for managing U-link group information, and a link switching control device for controlling grouping of U-links directed to the same destination network and arbitrating link paths in the group.

According to the present invention, it is possible to implement efficient availability for maximum data rate and limited memory resources in each node with uniform traffic distribution between links under a multi-link configuration between a control station and a base station network of a CDMA system. Fault Tolerant Traffic Distributed Control Node of High Performance IPC Networks

1 is a structural diagram of a control station and a base station network of a CDMA system to which the present invention is applied.

Referring to FIG. 1, a control station and a base station network structure of a CDMA system to which the present invention is applied will be described.

Local CDMA Interconnection Network (LCIN) 110, which is a control station 100 network, can accommodate up to 16 base station 160 networks 170. Each network consists of a unit node 120, a D-bus, which is a system backplane bus connecting each unit node, an M-bus, which is a maintenance channel of the nodes, and a U-link 130. The relay line 150 is connected to the relay device 140 for matching. The control station and each base station are connected by multiple U-links and are configured to overcome the limitations of each U-link having a transmission rate of up to 10 Mbps, which is relatively smaller than the maximum switching speed of 320 Mbps, which is the frame switching rate on the D-bus. In other words, in order to support the maximum traffic rate between the control station and a specific base station, not only the frame switching rate within the unit network but also the sufficient frame rate between the networks must be supported. Among these requirements, the rate between the networks reaches the limit first. A method for increasing the overall data rate over multiple links is applied. The node 120 is divided into a processor node and a bridge node according to the connected end device by nature, and outputs the frame data received from the U-link to another node by transmitting it to another node, and the frame received from the D-bus. It outputs data to U-link connected to the node and transmits it to the processor or bridge node of other network.

2 is a structural diagram of a fault tolerant traffic distribution control node device according to the present invention.

Referring to FIG. 2, the fault tolerance traffic distribution control node device structure according to the present invention will be described.

It consists of nine kinds of functional blocks.

The U-link 201 is a cable connecting a processor or a bridge node of another network according to the RS422 standard. The link matching unit 202 performs a function of matching the U-link with the node buffer controller 204 and transmits and receives frame data, a data clock, and an alarm signal with the node buffer controller through the signal line 203. The node buffer controller 204 temporarily links frame data destined for the U-link received from the link switching controller 250 via the signal line 206 to the internal memory and transmits the data in synchronization with the U-link clock. The frame received from the memory is temporarily stored in the internal memory and then transmitted to the bus controller 208 through the signal line 205. The bus controller 208 performs the D-bus license control, which is a shared bus, on behalf of a plurality of node buffer controllers housed in one hardware module, and transmits frame data from the node buffer controller through the signal line 210. Performs the function of transmitting to the D-bus matching unit. The D-bus matching unit 211 transmits and receives frame data, a data clock, and an alarm signal between the nodes through the tripled D-bus signal line 212. The frame address checker 214 temporarily stores the destination address area of 8-bit or 16-bit parallel frame data received from the D-bus matching unit 211 via the parallel signal line 213 and performs HDLC communication from an address area of up to 3 bytes. Remove the forced 0 bits according to the method. Thereafter, the address is checked to finally determine whether the frame is received, and the result is transmitted to the link switching controller 250 through the signal line 215. Path control characteristic information of each node is provided to the node controller 217 through the signal line 216 and has a function of being utilized in path control. The node controller 217 is a function module that performs various maintenance functions. The node controller 217 analyzes the collected fault information reported through the fault information signal line 219 to perform a node self test, and if necessary, matches the M-bus with the signal line 221. Report to the operator through the unit (222). The node's own address and path control attribute register in the frame address checker is initialized through the signal line 216 when necessary during system startup and operation. In addition, it has a function of managing the state and group information of the U-link connected to each node buffer controller and reports the result to the link switching controller 250 through the signal line 218 when the state and information change. The link switching controller 250 determines the group of each output U-link by using the U-link group information reported from the node controller, sets the physical path through the internal switching matrix device, and sets the frame path from the frame address. When a path control result signal is inputted, the output link is arbitrated for each output signal preference corresponding to each U-link in the same group to allocate uniform traffic to each node buffer controller in the same group. In addition, when the information on the failed U-link is reported from the node controller, the frame is not transmitted to the failed U-link by excluding the failed link during link arbitration within the link group to which the corresponding U-link belongs. It also has a function to allow flexible frame transmission management by participating in the link arbitration during recovery.

The node device of the present invention has a structure in which a link switching controller 250 is added to a conventional node module (Patent No. 138872) structure as shown in FIG.

The operation function and features of this link switching controller 250 are as follows.

First, since the node pairs forming the same link group all have the same node address, the frame reception permission signal from the frame address checker allocated to each node is also generated. In this case, the link switching controller controls the frame reception allowance signal to be transmitted to only one link node pair, which occurs simultaneously for multiple node pairs of the same link group, so that the packet frame is not duplicated.

Second, since the number of node pairs forming one link group is controlled by the control of the link group management unit 309, the network configuration can be maximized according to the maximum traffic volume between networks.

3 is a detailed structural diagram of a link switching controller according to the present invention.

The detailed structure of the link switching controller according to the present invention will be described with reference to FIG.

It is largely composed of four types of functional blocks.

The frame path control result signal for each node buffer controller input through the signal line 301 is separated for each output U-link group designated at the time of system configuration in the input switching matrix device 302, and is separated through the corresponding group signal line 303. Is sent to the link arbiter. In this process, the corresponding input / output port of the switching matrix is determined by the group information signal input from the link group manager 309 through the signal line 310. The round robin link arbiter 304 is generated for each link group, and determines the output port in a round robin manner only for a link whose state of the output U-link corresponding to the input link is normal. In this process, the link state information input from the link group manager 309 via the signal line 311 is applied.

In the CDMA system network to which the present invention is applied, the frame path control results for the U-link or node buffer controllers assigned to the same group are the same, and the path control result signals input to the specific group from the input switching matrix device are also the same. Accordingly, the round robin method uses a method of sequentially moving in units of input ports and corresponding output ports. The link arbitration result is output to the output switching matrix device 306 via the group signal line 305. The output switching matrix device 306 operates in reverse to that of the input switching matrix device 302 and has a function of reconfiguring the output link in the order of the first input link of the link switching controller to output the frame to the signal line 307. In this process, link group information input from the link group manager 309 via the signal line 312 is used. The link group manager 309 has a register table that designates a group of each link, and has a function of managing group information for each link and the total number of groups.

4 is a diagram illustrating an embodiment of a link switching controller according to the present invention.

An operation of the link switching controller according to the present invention will be described with reference to FIG.

This shows a process of switching eight input signal lines 401.

The group information input from the node controller via the signal line 408 is stored in the link group manager 409 and input to each switching matrix 402, 406 through the signal lines 410, 412 to form a path in the link switching matrix. .

In this embodiment, link group-1 is linked to links 1, 2, 3, and 6, and group 2 is 4, 5, 7, 8, and not necessarily in a sequential order for physical or shape configuration when constructing a CDMA system. The case where it consists of a link is shown. In order to group each link, the input switching matrix device 402 sets up an input / output path as shown in FIG. 4, and the round robin link arbiter 404 binds the output link to the input links through the group signal line 403. FIG. The path is set in turn every frame input. In this process, the internal path corresponding to the U-link that is found to be a failure is excluded from the link arbitration process. Also, at any one time, only one path is established and the output end of the unconnected path exhibits a high impedance state and the arbitration result signal is transmitted to the output switching matrix device 406 through the group signal line 405. The output switching matrix device 406 performs a function of returning the group link order configured in the input switching matrix device to an initial state, and as a result, transmits signals to each node buffer controller through the signal line 407. Therefore, in the present invention as described above, in the multi-link system configuration between the same networks considering the real-time data service currently configured in the CDMA system network, the bit region for link division is lost from the destination address region of the frame. Increased capacity and uniform distribution of traffic between multiple links regardless of the destination address of the frame maximizes the overall data rate.In the event of a link failure, the hardware circuit alone isolates the link and returns it to the other The effect is that fault tolerance can be implemented by distributing traffic.

Claims (6)

A fault tolerance traffic distribution control node device of a high performance IPC network, comprising: a link switching controller for performing traffic distribution control; A fault tolerant traffic distribution control node device for a high performance IPC network, comprising: a node controller for isolating a failed link and reassigning traffic in the link group. 2. The apparatus of claim 1, wherein the link switching controller comprises: an input switching matrix device configured to form a link group node pair in which the same routing is performed according to a link group shape information register value of the controller; A round robin link arbitration apparatus for determining an output link among links in each same group; An output switching matrix device for reconfiguring group-specific U-links in order of input links; A failure tolerance traffic distribution control node device of a high performance IPC network, comprising: a link group management device managing U-link group information. 3. The fault tolerant traffic distribution control node of claim 2, wherein the input switching matrix device configures a link group node pair in which the same routing is performed according to the link group shape information register value of the node controller. Device. 3. The apparatus of claim 2, wherein the round robin link arbitration apparatus selects one of the same packet frame reception permission signals for each node pair of the link group output from the input switching matrix apparatus, and selects and outputs the output link in a series of orders. Fault-tolerant traffic distribution control node device for a high performance IPC network. The fault tolerance type of the high performance IPC network according to claim 2, wherein the output switching matrix device reconfigures a pair of link group nodes for which the same routing is performed for each physical output link according to a link group shape information register value of a node controller. Traffic distribution control node device. The apparatus of claim 2, wherein the link group management apparatus manages link group shape information by generating a signal to monitor individual link states in a link group and to isolate them in a round robin link arbitration process in a group when a failure occurs. Fault Tolerant Traffic Distributed Control Node Device in High Performance IPC Networks.