KR0169965B1 - Monolithic integrated circuit with auxiliary LDMOS power transistor CMOS and vertical PNP integrated structure - Google Patents

Abstract

None.

Description

Monolithic integrated circuit with auxiliary LDMOS power transistor, CMOS and vertical PNP integrated structure

1 is a partial cross-sectional view of an integrated circuit made in accordance with the present invention.

FIG. 2 shows the electric field in the overmapping region between the n-channel LDMOS transistor gate and the drain region of the prior art generated by computer simulation without the additional n-doped region of the present invention.

3 shows electric field lines in the same overlapping region of previous FIG. 2 generated by computer simulation for a transistor provided with an additional n-doped region in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2: n-type silicon layer

3: n ⁺ layer 4: p type low isolation layer

5: field oxide layer 6: p-well region

7: p-doped region 8: n-type region

9: p ⁺ drain-source junction 10: n ⁺ source-drain junction

The present invention relates to a complex technology, smart power integrated device comprising a power transistor and control logic and an analog drive circuit combined into a complete integrated silicon chip.

The commercial success of so-called smart powers, in which analog signal processing circuits, control logic circuits and output power devices are conveniently integrated into one single chip as a complete unit, has been associated with different integrated devices that need to be operated under different supply voltages. It was to overcome the problem of compatibility among different manufacturing processes. In most cases, the power section of such an integrated circuit requires a VDMOS transistor that requires a constant drive gate voltage level between about 10v-20v.

This makes it difficult to connect a power transistor (e.g., VDMOS) with the driving circuit. Typically, the maximum operating voltage of a CMOS transistor used in a logic circuit is 5V. Conversely, the driving circuit for the power transistor is operated at about 12V, and the CMOS transistor supply voltage of the associated driving circuit must be at least 15V to ensure the drive level at the 10V VDMOS power transistor gate, and if the appropriate processing spread is assured. do. Better operating conditions of the VDMOS power transistor (ie, lower resistance R _On ) can be achieved if the driving voltage at the gate can be raised to 15-20V as is well known in the art.

In smart power type integrated circuits, this particular problem is usually eliminated by using a level shift which makes the driving circuit more complicated.

In order to directly drive an output power transistor at a relatively high voltage without using a special level shift circuit, a CMOS transistor having an operating voltage of about 20 V needs to be used in a fully integrated semiconductor device of a smart power type.

On the other hand, there are other CMOS and bipolar transistors used in these integrated circuits because of their inherent characteristics in control logic circuits and in signal processing circuits, respectively. The availability and dependence of their other integrated devices may allow their other integrated devices to tolerate supply voltages higher than normally allowed by the physical structure of these integrated devices also generated through a mixed-technology manufacturing process. Can be improved.

In view of this level of technology, smart power type devices, CMOS structures, and insulated collectors that are integrated in a monolithic fashion (monolithically) are typically tolerated by these devices as they are formed together as a complete monolith in a single chip. Its main purpose is to provide a vertical, PNP transistor capable of withstanding operating voltages higher than the voltage.

This object is achieved by the integrated device of the invention as defined in the appended claims.

Structurally, such a device is diffused from the surface of a n-type epitaxial layer doped with phosphors, in which different devices are formed through the drain region of the n-channel LDMOS transistor extending between the gate electrode and the adjacent insulating oxide. It includes an n-type silicon region with a similar diffusion end surface, the body of the p-channel LDMOS transistor extends between its gate electrode and adjacent dielectric oxide, and the drain region of the n-channel MOS transistor is adjacent to the gate electrode. An n ⁺ doped drain region of an n-channel LDMOS transistor, a p ⁺ doped p-channel LDMOS transistor, characterized in that the emitter region of the insulated collector extends between the associated oxides and is perpendicular to the PNP bipolar transistor. a drain region of the n- channel MOS transistor by doping the source region, n ^+, and in the PNP transistor is doped with p ⁺ It is characterized by having a depth sufficient to contain the meter area.

In the case of n-channel LDMOS transistors, the presence of this auxiliary n-doped region obtained by injecting phosphorus through the drain region causes the field strength between the drain and gate to increase the breakdown voltage, which is the conduction resistance (R) of the transistor. This is particularly advantageous when the LDMOS transistor itself is used as an integrated power switching device, as the field strength between the drain and the gate is reduced while acquiring a decrease in _ON ), as is often the case in the mixing technology of these integrated devices.

In the case of a p-channel LDMOS transistor, the same auxiliary n-doped region can conveniently construct a body region formed without other specific additional processing steps.

When an n-doped region is provided with phosphorus, the CMOS structure formed by the LDMOS auxiliary transistor pair can operate with a supply voltage of about 20V without requiring special precautions such as field plates, thus concise You lose.

In the case of n-additional MOS transistors belonging to another type of CMOS structure, the n-doped region obtained by injecting phosphorus into the drain region of the transistor acts as a drain extension region, thereby reducing the sensitivity to electrical stress caused by high temperature electrons. This allows the transistor to withstand about 12V of power supply.

In the case of an insulated collector, a vertical PNP bipolar transistor, an additional n-doped region obtained by injecting through the emitter region of the transistor, increases the charge in the transistor base region, thereby improving the performance of the transistor and Increase the punchthrough voltage between the rotor and collector.

The ability to withstand the specially increased operating voltage of PNP transistors perpendicular to different CMOS structures allows for the creation of mixed integrated circuits (i.e. smart power devices) with even more severe interference problems among different circuit types, It allows you to fully expose the unique features of different devices and have a higher degree of dependence.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

A smart power type integrated circuit that is relatively easy to implement the present invention is shown in FIG. The cross-section shown includes a VDMOS power transistor, which can be easily thought from the region shown in the partial cross-section of the same figure, in which two different structures are shown, with the first structure being an n-channel and a p-channel. The structure of the collector formed by the LDMOS transistor and the second structure by the p-channel and by the n-channel MOS transistor, and the structure of the insulated collector is a vertical PNP bipolar transistor.

The device comprises a p-type silicon substrate (1), on which the epitaxial n-type silicon layer (2) forms a single crystal to form an n ⁺ bite layer (3) and a p-type bottom isolation (4). A portion made on the surface of the silicon substrate 1 is grown after doping with arsenic and / or boron. The integrated device further comprises an isolated insulation structure among several other integrated devices, and in the illustrated embodiment, the p-well region 6 (i.e., the upper insulation and the p-well), according to well-known techniques, During the growth of the field oxide (5), growth is carried out on the silicon surface (2) after doping a predetermined portion on the silicon surface with boron to form a dark boron doped region, also known as a p-field region, according to known techniques. Formed by the field oxide layer 5.

A gate structure 12 is usually formed of doped polycrystalline silicon in an active region where MOS-type devices are to be formed.

Typically, an n-channel LDMOS transistor injects boron under auto-tuning conditions into a source portion extending between gate 12 and field oxide 9 and then implanted boron until a desired diffusion longitudinal section of region 7 is obtained. P-body region, n ⁺ source and drain junction 10 generated in the silicon by implanting a, and p ⁺ region 9 having a relatively high doping level formed in the source region to contact the body region 7 do.

Similarly, the p-channel LDMOS transistor has a p-doped region 7 (having the same longitudinal section of the n-channel LDMOS body region) formed in the drain region of the transistor, the p ⁺ drain and source junction 9 and the n-body region. The formation of n ⁺ region 10 formed in the source region for contacting, together with other n-regions in other integrated structures, will be described next in accordance with the present invention.

The p-channel MOS transistor forming the second CMOS structure shown in FIG. 1 usually includes a source and drain p ⁺ junction 9 and a back gate contact, n ⁺ region formed in the source region of the transistor. Similarly, the n-channel MOS transistor includes n ⁺ source and drain coupling 10 and a back gate contact formed in the source region of the transistor.

The structure of the isolated collector PNP vertical transistor comprises collector C and emitter E contact p ⁺ diffusion 9 and base B n ⁺ contact diffusion 10.

According to the present invention, the n-type region 8 doped with phosphorus is at least n-channel LDMOS transistor n ⁺ drain junction, p ⁺ source junction of n-channel LDMOS transistor and n ⁺ body contact region, n-channel MOS, respectively. N-channel LDMOS transistor drain region between the gate electrode and the isolation oxide from the surface of the epitaxial layer, with a depth sufficient to contain the n ⁺ drain junction of the transistor and the n ⁺ emitter junction of the PNP transistor, the gate electrode and the isolation system P-channel LDMOS transistor source region interposed between oxides, drain region of n-channel MOS transistor interposed between gate electrode and adjacent isolation oxide, and isolated collector PNP bipolar transistor emitter region formed by surrounding isolation oxide Respectively spread.

These n-type regions 8 are evident in the schematic cross section shown in FIG.

As will be apparent to those skilled in the art, the phosphorus is simply inserted into the auto-adjustment conditions in the region where the separate region 8 is marked, and the arsenic contained in the secondary region 8 is inserted and diffused therein. Prior to the formation of the doped p ⁺ region obtained by injecting and diffusing the doped n ⁺ region and boron obtained by diffusing the inserted phosphorus in the indicated region without requiring an important treatment step At the same time, it can be easily formed. In the normal fabrication process, the doping level of the n-region 8 of the stock price is 10 ¹³ to 10 ¹⁴ p atoms per one centimeter.

Figure 2 shows a transistor with no secondary n-doped region (8 in FIG. 1) subjected to a 20V bias in accordance with the present invention, n- having a 600 angstrom thick gate oxide generated by computer model simulation. The electric field line in the overlapping region between the channel LDMOS transistor gate and the drain region is shown. The maximum field strength is estimated to be 6 × 10 ⁵ V / cm.

In FIG. 3, the same bias condition (20V) as in the example shown in FIG. 2, except that the n-channel LDMOS transistor is provided with an auxiliary n-region doped with phosphorus of 10 ¹⁴ atoms per cubic centimeter according to the present invention. The same form is shown in the same overlapping area below. As can be readily seen by comparing FIG. 2 and FIG. 3, in FIG. 3, the same shape is more distant than the length of FIG. 2, and the maximum field strength is 5 × 10 ⁵ V / cm. May be evaluated. This is 17% less than the maximum intensity evaluated for a transistor in a conventional doped region without a doped region with an auxiliary phosphorus.

The CMOS structure formed by the auxiliary LDMOS transistor provided with the n-doped region 8 (FIG. 1) according to the present invention acts as a supply voltage of 20V and eliminates the need for an appropriate level shifting circuit as a driving element to the VDMOS power transistor. Can be connected directly. Furthermore, the modified and modified LDMOS transistor structures in accordance with the present invention do not require the formation of field plates (according to known techniques for increasing the inherent breakdown voltage of the integrated transistor) which are inevitably shifted from the miniaturization of these integrated structures. The voltage of about 20V can be tolerated.

As will be apparent to those skilled in the art, the auxiliary LDMOS transistors shown in Figure 1 as forming CMOS structures can themselves be used as power transistors with appropriate arrangements, and voltage tolerance for such applications. The same improved performance is shown by the presence of the n-region 8 of the above-described stock price in accordance with the present invention in terms of capacity and reduced resistance R _On .

The electrical performance of another illustrated CMOS structure formed by a pair of auxiliary MOS transistors is improved because the n-region 8 formed at the drain of the n-channel transistor acts as a drain extension region and thus increases the nominal operating voltage of the associated CMOS structure. do.

By providing a phosphorus-doped n-region 8 that penetrates such an integrated device, an improved performance of an isolated collector, vertical PNP bipolar transistor is obtained from the point of view that is another non-negligible advantage. The resulting increase in base region doping level reduces the sensitivity to base region depletion and thus increases the punchthrough voltage between emitter and collector. This allows the integrated components of such smart power devices to operate under relatively high voltages, and are therefore prominent for other types of transistors to implement circuits with higher cutoff frequencies than can be obtained by horizontal PNP transistors. This broadens the possibilities for using suitable transistor types.

Claims (1)

at least one formed by a pair of auxiliary LDMOS transistors formed on an n-type epitec silicon layer grown on a p-type unity silicon substrate, the first having an n-type channel and the other having a p-type channel. A first CMOS structure, a second MOS structure formed of a pair of auxiliary MOS transistors, the first having a p-type channel and the other having an n-type channel, and at least one isolated collector, vertical PNP bipolar transistor. A monolithic integrated circuit comprising: a p-channel transistor formed between a gate electrode of a transistor, a drain region of the n-channel LDMOS transistor formed between an adjacent isolation oxide, and a p-channel transistor formed between a gate electrode of an transistor and an adjacent isolation oxide. The source region of the transistor and the gate electrode of the transistor The same diffusion termination diffused from the epitaxial layer surface in each of the drain region of the n-channel MOS transistor and the emitter region of the isolated collector and vertical PNP transistor made by a surrounding isolation field oxide The epitaxial layer depths described above, including n-type silicon regions doped with phosphorus, have n ⁺ drain diffusion of n-channel LDMOS transistors, p ⁺ source diffusion of p-channel LOMOS transistors, and n-channel MOS transistors, respectively. monolithic integrated circuit, sufficient to include n ⁺ drain diffusion, and p ⁺ emitter diffusion, and further diffused beyond the epitaxial layer into the isolated collector, vertical PNP transistor base region.