KR0166027B1 - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR0166027B1 KR0166027B1 KR1019940037785A KR19940037785A KR0166027B1 KR 0166027 B1 KR0166027 B1 KR 0166027B1 KR 1019940037785 A KR1019940037785 A KR 1019940037785A KR 19940037785 A KR19940037785 A KR 19940037785A KR 0166027 B1 KR0166027 B1 KR 0166027B1
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 21
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000000206 photolithography Methods 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 229910001111 Fine metal Inorganic materials 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 230000007257 malfunction Effects 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 230000007547 defect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 210000004185 liver Anatomy 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히, 소자 보호막으로 사용되는 실리콘 질화막을 이용하여 미세 접촉창 및 미세 금속선을 동시에 형성하여 포토 리소그라피 공정의 스텝퍼(stepper)를 이용한 정렬시 오차를 없애 디자인상 충분히 공정 여유도를 확보할 수 있는 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a micro contact window and a fine metal line are simultaneously formed using a silicon nitride film used as a device protection film, thereby eliminating an error during alignment using a stepper of a photolithography process. The present invention relates to a metal wiring forming method capable of sufficiently securing a process margin.
본 발명은, 반도체 기판 상부에 필드 산화막, 게이트 전극, 확산 영역을 형성하고, 전면에 절연막을 형성한 후, 확산 영역 상부의 절연막을 제거하여 접촉창을 형성하며 금속 배선을 노출된 확산 영역에 접속하는 반도체 소자의 제조 방법에 있어서, 상기 확산 영역 상부에 미세 콘택을 형성하기 위하여, 반도체 기판상에 필드 산화막, 게이트 전극, 확산 영역을 순차적으로 형성한 후, 전면에 절연막으로서 BPSG막 및 질화막을 형성하는 단계와, 감광막 패턴을 마스크로 하여 상기 확산 영역 상부의 질화막을 식각하는 단계, 전면에 산화막을 형성한 후 이방성 식각을 실시하여 질화막 측벽에 스페이서를 형성하는 단계, 상기 확산 영역 상부의 BPSG막과 스페이서를 식각하여 접촉창을 형성하는 단계, 및 상기 접촉창에 금속막을 형성하여 금속 배선을 완성하는 단계로 이루어져, 본 발명에 의하면, 질화막을 금속 배선 전에 증착함으로써, 사진 식각 공정에 의한 오정렬에 따른 금속 배선 형성시 금속 배선 패턴 불량을 감소시켜 반도체 소자의 오동작을 방지할 수 있고, 서브 마이크론 금속 배선 또한 용이하게 형성할 수 있다.According to the present invention, a field oxide film, a gate electrode, and a diffusion region are formed over a semiconductor substrate, an insulating film is formed over the entire surface, and then an insulating window is formed over the diffusion region to form a contact window, and the metal wiring is connected to the exposed diffusion region. In the method of manufacturing a semiconductor device, in order to form a fine contact on the diffusion region, a field oxide film, a gate electrode, and a diffusion region are sequentially formed on a semiconductor substrate, and then a BPSG film and a nitride film are formed on the front surface as an insulating film. And etching the nitride film over the diffusion region using the photoresist pattern as a mask, forming an oxide film over the entire surface, and then performing anisotropic etching to form a spacer on the sidewall of the nitride film, wherein the BPSG film over the diffusion region is formed. Etching the spacers to form a contact window, and forming a metal film on the contact window to complete metal wiring. According to the present invention, by depositing the nitride film before the metal wiring, by reducing the metal wiring pattern when forming the metal wiring due to the misalignment by the photolithography process, it is possible to prevent the malfunction of the semiconductor device, the sub-micron metal wiring It can also be easily formed.
Description
제1도 내지 제4도는 본 발명의 반도체 소자의 제조 방법의 공정을 순차적으로 나타내는 단면도.1 to 4 are cross-sectional views sequentially showing the steps of the method of manufacturing a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 절연막(필드 산화막)1 semiconductor substrate 2 insulating film (field oxide film)
3 : 게이트 산화막 4 : 게이트 전극3: gate oxide film 4: gate electrode
5 : 확산 영역 6 : 절연 산화막5: diffusion region 6: insulating oxide film
7 : 질화막 8 : 감광막 패턴7: nitride film 8: photosensitive film pattern
9 : 스페이서 10 : 금속막9 spacer 10 metal film
11 : 소자 보호막11: element protection film
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히, 소자 보호막으로 사용되는 실리콘 질화막을 이용하여 미세 접촉창 및 미세 금속선을 동시에 형성하여 포토 리소그라피 공정의 스텝퍼(stepper)를 이용한 정렬시 오차를 없애 디자인상 충분히 공정 여유도를 확보할 수 있는 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a micro contact window and a fine metal line are simultaneously formed using a silicon nitride film used as a device protection film, thereby eliminating an error during alignment using a stepper of a photolithography process. The present invention relates to a metal wiring forming method capable of sufficiently securing a process margin.
일반적으로 소자의 집적도가 증가하고, 다층 금속 배선이 이루어지므로, 소자의 막이 적층됨에 따라 패턴의 차이에 의한 단차비가 심해지면서 상대적으로 콘택홀의 크기가 작아지게 되므로, 사진 식각 공정에 의한 소정의 콘택홀을 형성하면 노광기의 노출시 발생하는 난반사 영향 및 노광기의 정렬시 발생오차, 접촉창에 금속선 형성시 금속선의 패턴불량 및 정렬불량으로 인한 소자의 수율감소 및 신뢰성에 많은 영향을 주고 있다.In general, since the degree of integration of the device is increased and the multi-layer metal wiring is formed, as the layer of the device is stacked, the step size ratio due to the difference in the pattern becomes relatively small and the size of the contact hole is relatively small. Formation of the structure has a large effect on the yield reduction and reliability of the device due to the diffuse reflection effect generated during exposure of the exposure machine and the occurrence error during alignment of the exposure machine, pattern defects and misalignment of the metal wire when forming the metal wire in the contact window.
종래의 반도체 장치의 금속 배선 공저에 대하여 개략적으로 살펴보면 반도체 기판 상부에 기본 전극을 제조한 후, 상층과의 전기적 절연을 위한 절연층으로 PSG 또는 BPSG와 같은 절연 산화막을 증착한 다음, 콘택이 이루어질 영역을 사진 식각 공정에 의하여 설정한 후, 금속 배선을 실시한다. 그 후, 금속 배선과 기 형성된 소자를 보호하기 위한 패시베이션층을 도포하는데, 이때의 패시베이션층으로 수분 흡수의 능력을 갖는 질화막이 많이 사용된다.In the schematic diagram of the metal wiring co-operation of a conventional semiconductor device, after fabricating a basic electrode on an upper surface of a semiconductor substrate, an insulating oxide film such as PSG or BPSG is deposited as an insulating layer for electrical insulation with an upper layer, and then a contact is made. After setting by the photolithography process, metal wiring is performed. Thereafter, a passivation layer for protecting the metal wiring and the pre-formed element is applied, and a nitride film having a capability of absorbing moisture is often used as the passivation layer at this time.
그러나, 상기에 서술한 바와 같이 사진 식각 공정시 노광기의 의한 오정렬 및 난반사 때문에 패턴의 불량 및 소자 자체가 불량해지는 문제점이 발생되었다.However, as described above, a problem arises in that the pattern is defective and the device itself is poor due to misalignment and diffuse reflection by the exposure machine during the photolithography process.
본 발명은 위와 같은 문제점 해결을 위한 것으로서, 접촉창과 금속 배선을 동시에 형성하기 위하여 공정 순서를 변경하여 디자인 여유도 증가시키고, 오정렬을 방지할 수 있는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다.An object of the present invention is to provide a method of manufacturing a semiconductor device that can increase the design margin by changing the order of processes to simultaneously form the contact window and the metal wiring, and prevent misalignment.
상기한 본 발명의 목적을 달성하기 위하여 반도체 소자의 제조 방법에 있어서, 반도체 기판사에 필드 산화막, 게이트 전극, 확산 영역을 순차적으로 형성한 후, 전면에 절연막인 BPSG 막을 도포하는 단계와, 질화막을 증착하는 단계와, 감광막 패턴을 마스크로 하여 금속 접촉을 이룰 소정의 부분의 질화막을 식각하는 단계, 전면에 산화막을 형성한 후 질화막 측벽에 스페이서를 제조하는 단계와, 금속 접촉을 이룰 소정 부분의 BPSG막을 식각하여 접촉창을 형성하는 단계, 및 상기 접촉장에 금속막을 형성하여 금속 배선을 완성하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object of the present invention, in the method of manufacturing a semiconductor device, after forming a field oxide film, a gate electrode, and a diffusion region in the semiconductor substrate yarn in sequence, applying a BPSG film as an insulating film on the entire surface, and the nitride film Depositing, etching a predetermined portion of the nitride film to be made into metal contact using the photoresist pattern as a mask, forming an oxide film on the entire surface, manufacturing a spacer on the sidewall of the nitride film, and forming a BPSG of the predetermined portion to be made into metal contact. Forming a contact window by etching the film, and forming a metal film in the contact field to complete the metal wiring.
이하, 본 발명의 일 실시예를 첨부도면에 의거하여 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
우선, 제1도에 도시된 바와 같이, 반도체 소자 내부의 기본 전극 제조 후 소자간 연결을 위한 금속 배선을 형성하기 위하여 먼저, 반도체 기판(1)의 LOCOS(local oxidation of silicon) 기술에 의하여 반도체 소자간을 전기적으로 분리하기 위한 절연막(피일드 산화막)(2)을 형성한다. 그 후, 반도체 소자부에 게치트 산화막(3)을 전면에 도포하고, 폴리 실리콘인 게이트 전극(4)을 형성한 다음, 게이트 전극(4)을 마스크로 하여 반도체 기판(1) 표면 근방의 반도체 소자부에 반도체 영역을 형성하기 위한 불순물을 주입한다.First, as shown in FIG. 1, in order to form a metal wiring for connection between devices after fabrication of a basic electrode inside the semiconductor device, first, a semiconductor device is manufactured by a local oxidation of silicon (LOCOS) technology of the semiconductor substrate 1. An insulating film (feed oxide film) 2 for electrically separating the liver is formed. Thereafter, a gett oxide film 3 is applied to the entire surface of the semiconductor element, a gate electrode 4 made of polysilicon is formed, and the semiconductor near the surface of the semiconductor substrate 1 using the gate electrode 4 as a mask. An impurity is implanted into the element portion to form a semiconductor region.
이 불순물의 주입 공정은 N모오스일 경우 측면 확산이 적은 비소(As)를 1×1016원자수/㎠ 정도의 농도로 80KeV 정도의 에너지로써 주입함이 바람직하다. 상기 불순물을 고온 열처리에 의한 확산을 행하여, 제1도에 도시된 바와 같이 자기 정합(self alignment)에 의한 반도체 확산 영역(소오스 드레인 영역)(5)을 형성한다. 그 후, 전면에 절연 산화막(6)을 형성한다. 이 절연 산화막(6)은 반도체 장치의 특성에 영향을 부여하는 이동 전하를 포획하거나, 다층에 의한 융기를 완화하는 PSG를 이용하여도 되지만, 저온에서 증착이 잘 이루어지는 성질을 갖는 BPSG막을 이용하는 것이 바람직하다. 그리고나서, PECVD 공정을 이용하여 질화막(7)을 형성한 후, 사진 식각 공정에 의한 감광막을 이용한 패턴을 이용하여 접촉창 형성 패턴(8)을 형성한다. 이때의 질화막(7)은 추후에 증착하여 공정 중의 수분을 흡수하는 역할을 하지만, 본 발명에서는 두 가지의 역할로써 작용하게 된다.In the impurity implantation step, in the case of N-Mos, arsenic (As) having low lateral diffusion is preferably implanted with energy of about 80 KeV at a concentration of about 1 × 10 16 atoms / cm 2. The impurities are diffused by high temperature heat treatment to form a semiconductor diffusion region (source drain region) 5 by self alignment, as shown in FIG. Thereafter, an insulating oxide film 6 is formed on the entire surface. The insulating oxide film 6 may use a PSG that traps mobile charges affecting the characteristics of the semiconductor device or alleviates the swelling due to the multilayer, but it is preferable to use a BPSG film having a property of evaporation at low temperatures. Do. Then, after the nitride film 7 is formed using the PECVD process, the contact window forming pattern 8 is formed using the pattern using the photosensitive film by the photolithography process. At this time, the nitride film 7 serves to absorb moisture in the process by depositing later, in the present invention serves as two roles.
첫째로는, BPSG막의 절연성을 보완하는 역할과 둘째로는, 금속 배선시 스텝퍼에 의한 오정렬 및 금속 배선의 패턴 불량을 방지할 수 있는 막으로 작용한다.First, it serves to complement the insulation of the BPSG film, and second, to act as a film that can prevent misalignment caused by the stepper during the metal wiring and pattern defect of the metal wiring.
그 후, 접촉창을 형성하기 위하여 사진 식각 공정에 의한 감광막 패턴을 형성하여 질화막(7)을 건식 식각에 의한 이방성 식각을 진행한 다음, 질화막 전면과 측면에 산화막, 예를 들면 SiO2막을 증착시킨다. 그 후, 상기 산화막을 블랭킷 식각에 의한 이방성 식각하여 산화막 스페이서(9)을 형성한다.(제2도 참고)Thereafter, a photoresist pattern is formed by a photolithography process to form a contact window, and the nitride film 7 is subjected to anisotropic etching by dry etching, and then an oxide film, for example, an SiO 2 film is deposited on the front and side surfaces of the nitride film. Thereafter, the oxide film is anisotropically etched by blanket etching to form the oxide film spacer 9 (see also FIG. 2).
그리고나서, 후의 공정에 의하여 비트 선과 접촉하는 반도체 확산 영역(5) 및 게이트 전극(4) 상부의 절연막(6)을, 질화막(7) 및 그 측부의 스페이서(9)를 마스크로 하여 제거하므로써 접촉창을 형성한다. 이때, 콘택 홀의 공정 여유도를 확보하고, 공정의 효율을 증대시키기 위하여 접속부는 건식식각에 의하여 좁게 형성하고, 입구부는 습식식각에 의하여 넓게 형성함이 바람직하다. 상기의 습식식각을 진행하기 위한 화학 용액은 BOE(buffer oxide etchant) 케미컬을 이용한다. 다음, 접촉창 및 전면에 금속막(10)을 증착한다.Then, the semiconductor diffusion region 5 in contact with the bit line and the insulating film 6 on the upper portion of the gate electrode 4 are removed by using the nitride film 7 and the spacer 9 at the side thereof as a mask by a later step. Form a window. In this case, in order to secure the process margin of the contact hole and increase the efficiency of the process, the connection part is preferably narrowly formed by dry etching and the inlet part is widely formed by wet etching. The chemical solution for the wet etching process uses BOE (buffer oxide etchant) chemical. Next, the metal film 10 is deposited on the contact window and the entire surface.
상기 금속막(10)으로는 알루미늄의 힐록 또는 난반사를 방지하는 티타늄과 티타늄 질화막이 알루미늄과 함께 증착된다.(제3도 참고)As the metal film 10, titanium and a titanium nitride film for preventing hillock or diffuse reflection of aluminum are deposited together with aluminum (see FIG. 3).
이들의 일련의 공정에 의하여 본 실시예의 반도체 장치를 완성한다.The semiconductor device of this embodiment is completed by these series of steps.
또, 그 후에, 제4도에 도시된 바와 같이, 소자 보호막을 형성하기 위하여, 금속막(10)을 평탄화 식각한 후, 소자 보호막(11)을 증착하여 금속 배선 패턴을 완성할 수도 있다.After that, as shown in FIG. 4, in order to form the device protection film, the metal film 10 may be planarized and etched, and then the device protection film 11 may be deposited to complete the metal wiring pattern.
또한, 본 발명은 상기 실시예에 한정되지 않으며 그의 요지를 변경하지 않는 범위에서 여러 가지 변경을 할 수 있음은 물론이다.In addition, this invention is not limited to the said Example, Of course, various changes can be made in the range which does not change the summary.
이상 설명한 바와 같이 본 발명에 의하면, 고집적화에 따른 금속 배선 형성시 금속 패턴의 불량을 감소시켜 반도체 소자의 오동작을 방지할 수 있고, 서브 마이크론 금속 배선 또한 용이하게 형성할 수 있다.As described above, according to the present invention, a malfunction of a semiconductor device can be prevented by reducing defects of a metal pattern when forming metal wirings due to high integration, and submicron metal wirings can be easily formed.
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| KR100437623B1 (en) * | 1997-09-30 | 2004-07-16 | 주식회사 하이닉스반도체 | Method of manufacturing contact of semiconductor device without short between gate and contact |
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