KR0161875B1 - Wiring Formation Method of Semiconductor Device - Google Patents
Wiring Formation Method of Semiconductor Device Download PDFInfo
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- KR0161875B1 KR0161875B1 KR1019950026651A KR19950026651A KR0161875B1 KR 0161875 B1 KR0161875 B1 KR 0161875B1 KR 1019950026651 A KR1019950026651 A KR 1019950026651A KR 19950026651 A KR19950026651 A KR 19950026651A KR 0161875 B1 KR0161875 B1 KR 0161875B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract
본 발명은 반도체장치의 배선 형성방법에 관한 것으로, Cu배선의 장점인 낮은 저항과 우수한 일렉트로마이그레이션 특성은 살리면서 단점인 건식식각의 어려움과 낮은 내산화성 문제는 해결하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device, and to solve the problems of dry etching and low oxidation resistance, which are disadvantages while maintaining low resistance and excellent electromigration characteristics, which are advantages of Cu wiring.
본 발명은 도전층이 형성된 실리콘기판 전면에 절연층을 형성하는 공정과, 상기 절연층을 선택적으로 식각하여 상기 도전층 표면을 노출시키는 콘택홀을 형성하는 공정, 상기 콘택홀이 형성된 기판 전면에 밀착층 및 제1배리어금속층을 형성하는 공정, 상기 콘택홀 영역 부위에만 남도록 상기 밀착층 및 제1배리어금속층을 선택적으로 식각하는 공정, 유기금속 소오스를 사용한 선택적 증착방법에 의해 상기 콘택홀을 통해 상기 도전층과 접속되도록 상기 제1배리어금속층 상부에만 선택적으로 Cu층을 형성하는 공정, 기판 전면에 제2배리어금속층을 형성하는 공정, 및 상기 Cu층의 노출된 표면을 덮도록 상기 제2배리어금속층을 선택적으로 식각하는 공정을 포함하여 이루어지는 반도체장치의 배선 형성방법을 제공한다.The present invention provides a process of forming an insulating layer on the entire surface of the silicon substrate on which the conductive layer is formed, forming a contact hole to selectively expose the surface of the conductive layer by selectively etching the insulating layer, and closely contacting the entire surface of the substrate on which the contact hole is formed. Forming the layer and the first barrier metal layer, selectively etching the adhesion layer and the first barrier metal layer so as to remain only in the contact hole region, and performing the conductive hole through the contact hole by a selective deposition method using an organic metal source. Selectively forming a Cu layer only on the first barrier metal layer so as to be connected to the layer, forming a second barrier metal layer on the entire surface of the substrate, and selectively selecting the second barrier metal layer to cover an exposed surface of the Cu layer. A method of forming a wiring of a semiconductor device, including a step of etching the same, is provided.
Description
제1도는 종래의 Al배선 형성방법을 도시한 공정순서도.1 is a process flowchart showing a conventional Al wiring forming method.
제2도는 종래의 Cu배선 형성방법을 도시한 공정순서도.2 is a process flowchart showing a conventional method for forming a Cu wiring.
제3도는 본 발명에 의한 Cu배선 형성방법을 도시한 공정순서도.3 is a process flowchart showing a method for forming a Cu wiring according to the present invention.
제4도는 본 발명에 의한 선택적 Cu증착공정시 사용되는 MO소오스인 Cu(II)및 Cu(I)의 구조도.4 is a structural diagram of Cu (II) and Cu (I) which are MO sources used in the selective Cu deposition process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 게이트1 substrate 2 gate
3 : 불순물확산영역 4 : 비트라인3: impurity diffusion region 4: bit line
5 : 절연층 6 : 포토레지스트5: insulation layer 6: photoresist
7 : 밀착층 및 배리어금속층 8 : 텅스텐7: adhesion layer and barrier metal layer 8: tungsten
9 : Al 10 : 배리어금속층9: Al 10: barrier metal layer
11 : Cu11: Cu
본 발명은 반도체장치의 배선 형성방법에 관한 것으로, 특히 선택적(selective) 구리 배선구조를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device, and more particularly to a method for forming a selective copper wiring structure.
종래 반도체장치의 배선은 낮은 콘택저항과 제조공정의 용이함이라는 장점을 가지는 Al을 사용하여 형성하였으나, 반도체장치가 고집적화되어 감에 따라 정션 스파이킹(junction spiking)이나 일렉트로마이그레이션(electromigration)문제가 생기게 되고, 배선길이가 증가되고 금속박막의 단면적이 감소됨에 따른 저항 증가와 절연막 두께의 감소로 인한 기생 커패시턴스(parasitic capacitance) 증가동에 의해 RC시간지연이 증가하게 되어 소자의 동작속도를 느리게 하는 요인이 되어 Al배선의 한계가 나타나고 있는 실정이다.Conventional semiconductor device wiring is formed using Al, which has the advantages of low contact resistance and ease of manufacturing process. However, as semiconductor devices become highly integrated, there is a problem of junction spiking or electromigration. In addition, the RC time delay increases due to increased parasitic capacitance due to increased resistance and decreasing insulation thickness as the wiring length increases and the cross-sectional area of the metal thin film decreases the operation speed of the device. The limitation of Al wiring is showing.
이러한 요구에 따라 Al배선에 비해 낮은 저항을 가지면서 일렉트로마이그레이션 특성이 우수한 Cu배선의 실용화가 요구되는데, Cu배선의 경우에는 낮은 내산화성과 실리콘내부로의 빠른 확산성 및 건식식각의 어려움등으로 인해 그 실용화가 어려운 실정이다.This requirement requires the practical use of Cu wiring, which has lower resistance than Al wiring and excellent electromigration characteristics. In the case of Cu wiring, due to low oxidation resistance, fast diffusion into silicon, and difficulty in dry etching, The practical use is difficult.
종래기술에 의한 Al배선 형성방법을 제1도를 참조하여 설명하면 다음과 같다. 먼저, 제1도(a)에 도시된 바와 같이 불순물 확산영역(3)과 게이트(2) 및 비트라인(4)과 같은 도전층이 형성된 실리콘기판(1) 전면에 절연층(5)을 형성한후, 포토레지스트(6)를 이용한 사진식각공정을 통해 상기 절연층(5)을 선택적으로 식각하여 상기 도전층(2,3,4)들과 배선층을 접촉시키기 위한 콘택홀을 형성한다.A method of forming an Al wiring according to the prior art will be described with reference to FIG. First, as shown in FIG. 1A, an insulating layer 5 is formed on the entire surface of the silicon substrate 1 on which the impurity diffusion region 3 and the conductive layer such as the gate 2 and the bit line 4 are formed. After that, the insulating layer 5 is selectively etched through a photolithography process using the photoresist 6 to form contact holes for contacting the conductive layers 2, 3, and 4 with the wiring layer.
이어서 제1도(b)에 도시된 바와 같이 상기 포토레지스트를 제거한 후, 상기 콘택홀이 형성된 기판 전면에 밀착층 및 배리어금속층(7)으로서, 예컨대 Ti와 TiN 또는 TiW을 형성한 다음, 수소환원법이나 SiH4환원법등의 화학증착법(CVD;Chemical Vapor Deposition)을 이용하여 텅스텐(8)을 증착한 후 에치백하여 상기 콘택홀 내부에만 텅스텐층이 남도록 하여 콘택홀을 매립하는 텅스텐 플러그를 형성한다. 이때, 이 텅스텐의 증착 및 에치백공정은 생략할 수도 있다.Subsequently, the photoresist is removed as shown in FIG. 1 (b), and then, for example, Ti and TiN or TiW are formed as an adhesion layer and a barrier metal layer 7 on the entire surface of the substrate on which the contact holes are formed. Tungsten (8) is deposited by chemical vapor deposition (CVD) such as SiH 4 reduction or the like, and then etched back to form a tungsten plug which fills the contact hole by leaving a tungsten layer only inside the contact hole. At this time, the deposition and etch back processes of tungsten may be omitted.
다음에 제1도(c)에 도시된 바와 같이 기판 전면에 Al(9)을 형성하고 이위에 다시 배리어금속층(10)으로서, TiN 또는 TiW를 형성하고 이를 포토레지스트(6)를 이용한 사진식각공정에 의해 소정패턴으로 패터닝하여 상기 텅스텐플러그를 통해 상기 도전층(2,3,4)들과 접속되는 배선층을 형성한다.Next, as shown in FIG. 1 (c), Al (9) is formed on the entire surface of the substrate, and again, as the barrier metal layer 10, TiN or TiW is formed, and the photolithography process using the photoresist 6 is performed. Patterned by a predetermined pattern to form a wiring layer connected to the conductive layers (2, 3, 4) through the tungsten plug.
다음에 종래기술에 의한 Cu배선의 형성방법을 제2도를 참조하여 설명한다.Next, a method of forming a Cu wiring according to the prior art will be described with reference to FIG.
먼저, 제2도(a)에 도시된 바와 같이 불순물 확산영역(3)과 게이트(2) 및 비트라인(4)과 같은 도전층이 형성된 실리콘기판(1) 전면에 절연층(5)을 형성한 후, 상기 절연층(5)을 선택적으로 식각하여 상기 도전층(2,3,4)들과 배선층을 접촉시키기 위한 콘택홀을 형성한다. 이어서 상기 콘택홀이 형성된 기판 전면에 밀착층 및 배리어금속층(7)으로서, 예컨대 Ti와 TiN 또는 TiW을 형성한다.First, as shown in FIG. 2A, an insulating layer 5 is formed on the entire surface of the silicon substrate 1 on which the impurity diffusion region 3 and the conductive layer such as the gate 2 and the bit line 4 are formed. After that, the insulating layer 5 is selectively etched to form contact holes for contacting the conductive layers 2, 3, and 4 with the wiring layer. Subsequently, for example, Ti, TiN, or TiW are formed as the adhesion layer and the barrier metal layer 7 on the entire surface of the substrate on which the contact hole is formed.
이어서 제2도(b)에 도시된 바와 같이 화학증착법이나 스퍼터링(sputtering)또는 ICBD(Ion Cluster Beam Deposition)이나 무전해 도금방법을 사용하여 상기 기판의 전표면에 Cu막(12)을 형성한 후, 이위에 확산방지층(13)으로서, TiN 또는 TiW를 형성한다.Subsequently, as shown in FIG. 2 (b), the Cu film 12 is formed on the entire surface of the substrate by chemical vapor deposition, sputtering, ion cluster beam deposition, or electroless plating. On this, as the diffusion barrier layer 13, TiN or TiW is formed.
다음에 제2도(c)에 도시된 바와 같이 상기 확산방지층(13) 및 Cu막(12)을 사진식각공정을 통해 소정패턴으로 패터닝하여 배선층을 형성한 후, 기판 전면에 다시 TiN 또는 TiW를 형성한 후, 이를 에치백하여 상기 형성된 Cu막(12)의 노출된 측면에 배리어금속층(14)을 형성한다.Next, as shown in FIG. 2C, the diffusion barrier layer 13 and the Cu film 12 are patterned in a predetermined pattern through a photolithography process to form a wiring layer, and then TiN or TiW is formed on the entire surface of the substrate. After forming, the barrier metal layer 14 is formed on the exposed side of the formed Cu film 12 by etching back.
상기한 종래의 배선 형성기술에 있어서, Al배선을 사용할 경우에는 소자의 고집적화가 진행되어 감에 따라 요구되는 낮은 저항과 일렉트로마이그레이션 특성을 만족시킬 수 있는 문제가 있으며, Cu배선의 경우에는 건식식각의 어려움으로 인해 포토레지스트를 사용한 패터닝공정이 어렵다. Cu배선을 형성하는 다른 방법으로는 Cu배선이 형성될 곳의 절연물질을 먼저 패터닝하고 Cu막을 형성한 후, CMP(Chimical Mechanical Polishing)공정을 행하는 것이 있는데 이는 공정이 복잡하고 불순물입자(particle)가 많이 발생하기 때문에 실용화가 어려운 실정이다.In the above-described conventional wiring forming technique, when Al wiring is used, there is a problem that high integration of the device can be progressed to satisfy the low resistance and electromigration characteristics required. In the case of Cu wiring, dry etching Due to the difficulty, the patterning process using the photoresist is difficult. Another method of forming the Cu wiring is to first pattern the insulating material where the Cu wiring is to be formed, form a Cu film, and then perform a CMP (Chimical Mechanical Polishing) process, which is complicated and impurity particles Since it occurs a lot, it is difficult to put it to practical use.
본 발명은 이와 같은 문제를 해결하기 위한 것으로, Cu배선의 장점인 낮은 저항과 우수한 일렉트로마이그레이션 특성은 살리면서 단점인 건식식각의 어려움과 낮은 내산화성 문제는 해결할 수 있는 Cu배선의 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve such a problem, to provide a method of forming a Cu wiring that can solve the problem of low etching resistance and low oxidation resistance, while maintaining the advantages of low resistance and excellent electromigration characteristics of the Cu wiring. The purpose is.
상기 목적을 달성하기 위한 본 발명의 반도체장치의 배선 형성방법은 도전층이 형성된 실리콘기판 전면에 절연층을 형성하는 공정과, 상기 절연층을 선택적으로 식각하여 상기 도전층 표면을 노출시키는 콘택홀을 형성하는 공정, 상기 콘택홀이 형성된 기판 전면에 밀착층 및 제1배리어금속층을 형성하는 공정, 상기 콘택홀 영역 부위에만 남도록 상기 밀착층 및 제1배리어금속층을 선택적으로 식각하는 공정, 유기금속 소오스를 사용한 선택적 증착방법에 의해 상기 콘택홀을 통해 상기 도전층과 접속되도록 상기 제1배리어금속층을 상부에만 선택적으로 Cu층을 형성하는 공정, 기판 전면에 제2배리어금속층을 형성하는 공정, 및 상기 Cu층의 노출된 표면을 덮도록 상기 제2배리어금속층을 선택적으로 식각하는 공정을 포함하여 이루어진다.The wiring forming method of the semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating layer on the entire surface of the silicon substrate on which the conductive layer is formed, and contact holes for selectively etching the insulating layer to expose the surface of the conductive layer. Forming the adhesive layer and the first barrier metal layer on the entire surface of the substrate on which the contact hole is formed, selectively etching the adhesive layer and the first barrier metal layer so as to remain only in the contact hole region, and an organic metal source Selectively forming the first barrier metal layer only on the upper portion of the first barrier metal layer so as to be connected to the conductive layer through the contact hole by using a selective deposition method, forming a second barrier metal layer on the entire surface of the substrate, and the Cu layer And selectively etching the second barrier metal layer to cover the exposed surface of the second barrier metal layer.
본 발명은 Cu배선의 단점인 건식식각의 어려움과 낮은 내산화성 문제를 TiN 또는 TiW등의 배리어금속층을 형성하고 패터닝한 후, 이 배리어금속층상에만 선택적으로 증착되는 선택적 Cu막을 형성하고 다시 배리어금속층을 Cu막 전표면에 형성함으로써 해결하는 것이다.According to the present invention, after forming and patterning a barrier metal layer such as TiN or TiW, the difficulty of dry etching and low oxidation resistance, which are disadvantages of Cu wiring, form a selective Cu film that is selectively deposited only on the barrier metal layer, and then again form a barrier metal layer. This is solved by forming on the entire surface of the Cu film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3도에 본 발명에 의한 Cu배선 형성방법을 공정순서에 따라 도시하였다.3 shows a method for forming a Cu wiring according to the present invention according to the process sequence.
먼저, 제3도(a)에 도시된 바와 같이 불순물 확산영역(3)과 게이트(2) 및 비트라인(4)과 같은 도전층이 형성된 실리콘기판(1) 전면에 절연층(5)을 형성한 후, 포토레지스트(6)를 이용한 사진식각공정을 통해 상기 절연층(5)을 선택적으로 식각하여 상기 도전층(2,3,4)들과 배선층을 접촉시키기 위한 콘택홀을 형성한다.First, as shown in FIG. 3A, an insulating layer 5 is formed on the entire surface of the silicon substrate 1 on which the impurity diffusion region 3 and the conductive layer such as the gate 2 and the bit line 4 are formed. After that, the insulating layer 5 is selectively etched through a photolithography process using the photoresist 6 to form contact holes for contacting the conductive layers 2, 3, and 4 with the wiring layer.
이어서 제3도(b)에 도시된 바와 같이 상기 포토레지스트를 제거한 후, 상기 콘택홀이 형성된 기판 전면에 밀착층으로서 예컨대 Ti를 형성하고, 계속해서 배리어금속층으로서, 예컨대 TiNx, TiWx, Ta, TaNx, WNx, TaSixNy, WBxNy, TiSixNy중에서 선택한 어느 하나를 형성하여 밀착층 및 배리어금속층(7)을 형성한 다음, 포토레지스트(6)를 이용한 사진식각공정을 통해 배선층이 형성될 부분, 즉, 상기 콘택홀 영역에만 남도록 상기 밀착층 및 배리어금속층(7)을 패터닝한다.Subsequently, the photoresist is removed as shown in FIG. 3 (b), and then Ti is formed on the entire surface of the substrate on which the contact hole is formed, for example, Ti, followed by TiNx, TiWx, Ta, TaNx as a barrier metal layer. , WNx, TaSixNy, WBxNy, TiSixNy to form any one of the adhesion layer and the barrier metal layer (7), and then the portion where the wiring layer is to be formed by a photolithography process using the photoresist 6, that is, the contact The adhesion layer and the barrier metal layer 7 are patterned so as to remain only in the hole region.
다음에 제3도(c)에 도시된 바와 같이 유기금속(MO;Metal-Organic)소오스를 사용하여 선택적 Cu증착공정을 행하여 상기 밀착층 및 배리어금속층(7)이 형성된 부분, 즉, 콘택홀내에만 Cu(11)가 형성되도록 한다. 이때, MO소오스로는 Cu(II)화합물인 Cu(II)(β-diketonate)2 또는 Cu(I)화합물인 Cyclopentadiene, Cu(I)trialkyl- phosphine, Cu(I)t-butoxide tetramer, Lewis-base stabilized Cu(I)β-diketonate 화합물등을 사용하는 것이 바람직하다. 여기서, β-diketonate 및 Lewis-base는 아래의 표로 나타내었으며, Cu(II) 및 Cu(I)의 구조는 제4도의 (a)와 (b)에 각각 도시하였다.Next, as shown in FIG. 3 (c), a selective Cu deposition process is performed using an organic metal (MO) source to form the contact layer and the barrier metal layer 7 in the contact hole. Only Cu (11) is formed. At this time, the MO source may be Cu (II) (β-diketonate) 2, which is a Cu (II) compound, or cyclopentadiene, Cu (I) trialkyl-phosphine, Cu (I) t-butoxide tetramer, or Lewis-, which is a Cu (I) compound. It is preferable to use a base stabilized Cu (I) β-diketonate compound or the like. Here, β-diketonate and Lewis-base are shown in the table below, and the structures of Cu (II) and Cu (I) are shown in (a) and (b) of FIG. 4, respectively.
상기 선택적 Cu증착공정시 압력은 0.01-0.5Torr, 온도는 140-220℃, 소오스의 양은 0.01-10g을 사용하는 것이 바람직하다.In the selective Cu deposition process, the pressure is 0.01-0.5 Torr, the temperature is 140-220 ° C., and the amount of the source is preferably 0.01-10 g.
이어서 밀착층 및 배리어금속층(7)영역 이외의 영역에 부분적으로 남아 있는 Cu를 제거하기 위해 건식식각을 행한다. 이때, 이 공정을 생략할 수도 있다.Subsequently, dry etching is performed to remove Cu partially remaining in regions other than the adhesion layer and barrier metal layer 7 region. At this time, this step may be omitted.
다음에 제3도(d)에 도시된 바와 같이 배리어금속층(10)으로서, 예컨대 TiN 또는 TiW를 기판 전면에 형성한 후, 포토레지스트(6)를 이용한 사진식각공정을 통해 상기 밀착층 및 배리어금속층(7)패턴보다 조금 크게 상기 배리어금속층(10)을 패터닝하여 상기 형성된 Cu(11)의 전표면에 배리어금속층(10)이 형성되도록 함으로써 Cu배선공정을 완료한다.Next, as shown in FIG. 3 (d), as the barrier metal layer 10, for example, TiN or TiW is formed on the entire surface of the substrate, and then the adhesion layer and the barrier metal layer are formed through a photolithography process using the photoresist 6. (7) The Cu wiring process is completed by patterning the barrier metal layer 10 to be slightly larger than the pattern so that the barrier metal layer 10 is formed on the entire surface of the formed Cu 11.
이상 상술한 바와 같이 본 발명에 의하면, Cu배선의 장점인 낮은 저항 및 우수한 일렉트로마이그레이션 특성을 그대로 살리면서 단점인 건식식각이 어려움을 선택적 증착방법을 통해 해결함으로써 Cu배선을 실용화할 수 있다.As described above, according to the present invention, the Cu wiring can be put to practical use by solving the disadvantage of dry etching, which is a disadvantage, by using the selective deposition method while maintaining the low resistance and the excellent electromigration characteristics of the Cu wiring.
Claims (5)
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| KR1019950026651A KR0161875B1 (en) | 1995-08-25 | 1995-08-25 | Wiring Formation Method of Semiconductor Device |
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| KR1019950026651A KR0161875B1 (en) | 1995-08-25 | 1995-08-25 | Wiring Formation Method of Semiconductor Device |
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