KR0161411B1 - High temperature oxide film manufacturing method - Google Patents
High temperature oxide film manufacturing method Download PDFInfo
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- KR0161411B1 KR0161411B1 KR1019950014344A KR19950014344A KR0161411B1 KR 0161411 B1 KR0161411 B1 KR 0161411B1 KR 1019950014344 A KR1019950014344 A KR 1019950014344A KR 19950014344 A KR19950014344 A KR 19950014344A KR 0161411 B1 KR0161411 B1 KR 0161411B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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Abstract
고온산화막 제조방법에 관해 개시되어 있다. 금속실리사이드층 상에 저압화학기상증착법에 의해 고온산화막을 형성하는 방법에 있어서, 상기 고온산화막은 소오스 가스인 N2O:SiH4의 혼합비율을 55:1 ~ 70:1로 하여 형성한다. 따라서, 고온산화막 표면에 요철이 생기는 것을 억제할 수 있다.A high temperature oxide film production method is disclosed. In the method of forming a high temperature oxide film on the metal silicide layer by a low pressure chemical vapor deposition method, the high temperature oxide film is formed with a mixing ratio of source gas N 2 O: SiH 4 of 55: 1 to 70: 1. Therefore, irregularities can be suppressed from occurring on the surface of the high temperature oxide film.
Description
제1도는 종래 실리사이드층 상에 HTO 막을 형성할 때 발생되는 문제점을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a problem caused when forming the HTO film on the conventional silicide layer.
제2도 본 발명에 따른 HTO 막 제조방법의 일 실시예를 설명하기 위한 단면도.2 is a cross-sectional view for explaining an embodiment of the HTO film production method according to the present invention.
제3a도 및 제3c도는 소오스 가스의 혼합비율에 따른 HTO 막의 표면 상태를 나타내는 SEM 사진.3a and 3c are SEM images showing the surface state of the HTO film according to the mixing ratio of the source gas.
본 발명은 산화막 제조공정에 관한 것으로, 특히 저압화학기상증착법으로 고온산화막(이하 HTO 막이라고 함)의 표면 개선방법에 관한 것이다.The present invention relates to an oxide film production process, and more particularly to a method for improving the surface of a high temperature oxide film (hereinafter referred to as HTO film) by low pressure chemical vapor deposition.
HTO 막은 절연막으로서의 용도 이외에, 이온주입이나 예칭공정시 마스크 또는 캐핑층(capping layer)등의 용도로 널리 이용되고 있다. 특히 64M 비트의 고집적 반도체 소자의 게이트 전극이나 비트라인 형성시 상기 용도로써 필수적으로 이용되고 있다.The HTO film is widely used not only as an insulating film but also as a mask or a capping layer in ion implantation or depositing. In particular, the gate electrode or the bit line of the 64M bit high-integral semiconductor device is essentially used for this purpose.
한편, 반도체 소자가 고집적화 되어감에 따라 소자의 패턴이 미세화되고 이에 적합한 저저항의 배선재료가 요구되어진다. 이를 위해 게이트 전극이나 비트라인의 배선재료로 널리 사용되고 있는 폴리실리콘막을 이용한 배선 대신에, 최근에는 고융점 금속과 실리콘의 화합물인 실리사이드층을 폴리실리콘막 상에 형성시킨 폴리사이드 배선에 이용되고 있다. 이러한 폴리사이드 배선 형성시, 상기 고융점 금속중에서 특히 텅스텐 실리사이드가 주로 이용되고 있다.On the other hand, as semiconductor devices become highly integrated, the pattern of the devices becomes finer, and a wiring material of low resistance suitable for this is required. For this purpose, instead of the wiring using the polysilicon film which is widely used as a wiring material of a gate electrode or a bit line, it is used for the polyside wiring which formed the silicide layer which is a compound of a high melting point metal and a silicon on the polysilicon film recently. In forming such polyside wirings, tungsten silicide is mainly used among the high melting point metals.
종래 실리사이드층 상에 HTO 막을 형성할 때 발생되는 문제점을 제1도를 참조하여 설명한다. 여기서 상기 실리사이드층은 텅스텐 실리사이드층을 예로 들며, 상기 HTO 막은 비트라인을 절연시키기 위한 절연막으로 형성되는 경우를 예로 든다.Problems occurring when the HTO film is formed on the conventional silicide layer will be described with reference to FIG. The silicide layer may be a tungsten silicide layer, and the HTO layer may be formed of an insulating film for insulating the bit line.
제1도를 참조하면, 반도체 기판(1) 상에 폴리실리콘층(3) 및 텅스텐 실리사이드층(5)을 구비하는 비트라인이 형성되어 있다. 비트라인(3 및 5)이 형성되어 있는 상기 결과물 상에, 비트라인을 절연시키기 위해 고온산화물을 저압화학기상증착법을 이용하여 증착하여 HTO 막(7)을 형성한다.Referring to FIG. 1, a bit line including a polysilicon layer 3 and a tungsten silicide layer 5 is formed on a semiconductor substrate 1. On the resultant on which the bit lines 3 and 5 are formed, hot oxides are deposited using low pressure chemical vapor deposition to form the HTO film 7 to insulate the bit lines.
여기에서, 상기 고온산화물은 통상적으로 800~830℃의 온도와 0.6~0.8Torr의 압력하에서 소오스 가스인 SiH4가스와 N2O 가스의 반응에 의해 형성된다. 이때, 상기 텅스텐 실리사이드층(5) 상에서 HTO 막(7) 형성시의 온도 800~830℃에서 발생된 텅스텐 실리사이드의 부산물인 텅스텐 화합물이 이온상태로 웨이퍼 전면에 존재하게 된다. 이들 텅스텐 화합물은 초기 표면반응단계에서 상기 소오스 가스 즉, SiH₄ 가스와 반응활성화를 일으킨다. 이로인해 이후 형성되는 상기 HTO 막(7)은 국부적으로 이상성장하여 HTO 막(7) 표면에 요철(9)이 발생한다. 즉, 이와 같은 표면요철(9)은 HTO 막(7) 형성시 소오스 가스인 SiH 가스와 금속화합물과의 결합에 의하여 발생한다.Here, the high temperature oxide is formed by the reaction of a source gas of SiH 4 gas and N 2 O gas at a temperature of 800 to 830 ° C. and a pressure of 0.6 to 0.8 Torr. At this time, a tungsten compound which is a by-product of tungsten silicide generated at a temperature of 800 to 830 ° C. when the HTO film 7 is formed on the tungsten silicide layer 5 is present on the entire surface of the wafer in an ionic state. These tungsten compounds cause reaction activation with the source gas, that is, SiH₄ gas, in the initial surface reaction step. As a result, the HTO film 7 formed afterwards grows abnormally locally, and irregularities 9 are generated on the surface of the HTO film 7. That is, such surface irregularities 9 are generated by the combination of the metal gas and SiH gas, which is a source gas, when the HTO film 7 is formed.
이러한 HTO 막 표면에 형성된 요철은 HTO 막 두께의 불균일을 초래하므로 이는 서브마이크론 이하의 미세 패턴을 형성하는 고집적 반도체 소자의 신뢰성을 저하시키고 반도체 소자의 특성을 저하시킨다.The unevenness formed on the surface of the HTO film causes unevenness of the thickness of the HTO film, which lowers the reliability of the highly integrated semiconductor device that forms a fine pattern of submicron or less and reduces the characteristics of the semiconductor device.
따라서, 본 발명은 금속층 상에 HTO 막 형성시 표면요철 현상을 방지하는 방법을 제공하는 것을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a method for preventing surface irregularities when the HTO film is formed on the metal layer.
상기 목적을 달성하기 위하여 본 발명은, 금속실리사이드층 상에 저압화학기상증착법에 의해 고온산화막을 형성하는 방법에 있어서, 상기 고온산화막은 소오스 가스인 N2O:SiH4의 혼합비율을 55:1~70:1로 하여 형성하는 것을 특징으로 하는 고온산화막 제조방법을 제공한다.In order to achieve the above object, the present invention provides a method for forming a high temperature oxide film on a metal silicide layer by low pressure chemical vapor deposition, wherein the high temperature oxide film has a mixing ratio of N 2 O: SiH 4 , which is a source gas, of 55: 1. It provides a high temperature oxide film production method characterized in that formed to ~ 70: 1.
바람직한 실시예에 의하면, 상기 금속실리사이드는 텅스텐 실리사이드이다.In a preferred embodiment, the metal silicide is tungsten silicide.
본 발명에 따르면, 소오스 가스인 N2O:SiN4의 혼합비율을 55:1~70:1로 하여 SiH₄ 가스비율을 감소시킴으로써 HTO 막의 표면요철을 방지할 수 있다.According to the present invention, the surface ratio of the HTO film can be prevented by reducing the SiH₄ gas ratio by setting the mixing ratio of N 2 O: SiN 4 as the source gas to 55: 1 to 70: 1.
이하, 첨부한 도면을 참조하여 본 발명의 일 실시예를 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.
제2도는 본 발명에 따른 HTO 막 제조방법의 일 실시예를 설명하기 위한 단면도이다. 제2도에 있어서, 상기 제1도에서와 동일한 도면부호는 동일한 부재를 나타낸다.2 is a cross-sectional view for explaining an embodiment of the HTO film production method according to the present invention. In Fig. 2, the same reference numerals as in Fig. 1 denote the same members.
제2도를 참조하면, 반도체 기판(1) 상에 폴리실리콘층(3) 및 실리사이드층, 예컨대 텅스텐 실리사이드층(5)을 구비하는 비트라인이 형성되어 있다. 비트라인(3 및 5)이 형성되어 있는 상기 결과물 상에, 비트라인을 절연시키기 위해 고온산화물을, 예컨대 저압화학기상증착법을 이용하여 증착하여 HTO 막(7)을 형성한다.Referring to FIG. 2, a bit line having a polysilicon layer 3 and a silicide layer such as a tungsten silicide layer 5 is formed on the semiconductor substrate 1. On the resulting bit lines 3 and 5, hot oxides are deposited, for example using low pressure chemical vapor deposition, to form the HTO film 7 to insulate the bit lines.
여기에서, 상기 HTO 막 (7)은 종래에서와 마찬가지로 800~830℃의 온도와 0.6~0.8Torr의 압력하에서 소오스 가스로 SiH4가스와 N2O가스를 사용하여 형성한다.Here, the HTO film 7 is formed using SiH 4 gas and N 2 O gas as the source gas at a temperature of 800 to 830 ° C. and a pressure of 0.6 to 0.8 Torr as in the prior art.
이때, 상기 HTO막은 소오스 가스 N2O:SiH4의 혼합비율을 종래 50:1 이하에서 55:1 이상, 예컨대 55:1~70:1로 변경하여 형성한다.At this time, the HTO film is formed by changing the mixing ratio of the source gas N 2 O: SiH 4 from 50: 1 or less to 55: 1 or more, for example, 55: 1 to 70: 1.
즉, 금속화합물, 예컨대 텅스텐화합물과 반응하는 소오스 가스 SiH4의 양을 감소시킴으로써 HTO 막 형성시 발생되는 국부적 이상성장을 방지할 수 있다. 따라서, HTO 막 표면요철 형성이 방지된다.That is, by reducing the amount of the source gas SiH 4 reacting with the metal compound, for example, tungsten compound, it is possible to prevent local abnormal growth generated during HTO film formation. Thus, HTO film surface irregularities formation is prevented.
본 출원인은 공정조건별, 예컨대 온도, 압력 및 소오스 가스의 혼합비율을 달리하여 텅스텐 실리사이드층 상에 HTO 막을 형성하고 형성된 막을 관찰하였다. 그 결과, 온도 및 압력 변화에 따른 HTO 막의 유의차는 미비하여, N2O/SiH4가스 혼합비율에 따라 HTO 막의 표면요철현상을 발견하였는데, 특히 SiH4가스의 비율이 높을수록 상기 요철현상은 심하게 발생하였다.Applicant observed the film formed by forming an HTO film on the tungsten silicide layer by varying the mixing ratio of the process gas, for example, temperature, pressure and source gas. As a result, the insufficient car significant HTO film according to temperature and pressure changes, N 2 O / SiH 4 gas in accordance with the mixing ratio were found HTO film, the surface roughness phenomenon, more particularly higher the ratio of SiH 4 gas badly is the uneven development Occurred.
제3a도 내지 제3c도는 소오스 가스의 혼합비율에 따른 HTO 막의 표면상태를 나타내는 SEM 사진으로서, 800~830℃의 온도와 0.6~0.8Torr의 압력하에서 저압화학기상증착법으로 소오스 가스 혼합비율만을 달리하여 수득한 소자의 단면을 보여준다. N2O/SiH4가스 혼합비율을 제3a도는 40:1로, 제3b도는 50:1, 제3c도는 60:1로 하여 HTO 막을 형성하였다.3a to 3c are SEM images showing the surface state of the HTO film according to the mixing ratio of the source gas. The cross section of the obtained device is shown. The N2O / SiH 4 gas mixing ratio was 40: 1 in FIG. 3a, 50: 1 in FIG. 3b, and 60: 1 in FIG. 3c to form HTO film.
상기 SEM 사진을 참조하면, SiH4가스의 비율이 높을수록 표면요철현상이 심하게 발생됨을 알수 있다. 즉, 종래의 HTO 막 제조시 사용하였던 N2O:SiH4의 소오스 가스 비율인 50:1 이하에서 표면에 요철이 심하나 60:1인 경우는 표면상태가 깨끗함을 보여준다.Referring to the SEM photograph, it can be seen that the higher the proportion of the SiH 4 gas, the worse the surface irregularities. That is, when the surface gas ratio of N 2 O: SiH 4 used at the time of manufacturing a conventional HTO film is 50: 1 or less, irregularities are severe on the surface, but the surface state is clean when 60: 1.
또한, 텅스텐 실리사이드의 침적조건인 SiH4/WF6의 비율, 어닐링 온도, 산화온도 및 RF 에칭의 물리적 손상을 가한후에도 HTO 막의 표면특성 변화는 없었다.In addition, the surface characteristics of the HTO film did not change even after the physical damage of the ratio of SiH 4 / WF 6 , annealing temperature, oxidation temperature, and RF etching, which are deposition conditions of tungsten silicide, was applied.
상술한 바와 같이 텅스텐 실리사이드층 상에 저압화학기상법으로 HTO 막을 형성할 경우 N2O:SiH4의 가스비율을 55:1~70:1로 하면 표면에 요철이 생기는 것을 억제할 수 있다.As described above, when the HTO film is formed on the tungsten silicide layer by a low pressure chemical vapor method, when the gas ratio of N 2 O: SiH 4 is set to 55: 1 to 70: 1, occurrence of irregularities on the surface can be suppressed.
본 발명에 따르면, 금속화합물, 예컨대 텅스텐화합물과 반응하는 소오스 가스, 예컨데 SiH4의 양을 감소시킴으로써 HTO 막 형성시 발생되는 국부적 이상성장을 방지할 수 있다. 따라서, HTO 막 표면요철 형성이 방지된다.According to the present invention, by reducing the amount of the source gas, for example SiH 4 reacting with the metal compound, such as tungsten compound, it is possible to prevent the local abnormal growth generated when forming the HTO film. Thus, HTO film surface irregularities formation is prevented.
본 발명은 상기 실시예에 한정되지 않으며 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 당분야의 통상의 지식을 가진자에 의한 다양한 응용이 가능함은 물론이다.The present invention is not limited to the above embodiments, and various applications by those skilled in the art are possible without departing from the technical spirit of the present invention.
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| KR (1) | KR0161411B1 (en) |
-
1995
- 1995-05-31 KR KR1019950014344A patent/KR0161411B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960043024A (en) | 1996-12-21 |
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