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KR0157921B1 - Field oxide film manufacturing method - Google Patents

Field oxide film manufacturing method Download PDF

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Publication number
KR0157921B1
KR0157921B1 KR1019950050639A KR19950050639A KR0157921B1 KR 0157921 B1 KR0157921 B1 KR 0157921B1 KR 1019950050639 A KR1019950050639 A KR 1019950050639A KR 19950050639 A KR19950050639 A KR 19950050639A KR 0157921 B1 KR0157921 B1 KR 0157921B1
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South Korea
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nitride film
etching
oxide film
cvd nitride
cvd
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KR1019950050639A
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Korean (ko)
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KR970052804A (en
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이상돈
김진호
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문정환
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 필드 산화막 제조 방법에 관한 것으로, 실리콘 기판에 패드 산화막을 증착하고 제1 CVD 질화막, 폴리 실리콘 및 제2 CVD 질화막을 차례대로 증착한 뒤, 포토 레지스트를 덮고 LOCOS 마스크를 사용하여 패턴을 형성하는 공정과; 상기 공정후 제2 CVD 질화막을 기울기(SLOPE)를 갖도록 식각하고 폴리 실리콘을 식각한 뒤 포토 레지스트를 제거한 다음에, 노출된 제1 CVD 질화막과 제2 CVD 질화막을 동시에 기울기를 갖도록 식각하는 공정과; 상기 공정 후 패드 산화막을 식각하고 실리콘 기판을 식각하는 공정과; 상기 공정 후 이온 주입 마스크를 이용하여 필드 이온 주입을 실시하는 공정으로 제조를 완료함으로써, 공정의 단순화를 이룰 수 있고 질화막의 두께 및 실리콘 식각량을 정확히 조절할 수 있는 장점을 갖는다.The present invention relates to a method for manufacturing a field oxide film, comprising depositing a pad oxide film on a silicon substrate, depositing a first CVD nitride film, a poly silicon, and a second CVD nitride film in turn, covering the photoresist, and forming a pattern using a LOCOS mask. To process; Etching the second CVD nitride film to have a slope after the process, removing the photoresist after etching polysilicon, and then simultaneously etching the exposed first CVD nitride film and the second CVD nitride film to have a slope; Etching the pad oxide layer after the step and etching the silicon substrate; After the manufacturing process is completed by the field ion implantation process using the ion implantation mask after the above process, the process can be simplified and the thickness of the nitride film and the silicon etching amount can be precisely controlled.

Description

필드 산화막 제조 방법Field oxide film manufacturing method

제1도는 종래 기술에 따른 필드 산화막의 제조를 도시한 공정 수순도.1 is a process flowchart showing the production of a field oxide film according to the prior art.

제2도는 본 발명에 따른 필드 산화막의 제조를 도시한 공정 수순도.2 is a process flowchart showing production of a field oxide film according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 실리콘 기판 12 : 패드 산화막11 silicon substrate 12 pad oxide film

13 : 제1 CVD 질화막 14 : 폴리 실리콘13 first CVD nitride film 14 polysilicon

15 : 제2 CVD 질화막 16 : 포토 레지스트15 second CVD nitride film 16 photoresist

17 : 필드 산화막17: field oxide film

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 질화막 측벽 로커스(Nitride Sidewall Local Oxidation of Silicon, 이하 NSL)같은 복잡한 공정을 사용하지 않는 단순한 공정으로 질화막의 두께와 실리콘 식각량을 정확히 조절할 수 있도록 한 필드 산화막 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a field in which the thickness and silicon etching amount of a nitride film can be accurately controlled by a simple process without using a complicated process such as nitride sidewall local oxide of silicon (NSL). It relates to an oxide film production method.

종래 NSL 기술에 의한 필드 산화막의 제조 방법에 대해 첨부된 도면을 참조하여 설명하면 다음과 같다.A method of manufacturing a field oxide film by the conventional NSL technique will be described with reference to the accompanying drawings.

먼저, 제1도의 (a)에 도시된 바와 같이 실리콘 기판(1)에 패드 산화막(2)을 성장시키고 제1 CVD 질화막(3)을 증착한다.First, as shown in FIG. 1A, a pad oxide film 2 is grown on a silicon substrate 1 and a first CVD nitride film 3 is deposited.

상기 공정 후, 포토 레지스트를 덮은 뒤 로커스(Local Oxidation of Sioicon, 이하 LOCOS) 마스크를 사용하여 제1 CVD 질화막(3)을 식각하고 포토 레지스트를 제거하여 LOCOS 패턴을 형성한다.After the process, after covering the photoresist, the first CVD nitride film 3 is etched using a Local Oxidation of Sioicon (LOCOS) mask and the photoresist is removed to form a LOCOS pattern.

이후, 질화막이 제거된 부분의 패드 산화막(2)을 제거하고 다시 측벽 패드 산화막(8)을 형성한 다음, 제2 CVD 질화막(5)을 증착한다.Thereafter, the pad oxide film 2 of the portion where the nitride film is removed is removed, and the sidewall pad oxide film 8 is formed again, and then the second CVD nitride film 5 is deposited.

그 다음, 제1도의 (b)에 도시한 바와 같이 상기 제2 CVD 질화막(5)을 건식각하여 질화막 측벽(NITRIDE SIDEWALL)을 형성하고 실리콘 기판(1)을 약간 식각한다.Next, as shown in FIG. 1 (b), the second CVD nitride film 5 is dry-etched to form a nitride film sidewall NITRIDE SIDEWALL, and the silicon substrate 1 is slightly etched.

상기 공정 후, 제1도의 (c)에 도시된 바와 같이 필드 이온 주입 마스크를 사용하여 필드 이온 주입 공정을 하고 필드 산화막(7)을 형성함으로써 공정을 완료한다.After the above process, the field ion implantation process is performed using a field ion implantation mask as shown in FIG. 1C, and the process is completed by forming the field oxide film 7.

상기와 같은 종래의 기술은 열산화(THERMAL OXIDATION) 공정이 2번, CVD 질화막 증착 공정이 2번, 열 산화막(THERMAL OXIDE) 식각 공정이 2번, 그리고 실리콘 식각 공정이 1번 필요하게 되어 공정이 복잡해진다.In the conventional technique, the thermal oxidation (THERMAL OXIDATION) process is required twice, the CVD nitride film deposition process is required twice, the thermal oxide (THERMAL OXIDE) etching process is required twice, and the silicon etching process is required once. It gets complicated.

또한 질화막 측벽의 식각시 식각량의 조절이 측벽 패드 산화막이나 실리콘 기판이 나타날때까지 되어야 하기 때문에 남아있는 질화막의 두께와 실리콘 식각량의 정확히 조절하기 힘든 문제점이 있다.In addition, there is a problem that it is difficult to precisely control the thickness of the remaining nitride film and the silicon etching amount because the etching amount must be controlled until the sidewall pad oxide layer or the silicon substrate is exposed during the etching of the sidewalls of the nitride layer.

본 발명은 상기와 같은 문제점을 해결하기 위하여 창안된 것으로, NSL등의 복잡한 기술을 사용하지 않아 공정을 단순화하고 질화막 식각시 발생하는 질화막 기울기를 이용하여 식각후의 질화막에 의하여 정의되는 액티브 영역의 폭을 원하는 양만큼 넓게 정의하기에 적당하도록 한 필드 산화막 제조 방법을 제공함에 그 목적이 있다.The present invention was devised to solve the above problems, and does not use complicated techniques such as NSL, which simplifies the process and uses the nitride film slope generated during etching of the nitride film to define the width of the active region defined by the nitride film after etching. It is an object of the present invention to provide a method for producing a field oxide film, which is suitable to be defined as wide as desired.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 필드 산화막 제조 방법은 실리콘 기판에 패드 산화막을 증착하고 제1 CVD 질화막과 폴리 실리콘 및 제2 CVD 질화막을 순차적으로 증착한 뒤, 포토 레지스트를 덮고 LOCOS 마스크를 사용하여 패턴을 형성하는 공정과; 상기 공정후 제2 CVD 질화막을 기울기(SLOPE)를 갖도록 식각하고 폴리 실리콘을 식각한 뒤 포토 레지스트를 제거한 다음에, 노출된 제1 CVD 질화막과 제2 CVD 질화막을 동시에 기울기를 갖도록 식각하는 공정과; 상기 공정후 패드 산화막을 식각하고 실리콘 기판을 식각하는 공정과; 상기 공정후 이온 주입 마스크를 이용하여 필드 이온 주입을 실시하는 공정으로 제조된다.Field oxide film manufacturing method according to the present invention for achieving the above object is to deposit a pad oxide film on a silicon substrate, sequentially depositing the first CVD nitride film and polysilicon and the second CVD nitride film, covering the photoresist and LOCOS mask Forming a pattern using; Etching the second CVD nitride film to have a slope after the process, removing the photoresist after etching polysilicon, and then simultaneously etching the exposed first CVD nitride film and the second CVD nitride film to have a slope; Etching the pad oxide layer after the step and etching the silicon substrate; After the process, it is manufactured by a process of performing field ion implantation using an ion implantation mask.

상기 공정 결과, 공정이 단순해지고 질화막의 두께와 실리콘의 식각량을 정확히 조절할 수 있다.As a result of the above process, the process is simplified and the thickness of the nitride film and the etching amount of silicon can be precisely controlled.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

먼저, 제2도의 (a)에 도시된 바와 같이 버드 빅(BIRD'S BEAK)을 고려한 액티브 영역의 폭을 확보한 후, 패드 산화막(12)을 증착한 다음 제1 CVD 질화막(13), 폴리 실리콘(14) 및 제2 CVD 질화막(15)을 순차적으로 증착한 뒤, 포토 레지스트(16)를 덮고 LOCOS 마스크를 사용하여 패턴을 형성한다.First, as shown in FIG. 2A, the width of the active region in consideration of BIRD'S BEAK is ensured, and then the pad oxide film 12 is deposited, and then the first CVD nitride film 13 and the polysilicon ( 14) and the second CVD nitride film 15 are sequentially deposited, then covers the photoresist 16 and forms a pattern using a LOCOS mask.

이때, 상기 패드 산화막(12)의 두께는 50-500Å으로 하고 폴리 실리콘(14)의 두께는 50-3000Å으로 한다.At this time, the thickness of the pad oxide film 12 is 50-500 kPa and the thickness of the polysilicon 14 is 50-3000 kPa.

다음으로, 제2도의 (b)에 도시된 바와 같이 제2 CVD 질화막(15) 및 폴리 실리콘(14)을 식각하고 포토 레지스트(16)를 제거한다.Next, as shown in FIG. 2B, the second CVD nitride film 15 and the polysilicon 14 are etched and the photoresist 16 is removed.

이때, 제1 CVD 질화막(13)의 두께는 패드 산화막(12)과의 비율에 의하여 미리 결정되고, 제2 CVD 질화막(15)의 두께는 제1 CVD 질화막(13)보다 작거나 같거나 크게 사용할 수 있으며 제1 CVD 질화막(13)과 제2 CVD 질화막(15)의 두께는 1000-3000Å으로 한다.In this case, the thickness of the first CVD nitride film 13 is determined in advance by the ratio with the pad oxide film 12, and the thickness of the second CVD nitride film 15 is smaller than, equal to, or larger than that of the first CVD nitride film 13. The thickness of the first CVD nitride film 13 and the second CVD nitride film 15 may be 1000-3000 mm 3.

또한, 제2 CVD 질화막(15)의 식각시 보통 기울기를 나타내게 되며 이러한 기울기에 의하여 LOCOS 포토 패턴 보다 식각 후의 패턴이 더 크게 정의된다.In addition, when the second CVD nitride film 15 is etched, a normal slope is displayed, and a pattern after etching is larger than the LOCOS photo pattern by this slope.

다음으로, 마스크를 사용하지 않고 노출된 제1 CVD 질화막(13)과 제2 CVD 질화막(15)을 동시에 식각한다.Next, the exposed first CVD nitride film 13 and the second CVD nitride film 15 are simultaneously etched without using a mask.

이때, 식각 종료 점(ETCH END POINT)은 제1 CVD 질화연막(13)과 제2 CVD 질화연막(15)의 두께에 따라 한 번에 잡히거나 또는 두번에 잡히게 되므로 원하는 제2 CVD 질화막(15)의 두께에 따라 식각 종료 점을 잡아 식각을 종료한다.At this time, the etch end point is caught at once or twice depending on the thickness of the first CVD nitride film 13 and the second CVD nitride film 15, so that the desired second CVD nitride film 15 is obtained. End the etching by grabbing the etching end point according to the thickness.

또한, 실리콘 기판(11)을 식각하지 않고 제1 CVD 질화막(13)의 두께가 제2 CVD 질화막의 두께보다 얇아 제1 CVD 질화막의 식각시 폴리 실리콘(14)이 다 식각되는 경우도 있으며 상기 폴리 실리콘(14) 대신에 CVD 산화막을 사용할 수도 있다.In addition, since the thickness of the first CVD nitride film 13 is thinner than the thickness of the second CVD nitride film without etching the silicon substrate 11, the polysilicon 14 may be etched when the first CVD nitride film is etched. Instead of the silicon 14, a CVD oxide film may be used.

상기 공정 후, 제2도의 (c)에 도시된 바와 같이 패드 산화막(12)을 식각하고 실리콘 기판(11)을 식각한다.After the above process, as shown in FIG. 2C, the pad oxide film 12 is etched and the silicon substrate 11 is etched.

이때, 실리콘 기판(11)의 식각시 식각 종료 점은 제1 CVD 질화막(13)의 위에 있는 폴리 실리콘(14)의 두께에 의하여 조절할 수 있으며, 따라서 원하는 실리콘의 식각량에 따라 폴리 실리콘(14)의 두께를 다르게 사용하면 된다.At this time, the etching end point during the etching of the silicon substrate 11 can be controlled by the thickness of the polysilicon 14 on the first CVD nitride film 13, and thus the polysilicon 14 according to the desired etching amount of silicon. You can use different thickness of.

이후, 제2도의 (d)에 도시된 바와 같이 마스크를 사용하여 필드 이온 주입을 실시하여 필드 산화막(17)을 형성함으로써 공정 진행을 완료한다.Subsequently, as shown in FIG. 2D, field ion implantation is performed using a mask to form a field oxide film 17 to complete the process.

본 발명에서는 열산화 공정이 1번, CVD 질화막 증착 공정이 2번, 폴리 실리콘 증착 공정이 1번, 열 산화막 식각 공정이 1번 그리고 실리콘 식각 공정이 1번 필요한 공정으로, 종래의 기술보다 공정이 단순해진다.In the present invention, the thermal oxidation process is one time, the CVD nitride film deposition process is two times, the polysilicon deposition process is one time, the thermal oxide film etching process is one time and the silicon etching process is required one time, the process is more than the conventional technology Simplify

상술한 바와 같이 본 발명에 의하면, 공정의 단순화가 이루어지고 질화막 식각시 식각 종료 점을 제1 CVD 질화막(13) 위에 있는 폴리 실리콘(14)에 의하여 검출할 수 있기 때문에 질화막 식각시 패드 산화막(12)과 실리콘 기판(11)이 식각되는 것을 방지할 수 있다.As described above, according to the present invention, since the process is simplified and the etching end point during the nitride film etching can be detected by the polysilicon 14 on the first CVD nitride film 13, the pad oxide film 12 during the nitride film etching. ) And the silicon substrate 11 may be prevented from being etched.

또한, 실리콘 기판(11)의 식각시에도 식각량을 폴리 실리콘(14)의 두께로 조절할 수 있기 때문에 정확하게 조절할 수 있는 장점이 있다.In addition, since the etching amount can be adjusted to the thickness of the polysilicon 14 even when the silicon substrate 11 is etched, there is an advantage that it can be accurately adjusted.

Claims (6)

실리콘 기판에 패드 산화막을 증착하고 제1 CVD 질화막, 폴리 실리콘 및 제2 CVD 질화막을 차례대로 증착한 뒤, 포토 레지스트를 덮고 LOCOS 마스크를 사용하여 패턴을 형성하는 공정과; 상기 공정후 제2 CVD 질화막을 기울기(SLOPE)를 갖도록 식각하고 폴리 실리콘을 식각한 뒤 포토 레지스트를 제거한 다음에, 노출된 제1 CVD 질화막과 제2 CVD 질화막을 동시에 기울기를 갖도록 식각하는 공정과; 상기 공정 후 패드 산화막을 식각하고 실리콘 기판을 식각하는 공정과; 상기 공정 후 이온 주입 마스크를 이용하여 필드 이온 주입을 실시하는 공정으로 제조되는 것을 특징으로 하는 필드 산화막 제조 방법.Depositing a pad oxide film on a silicon substrate, depositing a first CVD nitride film, a poly silicon, and a second CVD nitride film in turn, covering the photoresist and forming a pattern using a LOCOS mask; Etching the second CVD nitride film to have a slope after the process, removing the photoresist after etching polysilicon, and then simultaneously etching the exposed first CVD nitride film and the second CVD nitride film to have a slope; Etching the pad oxide layer after the step and etching the silicon substrate; And a field ion implantation method using an ion implantation mask after the step. 제1항에 있어서, 제1 CVD 질화막의 두께는 패드 산화막과의 비율에 의해 미리 결정되고, 제1 CVD 질화막 및 제2 CVD 질화막에 대하여 각각 1000-3000Å의 두께로 제조되는 것을 특징으로 하는 필드 산화막 제조 방법.2. The field oxide film according to claim 1, wherein the thickness of the first CVD nitride film is predetermined by a ratio with the pad oxide film, and is manufactured to a thickness of 1000-3000 kPa for the first CVD nitride film and the second CVD nitride film, respectively. Manufacturing method. 제1항에 있어서, 패드 산화막의 두께를 50-500Å으로 사용하여 제조되는 것을 특징으로 하는 필드 산화막 제조 방법.The method of manufacturing a field oxide film according to claim 1, wherein the pad oxide film is produced using a thickness of 50 to 500 kPa. 제1항에 있어서, 폴리 실리콘의 두께를 50-3000Å으로 사용하여 제조되는 것을 특징으로 하는 필드 산화막 제조 방법.The method of manufacturing a field oxide film according to claim 1, which is produced using a thickness of 50-3000 kPa of polysilicon. 제1항에 있어서, 실리콘 기판을 식각하지 않고 또한 제2 CVD 절연막의 두께가 제1 CVD 절연막의 두께보다 얇아 제1 CVD 절연막의 식각시 폴리 실리콘이 다 식각되도록 하여 제조되는 것을 특징으로 하는 필드 산화막 제조 방법.The field oxide film of claim 1, wherein the silicon oxide is not etched and the thickness of the second CVD insulating film is thinner than that of the first CVD insulating film so that polysilicon is etched when the first CVD insulating film is etched. Manufacturing method. 제1항에 있어서, 폴리 실리콘 대신 CVD 산화막을 사용하여 제조되는 것을 특징으로 하는 필드 산화막 제조 방법.The method of manufacturing a field oxide film according to claim 1, which is produced using a CVD oxide film instead of polysilicon.
KR1019950050639A 1995-12-15 1995-12-15 Field oxide film manufacturing method KR0157921B1 (en)

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