KR0157876B1 - Method of fabricating wire of semiconductor device - Google Patents
Method of fabricating wire of semiconductor device Download PDFInfo
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- KR0157876B1 KR0157876B1 KR1019950008643A KR19950008643A KR0157876B1 KR 0157876 B1 KR0157876 B1 KR 0157876B1 KR 1019950008643 A KR1019950008643 A KR 1019950008643A KR 19950008643 A KR19950008643 A KR 19950008643A KR 0157876 B1 KR0157876 B1 KR 0157876B1
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- copper
- film
- wiring
- forming
- copper silicide
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 69
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052802 copper Inorganic materials 0.000 claims abstract description 50
- 239000010949 copper Substances 0.000 claims abstract description 50
- JUZTWRXHHZRLED-UHFFFAOYSA-N [Si].[Cu].[Cu].[Cu].[Cu].[Cu] Chemical compound [Si].[Cu].[Cu].[Cu].[Cu].[Cu] JUZTWRXHHZRLED-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910021360 copper silicide Inorganic materials 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 25
- 239000010703 silicon Substances 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 238000010849 ion bombardment Methods 0.000 claims description 6
- -1 silicon ions Chemical class 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 4
- 239000007789 gas Substances 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속배선 제조방법에 관한 것으로, 반도체 기판 위에 절연막을 형성하고, 상기 절연막을 선택 식각하여 콘택 홀을 형성하는 공정과; 상기 콘택홀이 형성된 절연막 상에 제1구리 실리사이드막 및 구리막을 순차적으로 형성하는 공정과; 상기 구리막 상에 제2구리 실리사이드층을 형성하는 공정과; 상기 제2구리 실리사이드층과 구리막 및 제1구리 실리사이드층을 선택 식각하여 배선을 형성하는 공정 및; 상기 배선 측벽에 제3구리 실리사이드막을 형성하는 공정을 구비하여 반도체 소자의 배선을 제조하므로써, 1) 구리 배선의 장점인 낮은 저항(low resistivity)(알루미늄의 저항치;2.65μΩ㎝, 구리의 저항치;1.7μΩ㎝) 및 우수한 일렉트로마이그레이션 특성을 가질 수 있으며, 2) 낮은 내산화성 및 유전막과의 낮은 접촉특성 등을 향상시킬 수 있고, 3) 단결정 실리콘내에서의 빠른 확산율 특성을 저하시켜 소자의 특성을 향상시킬 수 있도록 한 고신뢰성의 배선 구조를 구현할 수 있게 된다.The present invention relates to a method for manufacturing a metal wiring of a semiconductor device, comprising: forming an insulating film on a semiconductor substrate, and selectively etching the insulating film to form contact holes; Sequentially forming a first copper silicide film and a copper film on the insulating film on which the contact hole is formed; Forming a second copper silicide layer on the copper film; Forming a wiring by selectively etching the second copper silicide layer, the copper film, and the first copper silicide layer; A process for forming a third copper silicide film on the sidewall of the wiring to produce a wiring of a semiconductor device, comprising: 1) low resistivity (resistance of aluminum; 2.65 µΩcm, resistance of copper; μΩ㎝) and excellent electromigration characteristics, 2) can improve the low oxidation resistance and low contact characteristics with the dielectric film, and 3) improve the characteristics of the device by reducing the fast diffusion rate characteristics in single crystal silicon A highly reliable wiring structure can be realized.
Description
제1(a)도 내지 제1(c)도는 종래 기술에 따른 반도체 소자의 알루미늄 배선구조 제조방법을 도시한 공정수순도.1 (a) to 1 (c) are process steps showing a method for manufacturing an aluminum wiring structure of a semiconductor device according to the prior art.
제2(a)도 내지 제2(e)도는 본 발명의 실시예 1에 따른 반도체 소자의 구리 실리사이드 배선구조 제조방법을 도시한 공정수순도.2 (a) to 2 (e) are process flowcharts showing a method for manufacturing a copper silicide wiring structure of a semiconductor device according to Embodiment 1 of the present invention.
제3(a)도 내지 제3(e)도는 본 발명의 실시예 2에 따른 반도체 소자의 구리 실리사이드 배선구조 제조방법을 도시한 공정수순도.3 (a) to 3 (e) are process flowcharts showing a method for manufacturing a copper silicide wiring structure of a semiconductor device according to Embodiment 2 of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 게이트 라인1 substrate 2 gate line
3 : 확산영역 4 : 비트 라인3: diffusion region 4: bit line
5 : 절연막 6 : 감광막5 insulating film 6 photosensitive film
10 : 제1 내지 제3 구리 실리사이드막 11 : 구리막10: first to third copper silicide film 11: copper film
본 발명은 반도체 소자의 금속배선 제조방법에 관한 것으로 특히, 장벽금속막과 보호막을 구리 실리사이드로 형성하여 고집적 소자에 적용가능한 배선구조를 갖는 반도체 소자의 배선 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing metal wiring of a semiconductor device, and more particularly, to a method for manufacturing wiring of a semiconductor device having a wiring structure applicable to a highly integrated device by forming a barrier metal film and a protective film with copper silicide.
종래 일반적으로 사용되어 오던 금속배선은 낮은 콘택(contact)저항 및 공정의 용이성으로 인해 알루미늄 배선구조가 주로 사용되어 왔으나 최근, 고집적 소자가 서브마이크론 지오메트리(submicron geometry)로 변화됨에 따라 접합 스파이크(junction spiking)나 일렉트로마이그레이션(electromigration) 문제, 그리고 배선길이 증가에 의한 낮은 저항의 요구 등과 같은 난관에 부딪혀 기존의 알루미늄 배선 사용에는 한계가 드러나고 있는 실정이다.Metal wiring, which has been generally used in the past, has been mainly used for aluminum wiring due to low contact resistance and ease of processing. However, in recent years, as the highly integrated device is changed to submicron geometry, junction spikes However, the use of aluminum wiring has become a limitation due to challenges such as), electromigration problems, and demand for low resistance due to increased wiring length.
이러한 요구에 부합하여 알루미늄 배선에 비해 낮은 저항을 가지면서도 일렉트로마이그레이션 특성이 우수한 구리 배선의 실용화가 요구되고 있다. 그러나, 상기 구리 배선의 경우 역시 낮은 내산화성과 실리콘 내부의 빠른 확산(diffusion)성 등으로 인해 그 실용화가 어려운 상태이다.In order to meet these demands, there is a need for the practical use of copper wiring having excellent resistance to electromigration while having lower resistance than aluminum wiring. However, the copper wiring is also difficult to be practical due to low oxidation resistance and rapid diffusion (diffusion) inside the silicon.
상기와 같은 기술적 결함을 염두에 두고, 기존 반도체 소자의 알루미늄 금속배선 제조방법과 구리 금속배선 제조방법 및 이에 따른 문제점들을 간략하게 살펴본다.With the above technical defects in mind, a brief description will be made of a method of manufacturing an aluminum metal wiring, a method of manufacturing a copper metal wiring, and problems thereof according to the existing semiconductor device.
먼저, 알루미늄 금속배선 제조공정을 설명한다. 상기 공정은 제1(a)도 내지 제1(c)도에 도시된 공정수순도에서 알 수 있듯이 제1공정으로서, 실리콘 기판(1) 상부에 게이트 전극용 금속을 증착하고 패터닝하여 게이트 라인(2)을 형성한 후, 상기 게이트 라인(2)이 형성된 기판 일측에 확산영역(n+또는 p+)(3)을 형성하고, 상기 확산영역(3) 및 게이트 라인(2)이 형성된 기판 상에 증착된 절연막(5) 내부에 게이트 라인(gate line)(2)과 서로 단차를 가지도록 비트 라인(bit line)(4)을 형성한 후, 전도층과 배선층을 접촉시키기 위해 감광막(photoresist) 패턴(6)을 마스크로 상기 절연막(5)을 선택적으로 제거하여 제1(a)도에 도시된 바와 같이 콘택 홀(contact hole)을 형성한다.First, an aluminum metal wiring manufacturing process will be described. The process is a first process, as can be seen from the process steps shown in FIGS. 1 (a) to 1 (c), and deposits and patterns a gate electrode metal on the silicon substrate 1 to form a gate line ( 2), a diffusion region (n + or p + ) 3 is formed on one side of the substrate on which the gate line 2 is formed, and on the substrate on which the diffusion region 3 and the gate line 2 are formed. After forming a bit line (4) to have a step with the gate line (2) in the insulating film (5) deposited on the photoresist (photoresist) to contact the conductive layer and the wiring layer The insulating film 5 is selectively removed using the pattern 6 as a mask to form a contact hole as shown in FIG. 1 (a).
그후 제2공정으로서, 상기 감광막 패턴(6)을 제거하고, 상기 실리콘 기판 상에 형성된 패턴의 노출된 전면이 포함되도록 밀착층/장벽층(7)을 순차적으로 증착한 후, 상기 콘택 홀 내부에 수소 환원법이나 SiH4환원법 등의 화학기상증착(chemical vapour deposition:이하 CVD라 한다)법을 이용하여 텅스텐막(8)을 증착하고, 이어서 상기 텅스텐을 에치백(etchback)하여 제1(b)도에 도시된 바와 같이 상기 콘택 홀 내부에만 텅스텐(8)이 남도록 패터닝한다. 이때 상기 밀착층은 Ti로 형성하고, 장벽층은 TiN 및, TiW 중 선택된 어느 하나를 이용하여 형성한다.Thereafter, as a second process, the photoresist pattern 6 is removed, and the adhesion layer / barrier layer 7 is sequentially deposited so as to include the exposed front surface of the pattern formed on the silicon substrate, and then into the contact hole. The tungsten film 8 is deposited by chemical vapor deposition (hereinafter referred to as CVD) method such as hydrogen reduction method or SiH 4 reduction method, and then the tungsten is etched back to obtain the first (b). As shown in FIG. 6, tungsten 8 remains in the contact hole only. In this case, the adhesion layer is formed of Ti, and the barrier layer is formed using any one selected from TiN and TiW.
여기서 상기 CVD법을 이용한 텅스텐 증착 공정은 경우에 따라 생략할 수도 있으며, 텅스텐막 증착 공정이 생략될 경우에는 텅스텐막의 에치백 공정 또한 생략한다.Here, the tungsten deposition process using the CVD method may be omitted in some cases, and when the tungsten film deposition process is omitted, the etch back process of the tungsten film is also omitted.
그 다음 제3공정으로서, 상기 패턴이 형성된 기판 전면이 도포되도록 알루미늄막(9)을 증착하고 감광막 패턴(6)을 마스크로 상기 알루미늄막(8) 및 밀착층/장벽층(7)을 선택적으로 식각하여 패터닝하므로써, 제1(c)도에 도시된 바와 같이 텅스텐 플러그(8)를 접촉하며 지나는 알루미늄 배선을 형성한다.Then, as a third process, an aluminum film 9 is deposited so that the entire surface of the substrate on which the pattern is formed is deposited, and the aluminum film 8 and the adhesion layer / barrier layer 7 are selectively subjected to the photoresist pattern 6 as a mask. By etching and patterning, as shown in FIG. 1 (c), aluminum wires passing through the tungsten plug 8 in contact with each other are formed.
다음으로 구리 금속배선 제조공정을 살펴본다. 상기 공정은 알루미늄 배선형성에서 언급된 제1공정까지는 동일하게 실시하고, 이후 CVD법이나 스퍼터링(sputtering)법, 혹은 스핀 코팅(spin coating)법 중 선택된 어느 하나를 이용하여 상기 콘택 홀이 형성된 기판 전 표면 상에 구리막을 증착한 후 감광막을 통한 마스킹(masking) 작업 및 에치(etch)작업을 실시하여 구리 배선을 형성한다.Next, look at the copper metallization manufacturing process. The process is performed in the same way up to the first process mentioned in forming the aluminum wiring, and then before the substrate on which the contact hole is formed by using any one selected from CVD, sputtering, or spin coating. After the copper film is deposited on the surface, a masking operation and an etching operation through the photosensitive film are performed to form a copper wiring.
그러나 이러한 일련의 제조공정을 거쳐 제조된 상기 알루미늄 및 구리 배선 구조는 그 각각의 취약점에 의해 알루미늄 배선을 사용할 경우에는 소자가 고집직화 됨에 따라 요구되는 낮은 저항과 일렉트로마이그레이션 특성을 만족시킬 수 없다는 단점을 가지게 되고, 구리 배선을 사용할 경우에는 구리의 낮은 내산화성으로 인해 후속 공정 진행시 구리가 산화되어 순수(pure) 구리에 비해 저항이 크게 올라가므로 저항치가 알루미늄 배선과 차이가 없거나 혹은 더 높은 값을 가지게 되는 문제점이 야기되며, 또한 구리의 경우는 단결정 실리콘 내에서의 확산율(diffusion rate)이 빨라 소자의 특성을 저하시키는 단점을 가지게 된다.However, the aluminum and copper wiring structures manufactured through such a series of manufacturing processes have disadvantages in that they cannot satisfy the low resistance and electromigration characteristics required as the device is highly integrated due to its weakness. In the case of using copper wiring, the resistance of the copper wiring is higher than that of pure copper because the copper is oxidized in the subsequent process due to the low oxidation resistance of the copper, so that the resistance is not different from that of the aluminum wiring or has a higher value. In addition, in the case of copper, the diffusion rate in the single crystal silicon is high, resulting in a deterioration of device characteristics.
이에 본 발명은 상기와 같은 단점을 개선하기 위하여 이루어진 것으로 구리가 구리 실리사이드막에 의해 둘러싸인 형상을 갖도록 배선을 형성하므로써, 단결정 실리콘내로의 빠른 확산을 방지함과 동시에 낮은 저항과 우수한 일렉트로마이그레이션 특성을 살리면서도 구리의 낮은 내화성을 향상시킬 수 있도록 한 반도체 소자의 금속배선 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to improve the above disadvantages, and by forming the wiring so that copper has a shape surrounded by a copper silicide film, it prevents rapid diffusion into single crystal silicon and at the same time utilizes low resistance and excellent electromigration characteristics. It is an object of the present invention to provide a method for manufacturing a metal wiring of a semiconductor device that can improve the low fire resistance of copper.
상기와 같은 목적을 달성하기 위한 본 발명의 실시예 1에 따른 반도체 소자의 배선 제조방법은 반도체 기판 위에 절연막을 형성하고, 상기 절연막을 선택 식각하여 콘택 홀을 형성하는 공정과; 상기 콘택 홀이 형성된 절연막 상에 제1구리 실리사이드막 및 구리막을 순차적으로 형성하는 공정과; 상기 구리막 상에 제2구리 실리사이드층을 형성하는 공정과; 상기 제2구리 실리사이드층과 구리막 및 제1구리 실리사이드층을 선택 식각하여 배선을 형성하는 공정 및; 상기 배선 측벽에 제3구리 실리사이드막을 형성하는 공정을 구비하여 이루어진다.In accordance with another aspect of the present invention, there is provided a method of manufacturing a wiring of a semiconductor device, the method including forming an insulating film on a semiconductor substrate and selectively etching the insulating film to form a contact hole; Sequentially forming a first copper silicide film and a copper film on the insulating film on which the contact hole is formed; Forming a second copper silicide layer on the copper film; Forming a wiring by selectively etching the second copper silicide layer, the copper film, and the first copper silicide layer; And forming a third copper silicide film on the wiring sidewalls.
한편, 상기와 같은 목적을 달성하기 위한 본 발명의 실시예 2에 따른 반도체 소자의 배선 제조방법은 반도체 기판 위에 절연막을 형성하고, 상기 절연막을 선택 식각하여 콘택 홀을 형성하는 공정과; 상기 콘택홀이 형성된 절연막 상에 제1구리 실리사이드막 및 구리막을 순차적으로 형성하는 공정과; 상기 구리막 및 제1구리 실리사이드층을 선택 식각하여 배선을 형성하는 공정 및; 상기 배선 상부면과 측벽에 제2구리 실리사이드막을 형성하는 공정을 포함하여 이루어진다.On the other hand, the semiconductor device wiring manufacturing method according to the second embodiment of the present invention for achieving the above object comprises the steps of forming an insulating film on the semiconductor substrate, and selectively etching the insulating film to form a contact hole; Sequentially forming a first copper silicide film and a copper film on the insulating film on which the contact hole is formed; Selectively etching the copper film and the first copper silicide layer to form a wire; And forming a second copper silicide film on the upper surface and the sidewall of the wiring.
상기 공정 결과, 반도체 소자의 특성을 향상시킬 수 있게 된다.As a result of the above process, the characteristics of the semiconductor element can be improved.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
본 발명은 구리 배선의 정점인 낮은 저항과 우수한 일렉트로마이그레이션 특성을 살리면서도, 단점인 실리콘 내에서의 빠른 확산성을 막고 구리의 낮은 내산화성 문제를 제거하기 위하여 구리막을 사이에 두고 장벽금속막 및 보호막(capping layer)을 구리 실리사이드로 형성한 후 이를 패터닝하여 구리 실리사이드 배선을 형성한데 주안점을 둔 것으로, 이점에 착안하여 각 실시예에 따른 제조공정을 구체적으로 살펴본다.The present invention provides a barrier metal film and a protective film with a copper film interposed therebetween in order to prevent the low diffusion resistance in silicon and to prevent the problem of low oxidation resistance of copper while utilizing the low resistance and excellent electromigration characteristics of the copper wiring. (capping layer) is formed of copper silicide and then patterned to form a copper silicide interconnection. The main focus is on the manufacturing process according to each embodiment.
먼저, 제2(a)도 내지 제2(e)도 도시된 본 발명의 실시예 1에 따른 반도체 소자의 구리 실리사이드 배선구조 제조방법을 도시한 공정 수순도를 이용하여 그 제조공정을 설명한다.First, the manufacturing process will be described using the process flowchart showing the method for manufacturing the copper silicide wiring structure of the semiconductor device according to the first embodiment of the present invention shown in FIGS. 2 (a) to 2 (e).
상기 공정수순도에서 알 수 있듯이 제1공정으로서, 제2(a)도에 도시된 공정은 종래와 동일하므로 확산영역(3)과 게이트 라인(2) 및 비트 라인(4)의 표면이 드러나도록 선택적으로 제거하여 콘택 홀을 형성하는 공정에 대한 세부적인 설명은 생략한다.As can be seen from the process flow chart, as the first process, the process shown in FIG. 2 (a) is the same as the conventional process so that the surfaces of the diffusion region 3, the gate line 2 and the bit line 4 are exposed. Detailed description of the process of selectively removing and forming the contact hole will be omitted.
그후 제2공정으로서, 제2(b)도에 도시된 바와 같이 절연막(5) 상에 형성되어 있는 감광막 패턴(6)을 제거하고, 상기 실리콘 기판(1) 상에 형성된 패턴의 노출된 전면이 포함되도록 구리 실리사이드로 이루어진 장벽금속막(10)을 형성한다.Thereafter, as a second process, as shown in FIG. 2 (b), the photosensitive film pattern 6 formed on the insulating film 5 is removed, and the exposed entire surface of the pattern formed on the silicon substrate 1 is removed. A barrier metal film 10 made of copper silicide is formed to be included.
여기서 상기 구리 실리사이드(10)는 스퍼터링법에 의해 직접 형성될 수도 있고, 구리 형성 후 실리콘 이온주입(ion implant) 및 어닐(anneal)공정에 의해 형성될 수도 있으며, 또는 구리 형성 후 ECR(electron cyclotron resonance:이하, ECR이라 한다)을 이용한 실리콘 밤버드먼트(bombardment) 및 어닐공정에 의해 형성될 수도 있고, 이외의 방법으로 구리 형성 후 희석된 SiH4또는 Si2H6가스 분위기에서의 어닐공정에 의해서도 형성될 수 있다.Here, the copper silicide 10 may be directly formed by sputtering, or may be formed by silicon ion implantation and annealing after copper formation, or after electron formation, electron cyclotron resonance It may be formed by a silicon bombardment (annealed as ECR) and an annealing process, also by an annealing process in a SiH 4 or Si 2 H 6 gas atmosphere diluted after copper formation by other methods Can be formed.
이때 상기 구리는 CVD법, 스퍼터링법 및, 스핀코팅법 중 선택된 어느 하나를 이용하여 증착하고, 상기 실리콘 이온주입 후 실시되는 어닐공정은 600℃ 이하에서 2시간 이하로 N2, Ar 및, He 분위기 중 선택된 어느 하나를 이용하여 실시되며, 실리콘 이온주입시 필요로되는 에너지는 형성하고자 하는 장벽금속의 두께에 따라 조정되고, 도우스(dose)는 1*1014ions/㎠이다.At this time, the copper is deposited using any one selected from CVD method, sputtering method, and spin coating method, and the annealing process performed after the silicon ion implantation is performed under N 2 , Ar, and He atmosphere at 600 ° C. or less for 2 hours. It is carried out using any one selected from among, the energy required for silicon ion implantation is adjusted according to the thickness of the barrier metal to be formed, the dose is 1 * 10 14 ions / ㎠.
한편, ECR을 이용한 실리콘 밤버드먼트(bombardment) 및 어닐공정에 의해 상기 구리 실리사이드를 형성할 시에는 먼저, 300℃ 이하의 온도에서 N2나 Ar 또는 He으로 희석된 SiH4또는 Si2H6가스나, 혹은 100%의 SiH4나 Si2H6가스 중 선택된 어느 하나를 이용하여 500watt 이하의 전력으로 공정을 진행하고, 이후의 어닐공정은 이온주입후 실시되는 어닐공정과 동일한 방법으로 실시하되, 여기서는 상기 어닐공정은 생략해도 무방하다.On the other hand, when the copper silicide is formed by silicon bombardment and annealing process using ECR, first, SiH 4 or Si 2 H 6 gas diluted with N 2 , Ar, or He at a temperature of 300 ° C. or less; B or 100% of SiH 4 or Si 2 H 6 gas using any one selected from the process to the power of less than 500watts, the subsequent annealing process is carried out in the same manner as the annealing process carried out after ion implantation, The annealing step may be omitted here.
그 결과, 단결성 실리콘내에서의 구리의 빠른 확산율 특성을 상기 장벽금속을 이용하여 저하시킬 수 있게 된다.As a result, the fast diffusion rate characteristic of copper in unitary silicon can be reduced by using the barrier metal.
이어서 제3공정으로서, 제2(c)도에 도시된 바와 같이 사이 장벽금속막(10) 상에 화학기상증착법, 스퍼터링법, 또는 스핀코팅법 중 선택된 어느 한 방법을 이용하여 구리막(11)을 형성하고, 상기 구리막(11) 상에 다시 제2공정에서 언급된 방법과 동일하게 보호막인 구리 실리사이드막(10)을 형성한다.Subsequently, as a third process, as shown in FIG. 2 (c), the copper film 11 is formed by using any one of chemical vapor deposition, sputtering, or spin coating on the barrier metal film 10. The copper silicide film 10, which is a protective film, is formed on the copper film 11 in the same manner as in the second process.
그 다음 제4공정으로서, 제2(d)도에 도시된 바와 같이 상기 구리 실리사이드막(10) 상에 패터닝된 감광막 패턴(6)을 마스크로 상기 구리 실리사이드막(10)과 구리막(11) 및 장벽금속막(10)을 식각하여 배선을 형성한다.Next, as a fourth process, the copper silicide film 10 and the copper film 11 using the photosensitive film pattern 6 patterned on the copper silicide film 10 as a mask as shown in FIG. And the barrier metal film 10 is etched to form wiring.
마지막으로 제5공정으로서, 제2(e)도에 도시된 바와 같이 상기 감광막 패턴(6)을 제거하고, 실리콘 이온주입 후 어닐처리하는 방법이나 ECR을 이용한 실리콘 이온 밤버드먼트 후 어닐처리하는 방법, 희석된 SiH4가스나 Si2H6가스 분위기에서 어닐처리하는 방법 중 선택된 어느 하나를 이용하여 상기 배선 측면을 실리사이드화 하거나, 또는 배선이 형성된 상기 절연막(5) 전면 상에 스퍼터링법으로 구리 실리사이드막을 형성한 후 에치백하여 구리 실리사이드 사이드웰(sidewall)을 형성하므로써 본 공정을 완료한다.Finally, as a fifth process, as shown in FIG. 2 (e), the photoresist pattern 6 is removed, and annealing after silicon ion implantation or annealing after silicon ion bombardment using ECR. Or silicide the side surface of the wiring using any one of a method of annealing in a dilute SiH 4 gas or Si 2 H 6 gas atmosphere, or copper silicide by sputtering on the entire surface of the insulating film 5 on which the wiring is formed. After the film is formed, the process is etched back to form a copper silicide sidewall.
그 결과, 상기 구리막 패턴(11)이 구리 실리사이드에 의해 둘러싸이는 형상으로 이루어진 구리 실리사이드 배선 구조를 가지게 되므로, 기존 구리 배선 구조에서 문제시 되어 오던 낮은 내산화성 문제를 해결할 수 있게 되는 것이다.As a result, since the copper film pattern 11 has a copper silicide wiring structure formed in a shape surrounded by copper silicide, it is possible to solve the low oxidation resistance problem that has been a problem in the existing copper wiring structure.
다음으로, 제3(a)도 내지 제3(e)도에 도시된 본 발명의 실시예 2에 따른 반도체 소자의 배선구조 제조방법을 도시한 공정수순도를 이용하여 그 제조공정을 설명한다.Next, the manufacturing process will be described using the process flowchart showing the wiring structure manufacturing method of the semiconductor device according to the second embodiment of the present invention shown in FIGS. 3 (a) to 3 (e).
상기 실시예는 상기 도면에서 알 수 있듯이 실시예 1와 비교했을 때 그 기본 구조는 동일하나 제조공정 상에 다소 차이가 있는 것으로, 상기 도면을 참조하여 그 제조공정을 살펴보면 아래와 같다.As can be seen from the drawing, the basic structure is the same as that of Example 1, but the manufacturing process is slightly different. Referring to the drawing, the manufacturing process is as follows.
여기서, 제3(a)도 내지 제3(c)도에 도시된 제1 내지 제3공정은 실시예 1에서 언급된 공정과 동일하게 진행되므로 설명을 생략한다.Here, since the first to third processes shown in FIGS. 3 (a) to 3 (c) are performed in the same manner as those described in Example 1, description thereof is omitted.
이후 제4공정으로서, 제3(d)도에 도시된 바와 같이 구리 실리사이드막으로 이루어진 장벽금속막(10) 위에 형성되어 있는 구리막(11) 상에 패터닝된 감광막 패턴(6)을 마스크로 상기 구리막(11) 및 구리 실리사이드막(10)을 식각하여 배선을 형성한다.Thereafter, as a fourth process, the photosensitive film pattern 6 patterned on the copper film 11 formed on the barrier metal film 10 made of a copper silicide film as shown in FIG. The copper film 11 and the copper silicide film 10 are etched to form wiring.
그 다음 제5공정으로서, 제3(e)도에 도시된 바와 같이 상기 감광막 패턴(6)을 제거하고, 실리콘 이온주입 후 어닐처리하는 방법, ECR을 이용한 실리콘 이온 밤버드먼트 후 어닐처리하는 방법, 희석된 SiH4가스나 Si2H6가스 분위기에서 어닐처리하는 방법 중 선택된 어느 하나를 이용하여 상기 구리 배선의 상부면과 측면을 모두 실리사이드화하여 본 공정을 완료한다.Next, as a fifth process, as shown in FIG. 3 (e), the photosensitive film pattern 6 is removed, and annealing after silicon ion implantation is performed, and annealing after silicon ion bombardment using ECR. This process is completed by silicidating both the upper and side surfaces of the copper wiring using any one of a method of annealing in a dilute SiH 4 gas or Si 2 H 6 gas atmosphere.
상술한 바와 같이 본 발명에 의하면, 1) 구리 배선의 장점인 낮은 저항(low resistivity)(알루미늄의 저항치;2.65μΩ㎝, 구리의 저항치;1.7μΩ㎝) 및 우수한 일렉트로마이그레이션 특성을 가질 수 있으며, 2) 낮은 내산화성 및 유전막과의 낮은 접촉특성 등을 향상시킬 수 있고, 3) 단결정 실리콘내에서의 빠른 확산율 특성을 저하시켜 소자의 특성을 향상시킬 수 있는 고신뢰성의 배선 구조를 구현할 수 있게 된다.As described above, according to the present invention, 1) low resistivity (resistance of aluminum; 2.65 µΩcm, resistivity of copper; 1.7 µΩcm), which is an advantage of copper wiring, and excellent electromigration characteristics, 2 Low oxidation resistance and low contact characteristics with the dielectric film can be improved, and 3) high reliability wiring structure that can improve the characteristics of the device can be realized by lowering the fast diffusion rate property in the single crystal silicon.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950008643A KR0157876B1 (en) | 1995-04-13 | 1995-04-13 | Method of fabricating wire of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950008643A KR0157876B1 (en) | 1995-04-13 | 1995-04-13 | Method of fabricating wire of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR960039202A KR960039202A (en) | 1996-11-21 |
| KR0157876B1 true KR0157876B1 (en) | 1999-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950008643A Expired - Fee Related KR0157876B1 (en) | 1995-04-13 | 1995-04-13 | Method of fabricating wire of semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR0157876B1 (en) |
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| KR960039202A (en) | 1996-11-21 |
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