KR0157294B1 - Pumping voltage generating circuit - Google Patents

Abstract

[Technical field to which the invention described in the claims belongs]

The present invention relates to a pumping voltage generation circuit of a semiconductor memory device for generating a pumping voltage boosted to a level higher than an operating power supply voltage inside the semiconductor memory device.

[Technical Challenges to Invent]

In a conventional semiconductor memory device, when the power supply voltage VCC is 2 volts or more, it is not difficult to make 2 VCC into VCC + 1.5 volts. However, it is not very easy to make 2 VCC into VCC + 1.5 volts with a low supply voltage of less than 1.5 volts. Accordingly, it is a problem of the present invention to output a voltage level that is elevated in a low power supply state.

[Summary of the solution of the invention]

Precharge means for precharging a predetermined first node to a power supply voltage level in an initial state, and a first step of boosting the voltage level of the first node to a predetermined first voltage level in response to the predetermined first clock signal; A boosting means, first transmission means for selectively connecting the first node and the predetermined second node in response to a predetermined second clock signal, and selectively controlling the transmission of the voltage to the second node by one node; Second boosting means for boosting the voltage level of the second node to a predetermined second voltage level in response to a third clock signal; and a second voltage level of the second node in response to a predetermined fourth clock signal. The above object is achieved by implementing a pumping voltage generation circuit of a semiconductor memory device, characterized in that it comprises a second transfer means for transmitting the output to the output terminal.

[Important Uses of the Invention]

A semiconductor memory device that outputs a desired pumping voltage at a low power supply voltage.

Description

Pumping voltage generating circuit

1 is a circuit diagram of a pumping voltage generation circuit according to the prior art.

2 is a circuit diagram of a pumping voltage generating circuit according to the present invention.

3 is an operation timing diagram according to FIG.

The present invention relates to a semiconductor memory device, and more particularly, to a pumping device generating circuit of a semiconductor memory device for generating a pumping voltage boosted to a level higher than an operating power supply voltage inside the semiconductor memory device.

A semiconductor memory device such as a DRAM is composed of a memory cell array storing data and peripheral circuit diagrams for accessing data stored in the memory cell array. The memory cell array is a collection of unit memory cells. In the DRAM, the unit memory cell includes one storage capacitor and one access transistor. The control electrode of the access transistor is connected to a word line. In general, the control electrode of the access transistor requires a voltage level higher than the operating power supply voltage VCC in the memory device. To prevent it. In addition, in the semiconductor memory device, a pumping voltage voltage boosted higher than the power supply voltage is required for various reasons. Therefore, it is common to mount a pumping voltage generation circuit that inputs an operating power supply voltage and boosts the voltage high.

1 is a circuit diagram of a pumping voltage generation circuit according to the prior art.

Referring to FIG. 1, the oscillation circuit 2 is commonly connected with the input terminals of the inverters 4, 8. The output terminals of the inverters 4, 8 are connected to the input terminals of the inverters 6, 10, respectively. The output ends of the inverters 6, 10 are connected to one ends of the capacitors 12, 14. The other ends of the capacitors 12 and 14 are connected to the channel end and the gate terminal of the NMOS transistor 16, respectively. The pumping voltage VPP1 is output to the other end of the channel of the NMOS transistor 16.

Note that in FIG. 1, precharge means for precharging nodes Na and Nb are omitted.

In the conventional circuit of FIG. 1, node Na is precharged to the power supply voltage VCC level, and node Nb is precharged to 2VCC. In this structure, the maximum value of the pumping voltage VPP1 level is 2VCC. The voltage level delivered to the gate of the access transistor that controls the input and output of data in the DRAM must be at least VCC + 1.5 volts. If VCC is more than 2 volts, it is not difficult to make 2 VCC into VCC + 1.5 volts. However, when VCC is below 1.5 volts, it is not easy to make 2VCC into VCC + 1.5 volts.

Accordingly, in order to achieve the object of the present invention, there is provided a pumping voltage generation circuit of a semiconductor memory device which easily outputs a voltage level boosted in the semiconductor memory device according to the present invention.

In order to achieve the object of the present invention, the pumping voltage generation circuit of the semiconductor memory device according to the present invention,

Precharge means for precharging a predetermined first node to a power supply voltage level in an initial state;

First boosting means for boosting the voltage level of the first node to a predetermined first voltage level in response to a predetermined first clock signal;

First transmission means for selectively controlling the transfer of the voltage to the second node by the first node and selectively to the first node and the predetermined second node in response to a predetermined second clock signal;

Second boosting means for boosting the voltage level of the second node to a predetermined second voltage level in response to a predetermined third clock signal;

And second transmission means for transmitting a second voltage level of the second node to an output terminal in response to a predetermined fourth clock signal.

Hereinafter, a preferred embodiment of a pumping voltage generation circuit of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram of a pumping voltage generation circuit according to an embodiment of the present invention.

Referring to FIG. 2, the first clock A is commonly connected to an input terminal of the inverter 32 and one end of the capacitor 22. An output terminal of the inverter 32 is connected to one end of the capacitor 34, and the other end of the capacitor 22 is an NMOS transistor in which a source terminal and a drain of the diode-connected enMOS transistor 24 are connected to a power supply voltage terminal. Commonly connected to the gate terminal of (26). The other end of the capacitor 34 and the source of the enMOS transistor 26 are commonly connected to a predetermined first node N1. In the NMOS transistor 28, both ends of the channel are connected in parallel to both ends of the channel of the NMOS transistor 26, and a gate thereof is diode-connected to the power supply voltage terminal. The pre-charge means for precharging the first node N1 from the initial state to the power supply voltage level is organically connected to the NMOS transistor 24 and the NMOS transistors 26 and 28 which are diode-connected with the capacitor 22. to be. In addition, the inverter 32 and the capacitor 34 are organically connected and are a circuit for pumping the first node N1 voltage in response to the first clock A. FIG. On the other hand, the node N1 is connected to the source of the PMOS transistor 36, the gate of the PMOS transistor 36 is connected to the first clock B, the drain is connected to the predetermined second node N2. The third clock C is connected to the input terminal of the inverter 42, and the output terminal of the inverter 42 is connected to one end of the capacitor 44. The other end of the capacitor 44 is connected to the second node N2. The PMOS transistor 36 performs a transfer role for selectively transferring the charge of the node N1 to the second node N2. In addition, the inverter 42 and the capacitor 44 serve to pump the voltage level of the node N2. The PMOS transistor 46 has a fourth clock D connected to its gate, a source connected to the second node N2, and a drain output line. The pumping voltage VPP2 is output to the output line. The PMOS transistor 46 transfers the charge of the node N2 to an output line. A well bias voltage is connected to the substrates of the PMOS transistors 36 and 46.

3 is an operation timing diagram according to FIG. 2.

In the initial state, the node Np is charged to VCC-Vtn1 (where Vtn1 is the threshold voltage of the NMOS transistor 24) by the voltage power transmitted through the diode-connected NMOS transistor 24. Since this is VCC, the node Np becomes 2VCC-Vtn1 level. Accordingly, the NMOS transistor 26 is turned on and the node N1 is precharged to the VCC level. In this state, since the PMOS transistor 36 is turned on, the node N2 is also precharged to the VCC level. As the clock A changes to the VCC level, the node N1 is pumped to the 2 VCC level by the operation of the inverter 32 and the capacitor 34. Since the PMOS transistor 36 is turned on, the 2 VCC level of the node N1 is turned on. Is 1.5 VCC level due to the charge sharing operation of the node N1 and the node N2. Here, as the clock B is boosted to the VPP level, the PMOS transistor 36 is turned off. At this time, the clock C is converted from the VCC level to the VSS level, so that the voltage level of the node N2 is pumped to the 2.5VCC level. The voltage of the node N2 is transmitted to the output line through the PMOS transistor 46 as the clock D is converted from the VPP level to the VSS level. VPP2 is the pumping voltage according to the present invention output in FIG.

As a result, the first pumping through the capacitor 34 and the second pumping through the capacitor 44 allow the pump to be sufficiently pumped at a low power supply voltage to obtain a desired voltage level. In this case, the reason why the well bias of the PMOS transistors 36 and 46 uses VPPW higher than the pumping voltage VPP is that a positive bias is applied between the node N2 and the well of the PMOS transistors, causing a latch-up problem. It is to prevent that. Details thereof are disclosed in Korean Patent Application No. 93-23697 filed by the applicant. The PMOS transistors 36 and 46 configured as the transmission means generate an effect of suppressing a voltage drop when transferring a charge.

By implementing the pumping voltage generation circuit as described above, it is possible to effectively obtain the desired voltage level at the low voltage voltage that has been a problem in the prior art.

Claims (5)

A pumping voltage generation circuit of a semiconductor memory device, comprising: precharge means for precharging a predetermined first node to a power supply voltage level in an initial state, and a voltage level of the first node in response to a predetermined first clock signal. First boosting means for boosting to a predetermined first voltage level, and selectively connecting the first node to a predetermined second node in response to the predetermined second clock signal to transfer the voltage of the first node to the second node; First transmission means for selectively controlling transmission, second boosting means for secondly boosting the voltage level of the second node to a predetermined second voltage level in response to a predetermined third clock signal, and a predetermined fourth And a second transmission means for transmitting a second voltage level of the second node to an output terminal in response to a clock signal. The pumping voltage generation circuit of claim 1, wherein the first voltage level is 1.5 times a power supply voltage level. 2. The pumping voltage generation circuit of claim 1, wherein the second voltage level is 2.5 times the power supply voltage level. The pumping voltage generation circuit of a semiconductor memory device according to claim 1, wherein the first transfer means and the second transfer means are pio transistors, respectively. The pumping voltage generation circuit of claim 4, wherein a voltage higher than a predetermined boost voltage is applied to the PMOS transistor as a well bias.