KR0155262B1 - Multi-channel serial processing apparatus - Google Patents

Abstract

According to the present invention, a multi-channel serial processing apparatus reduces the amount of hardware and time delay between channels by actually processing the multi-channel voice data in a muse audio decoder without separating the voice data of each channel. In the related art, since the conventional multichannel parallel processing apparatus performs parallel processing of the same process for multiple channels, the timing relationship has to be considered in order to increase the amount of hardware and to have a phase relationship between each channel. Therefore, in the present invention, the error correction unit 100 processes the separated region bits in a channel order at a constant speed and performs an error correction operation, and a word d sequentially rearranging the sample order for each channel with respect to the separated voice data. By including the interleave unit 200, a quasi-temporal demodulation unit 300 for receiving the area bits and voice data to restore the original voice data, and a channel multiple unit 400 for separating and multiplexing the restored voice data by channel Compared with the conventional parallel processing, the amount of hardware can be greatly reduced, and there is no need to worry about the timing relationship between channels.

Description

Multichannel Serial Processing Unit

1 is a block diagram of a multi-channel parallel processing apparatus according to the prior art.

2 is a block diagram of a multi-channel serial processing apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

100: error correction 110: demultiplexer

120: address counter 130: where address

140: buffer memory 150: error correction ROM

200: word deinterleave unit 210: address counter

220: address ROM 230: buffer memory

300: quasi-instantaneous demodulation unit 310: data extension ROM

320: adder 330: 3 sample delay

340: Incomplete Integrator 400: Channel Multiple

410,420,430,440: latches 450,460; inverter

The present invention relates to a multi-channel serial processing apparatus, and in particular, in processing a multi-channel voice data in a MUSE voice decoder, the amount of hardware required for the actual configuration by serial processing without separating the voice data of each channel. And a multi-channel serial processing apparatus for reducing time delay between channels.

A conventional multichannel parallel processing apparatus has a demultiplexer 10, error correction stages 20a, 30a, 40a, 50a, and word deinterleave stages 20b, as shown in FIG. 30b, 40b, 50b), compressed DPCM decoder stages (60a, 60b, 70a, 70b), and channel multiplexers (80, 90) for voice data and area bits of four channels (CH1, CH2, CH3, CH4). By separating, four parallel channels (CH1, CH2, CH3, and CH4) are processed in parallel, so that the amount of hardware is increased. In addition, there is a problem in that the timing relationship must be considered in order to make the phase relationship between the channels CH1, CH2, CH3, and CH4 equal.

Therefore, the present invention was created to solve the above problems, and in the muse speech decoder, four channels are separated and serially processed in one pass instead of parallel signal processing, thereby reducing the overall amount of hardware and being considered in parallel processing. It is an object of the present invention to provide a multi-channel serial processing apparatus that can eliminate the time delay between channels.

In order to achieve the above object, the present invention provides an error correction unit for processing the region bits separated from the format of the input mute voice data at a constant speed and performing an error correction operation, and in the format of the input mute voice data. The word deinterleave unit sequentially rearranges the sample order for the separated voice data for each channel, and receives the area bits and the voice data transmitted from the error correction unit and the word deinterleave unit, respectively, and restores the original voice data. A quasi-instantaneous demodulation unit and a channel multiple unit for separating and multiplexing the voice data restored in the quasi-instantaneous demodulation unit for each channel.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a multi-channel serial processing apparatus according to the present invention.

Referring to FIG. 2, the error correction unit 100 includes a demultiplexer 110 that separates an area bit and voice data in a format of an input muse voice data, an address counter 120 for generating an address, and an address counter 120. In the buffer memory 140 and the buffer memory 140 buffering the area bits separated by the demultiplexer 110 in accordance with the address stored in the address ROM 130 and the address stored in the address ROM 130; An error correction ROM 150 that performs error correction on the output region bits.

The word deinterleave unit 200 addresses the address counter 210 for supplying the linear address, the address ROM 220 for storing the linear address supplied from the address counter 210, and the voice data transmitted from the demultiplexer 110. A buffer memory 230 is buffered according to the address output from the ROM 220.

The quasi-instantaneous demodulation unit 300 receives data output from the buffer memory 140 of the error correcting unit 100 and the buffer memory 230 of the word deinterleave unit 200 and outputs a 15-bit extended voice data. ROM 310, an adder 320 for restoring the voice data transmitted from the data extension ROM 310 to the original data, and a three sample delayer 330 for delaying the sample added by the adder 320 by three samples. And an incomplete integral counter 340 for multiplying the incomplete integral coefficient α by the three sample delayed data by the three sample delay unit 330 and transmitting it to one end of the adder 320.

The channel multiplexer 400 includes latches 410 and 420 for separating voice data transmitted from the adder 320 of the quasi-instantaneous demodulator 300 into 1, 2, 3, and 4 channels using a 2sf clock. The latches 430 and 440 for multiplexing the channel data transmitted from the latches 410 and 420 using sf clocks, and the inverters 450 and 460 for applying a clock signal to the latches 410, 420, 430 and 440. Equipped.

The present invention having the configuration as described above will be described in more detail as follows.

The demultiplexer 110 of the error correction unit 100 separates the region bits and the multiplexed speech data in the format of the muse speech data input through the input terminal IN. At this time, the order of the separated audio data is expressed as Dij (i: channel, j: sample order) as shown in Table 1 below.

The area bits are input to the error correction ROM 150 at a rate of 4 sf (sampling frequency) in the order of 1, 3, 2, and 4 channels through the buffer memory 140 of the error correction unit 100. At this time, the address counter 120 generates an address for accessing the address ROM 130 and uses a clock generated at the position of every area bit when writing the buffer memory 140. At the time of reading the buffer memory 140, 4sf is the clock. The address ROM 130 generates linear addresses from 0 to 28 during the write operation of the buffer memory 140, and 1, 2, 4, 6, 8, 10, 12 during the read operation of the buffer memory 140. Addresses are output in the order of 1, 3, 5, 7, 9, 11, 13, 14, 16, 18, 20, 22, 24 26, 15, 17, 19, 21, 23, 25, 27.

The error correction ROM 150 receives the area bits transmitted from the buffer memory 140, performs error correction, and outputs three-bit area bits.

Meanwhile, the word deinterleave unit 200 including the address counter 210, the address ROM 220, and the buffer memory 230 performs a word deinterleave operation on voice data. The word deinterleave sequentially rearranges the sample order for each channel. The channel order output through the buffer memory 230 is in the order of channels 1, 3, 2, and 4, and the actual sample order is shown in Table 2 below.

The address counter 210 supplies a linear address for accessing the address ROM 220, and uses a clock for extracting an audio sample from a voice data format during memory writing. When reading the memory, address counting from 0 to 127 is performed using 4sf as the clock. The address ROM 220 generates input / output addresses of the buffer memory 230, and generates serial addresses from 0 to 127 during memory writing. In addition, during memory reading, addresses are generated in the order shown in Table 3 below.

Meanwhile, the area bits (3 bits) and the voice data (8 bits) transmitted from the error correction unit 100 and the word deinterleave unit 200, respectively, are 15 bits in the data extension ROM 310 of the quasi-temporal demodulation unit 300. It is output as the expanded voice data of. Since the muse speech data input to the multiplexer 110 is differential data, the adder 320 of the quasi-temporal demodulator 30 continuously accumulates and restores the original data. In this case, since the order of the voice data input to the adder 320 is 1, 3, 2, and 4 channels, the 3 sample delay, not the sample delay, is performed by the 3 sample delay unit 330 for the voice data added and returned. The incomplete integral counter 340 transmits. The incomplete integral counter 340 multiplies the incomplete integral coefficient α by the three sample delayed speech data transmitted from the three sample delay unit 330 and sends the multiplier to the adder 320.

On the other hand, in the latches 410 and 420 of the channel multiple 400, 2sf is used as a clock to separate voice data of 1, 2 and 3 and 4 channels and transmit them to the latches 430 and 440, respectively. The latch 430 into which the voice data of one or two channels are input is clicked on the 2sf inverted by the inverter 450, and multiplexes the voice data of the one and two channels in one sf to the output terminal OUT1. In addition, the latch 440 to which the voice data of three or four channels are input is multiplexed to the output terminal OUT2 by multiplexing the voice data of the three and four channels by applying a clock of 2sf inverted by the inverter 450. In this case, 460 is an inverter for inverting sf.

As described above, according to the present invention, serial processing of multi-channel voice data can bring about a significant reduction in the amount of hardware compared to conventional parallel processing, and there is no need to worry about the timing relationship between channels.

Claims (5)

The error correction unit 100 processes the area bits separated from the format of the input muse voice data at a constant speed and performs an error correction operation, and each of the voice data separated from the format of the input muse voice data. The word deinterleave unit 200 sequentially rearranges the sample order for each channel, and receives the region bits and the voice data transmitted from the error correcting unit 100 and the word deinterleave unit 200 as original voice data. And a multi-channel demodulation unit (300) for restoring the quasi-instantaneous demodulation unit (300) and the multiplexed audio data restored by the quasi-instantaneous demodulation unit (300) for each channel. The method of claim 1, wherein the error correction unit transmits the demultiplexer 110 for separating the area bits and the voice data in the format of the input mute voice data, the address counter 120 for generating an address, and the address counter 120. An address ROM 130 for storing an address, a buffer memory 140 for buffering the region bits separated from the demultiplexer 110 according to the address stored in the address ROM 130, and an output from the buffer memory 140. And an error correction ROM (150) for performing error correction of the area bits. The word deinterleave unit 200 includes an address counter 210 for supplying a linear address, an address ROM 220 for storing a linear address supplied from the address counter 210, and a demultiplexer (2). And a buffer memory (230) for buffering voice data transmitted from 110 according to an address output from the address ROM (220). The speech data of claim 1, wherein the quasi-instantaneous demodulation unit 300 receives the output signals of the buffer memory 140 of the error correcting unit 100 and the buffer memory 230 of the word deinterleave unit 200. A three-sample delay for the data extension ROM 310 for outputting the data, an adder 320 for restoring the voice data transmitted from the data extension ROM 310 to the original data, and the data added by the adder 320; A three-sample delay unit 330 and an incomplete integral coefficient unit 340 for multiplying the three-sample delayed data by the three-sample delay unit 330 by the incomplete integral coefficient α and transmitting it to one end of the adder 320. Multi-channel serial processing unit, characterized in that. The channel multiplexer 400 separates the voice data transmitted from the adder 320 of the quasi-instantaneous demodulator 300 into 1, 2, 3, and 4 channels using a 2sf (sampling frequency) clock. The latches 410 and 420, the latches 430 and 440 for multiplexing the channel data transmitted from the latches 410 and 420 using sf clocks, and the latches 410, 420, 430 and 440. And an inverter (450, 460) for applying a clock signal.