KR0154195B1 - Storage electrode fabrication method of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a charge storage electrode of a semiconductor device, in order to effectively increase the effective surface area of the charge storage electrode by using an etch selectivity of the dope polysilicon and HSG film to form a multi-layer HSG film having a cavity (cavity) structure This maximizes the exposure of the hemispherical grain surface of the HSG film exposed to the inside and outside of the charge storage electrode, thereby effectively increasing the effective surface area of the charge storage electrode and thus maximizing the capacitance of the capacitor within the limited region. The present invention relates to a storage electrode forming method.

Description

Method for forming charge storage electrode of semiconductor device

1A to 1E are cross-sectional views of devices sequentially shown to explain a method of forming a charge storage electrode of a semiconductor device according to the present invention.

2 is a partial perspective view of FIG.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2: field oxide film

3: junction region 4: gate electrode

5: insulating film

6, 8, 10, and 12: first to fourth dope amorphous silicon

6A, 8A, 10A, and 12A: first to fourth dope polysilicon

7, 9, 11, and 14: first through fourth HSG films

13 and 13A: first and second photosensitive film pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a semiconductor device. In particular, a multi-cavity cavity is formed of a hemispherical polycrystalline silicon using an etch selectivity of doped polysilicon and hemispherical silicon grains. The present invention relates to a method for forming a charge storage electrode of a semiconductor device in which the capacitance of the capacitor can be maximized by increasing the effective surface area by forming the structure.

In general, the area of a cell is rapidly reduced due to the high integration of semiconductor devices such as DRAM. However, in order to operate the device, it is difficult to secure a certain amount or more of capacitance per unit cell. Accordingly, while maintaining the capacitance required for the operation of the cell as it is, while minimizing the area on the chip occupied by the capacitor and securing a certain level of capacitance, it is highly necessary to develop high process technology and secure device reliability. It is a problem.

In order to solve this problem, it is necessary to form a three-dimensional structure of a capacitor to increase the effective surface area or to develop a dielectric having improved dielectric properties. However, the development of a dielectric film having an ideal dielectric property is difficult to apply to the manufacturing of the device yet, so much research has been made in the direction of maximizing the effective surface area of the charge storage electrode in order to secure the capacitance required for the operation of the device. .

Accordingly, the present invention provides a method for forming a charge storage electrode of a semiconductor device that can solve the above disadvantages by forming a hemispherical polycrystalline silicon in a multi-layered cavity structure by using the etching selectivity of the dope polysilicon and the hemispherical polycrystalline silicon. There is a purpose.

According to an aspect of the present invention, there is provided a method of forming a contact hole by etching a predetermined portion of an insulating film formed on a silicon substrate until the junction region is exposed, and forming doped amorphous silicon for a charge storage electrode in the contact hole. Depositing, forming a HSG film and dope amorphous silicon in a multi-layer structure on the entire structure, and forming a first photoresist film pattern on the uppermost dope amorphous silicon, and using the first photoresist pattern as an etching mask. Patterning the HSG film and the dope amorphous silicon formed in multiple layers, forming a top HSG film and a second photoresist pattern on the entire structure, and exposing the top HSG film using the second photoresist pattern as an etch mask. Removing the second photoresist pattern after etching the portion of the formed portion, and the dope amorphous chamber for the charge storage electrode And crystallizing the dope amorphous silicon formed of the multi-layer and the multi-layer to form the do polysilicon, and removing the dope polysilicon formed of the multi-layer.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1A through 1E are cross-sectional views of devices sequentially shown to explain a method of forming a charge storage electrode of a semiconductor device, and FIG. 2 is a partial perspective view of FIG. 1E.

Referring to FIG. 1A, an insulating film 5 is formed on a silicon substrate 1 on which a field oxide film 2, a gate electrode 4, a junction region 3, and the like are formed through a predetermined process. A contact hole is formed in the insulating layer 5 so that the junction region 3 is exposed through a photolithography and an etching process using a mask for forming a contact hole for the charge storage electrode. The first dope amorphous silicon 6 for the charge storage electrode is deposited inside the contact hole.

Referring to FIG. 1B, a first hemispherical polysilicon film (hereinafter referred to as HSG film) 7 is deposited on the entire structure at a temperature range of 560 to 580 ° C., followed by phosphorus (P) or arsenic (As). A second dope amorphous silicon 8 doped with a dopant is formed in a temperature range of 490 ° C to 550 ° C. In the same manner, the second HSG film 9, the third dope amorphous silicon 10, the third HSG film 11, and the fourth dope amorphous silicon 12 are sequentially formed. The first photoresist layer pattern 13 is formed on the fourth dope amorphous silicon 12.

Referring to FIG. 1C, the fourth dope amorphous silicon 12, the third HSG film 11, the third dope amorphous silicon 10, and the second HSG film 9 using the first photoresist film pattern 13 as an etching mask. ), The second dope amorphous silicon 8 and the first HSG film 7 are sequentially etched and patterned. The first photoresist layer pattern 13 is removed, and the fourth HSG layer 14 is deposited on the entire structure at a temperature range of 560 to 580 ° C., and then the photoresist layer is applied. The second photoresist pattern 13A is formed through a photolithography and an etching process using a mask for a charge bottom electrode.

Here, the HSG film and the dope amorphous silicon are repeatedly formed as many as the number of layers to be formed, and the top layer is made the HSG film and the deposition temperature of the HSG film is not higher than 580 ° C.

Referring to FIG. 1D, the exposed portion of the fourth HSG film 14 is etched using the second photoresist pattern 13A as an etching mask, and then the second photoresist pattern 13A is removed. Heat treatment is performed under an inert gas atmosphere to activate the dopants contained in the second to fourth dope amorphous silicon 8, 10 and 12. At this time, doping the dopant contained in the amorphous silicon is not diffused into the upper and lower HSG film only doped amorphous silicon in only enabled to 600 ~ 700 ℃ temperature 30 minutes in an inert gas atmosphere such as nitrogen (N ₂₎ or argon (Ar) a - Heat treatment for 5 hours. Through the heat treatment process, the first to fourth dope amorphous silicon 6, 8, 10, and 12 are crystallized and changed into the first to fourth dope amorphous silicon 6A, 8A, 10A, and 12A.

FIG. 1E is a cross-sectional view of the fourth to second dope polysilicon 12A, 10A, and 8A removed to form the charge storage electrode. HNO ₃ : CH ₃ COOH during etching of dope polysilicon; HF: H ₂ O = 30: 3: Wet etching using an etching solution mixed from 0.5 to 0.3: 15 or dry etching in a reactive ion etching equipment (RIE Etcher), but the ion energy in a Cl ₂ gas atmosphere Etch under low conditions. In other words, Cl ₂ is more than 50SCCM, pressure is more than 1 Torr and less than 150W, isotropic etching with selectivity of 10: 1 or more. Therefore, as shown in FIG. 2, only the dope polysilicon existing between the layers with the HSG film is removed to form a multi-layer HSG film in a hollow structure.

As described above, according to the present invention, a multi-layer HSG film is formed into a cavity structure by using an etch selectivity of the dope polysilicon and the HSG film. The exposure is maximized so that the effective surface area of the charge storage electrode is effectively increased, and therefore, there is an excellent effect that the capacitance of the capacitor can be maximized within the limited area.

Claims (8)

Forming a contact hole by etching a predetermined portion of the insulating film formed on the silicon substrate until the junction region is exposed, embedding the dope amorphous silicon for the charge storage electrode in the contact hole, and HSG over the entire structure Forming a film and a dope amorphous silicon in a multi-layered structure, and forming a first photoresist film pattern on the uppermost dope amorphous silicon, and then using the first photoresist film pattern as an etching mask, the HSG film and the dope amorphous silicon. Forming a top HSG film and a second photoresist pattern on the entire structure, and etching the exposed portion of the top HSG film using the second photoresist pattern as an etching mask. Removing the pattern; and the dope amorphous chamber formed of the dope amorphous silicon and the multilayer for the charge storage electrode. And a step of heat treatment to make the doped polysilicon by crystallizing the cone, the charge storage electrode is formed of a semiconductor element, characterized in that comprising the step of removing the doped polysilicon formed by the multi-layer. The method of claim 1, wherein the HSG film and the uppermost HSG film formed in multiple layers are deposited at a temperature of 560 to 580 ° C. 7. The method of claim 1, wherein the dope amorphous silicon formed of the multilayer is doped with a dopant such as phosphorous or arsenic, and is formed at a temperature in a range of 490 to 550 ° C. The method of claim 1, wherein the heat treatment is performed in an inert gas atmosphere at a temperature of 600 to 700 ° C. so that the dopant contained in the multilayered dope amorphous silicon is activated only in the dope amorphous silicon without diffusing to the upper and lower HSG films. A charge storage electrode forming method of a semiconductor device, characterized in that performed for about 5 hours. The method of claim 4, wherein the inert gas is any one of nitrogen and argon. The method of claim 1, wherein the HNO ₃ : CH ₃ COOH of the dope polysilicon formed in a multilayer; HF: H ₂ O = 30: 3: The method for forming a charge storage electrode of a semiconductor device, characterized in that the removal by the wet etching method using an etching solution mixed from 0.5 to 0.3: 15. The method of claim 1 or 6, wherein the dope polysilicon formed in the multilayer is etched by a dry etching method in a condition of low Cl ₂ gas atmosphere and ion energy in the reactive ion etching equipment, isotropic etching having a selectivity of 10: 1 or more The charge storage electrode forming method of a semiconductor device, characterized in that the etching. The method of claim 7, wherein the dry etching is performed using Cl ₂ gas of 50 SCCM or more and energy of 150 W or less in a pressure atmosphere of 1 Torr or more.