KR0153112B1 - Counter enable to program - Google Patents

Abstract

The present invention discloses a programmable counter. The circuit consists of a counter consisting of n flip-flops that count in increments of 0 to 2 ⁿ -1 by 1 in response to a clock signal, n output signals of the counter, and n signals representing the counting range, respectively. A comparison unit composed of n comparators for comparing and generating n comparison output signals, and an inverted clock signal when the counter resets in response to a reset signal or a signal indicating that the n comparison output signals of the comparison unit are all the same And a reset section for generating a control signal and resetting the counter in response.

Description

Programmable counter

The present invention relates to a programmable counter, and more particularly to a programmable counter that allows a user to arbitrarily set a counting range to count a desired value.

FIG. 1 is a circuit diagram of a conventional counter, showing a 14-degree counter which is reset in binary 1101. As shown in FIG. Counter consisting of four T flip-flops 11, 12, 13, and 14 counting values from 0000 to 1101 in response to the clock signal CLK, T flip-flops 11, 12, when counting 1101. It consists of the reset part 15 for resetting 13,14.

The reset unit 15 uses an AND gate 16 for performing logical multiplication on the output signals of the T flip-flops 11, 12, 13, and 14, and an output signal of the AND gate 16 as an input signal D, and an inverter ( 17) is used to logically multiply the output signals of the D flip-flop 18 and the inverter 17 by the clock signal CLK inverted by the clock signal input terminal CK. AND gate 19 and NOR gate 20 which outputs the output signal of AND gate 19 and the reset signal RESET non-logically and outputs it as the reset signal of T flip-flops 11, 12, 13, and 14. It is.

The counter shown in FIG. 1 is a 4-bit counter and is a circuit capable of counting the output signals A1, A2, A3, A4 from 0000 to 1101 in response to the clock signal CLK.

FIG. 2 is an operation timing diagram for explaining the operation of the counter shown in FIG. 1. Referring to FIG. 2, the operation of the circuit shown in FIG.

First, when the high level reset signal RESET is input, the NOR gate 20 generates a low level signal to reset the T flip-flops 11, 12, 13, and 14. After the T flip-flops are reset, when the low level reset signal RESET is applied and the clock signal CLK is applied, the T flip-flops perform up counting. That is, the T flip-flops count from 0000 to 1101 in response to the clock signal. The AND gate 16 logically multiplies the output signals of the T flip-flops 11, 12, 13, 14, and the inverter 21 to output a high level signal. The D flip-flop 18 latches and outputs the output signal of the AND gate 16 in response to the clock signal inverted by the inverter 17. The AND gate 19 then multiplies the high level output signal output from the D flip-flop 18 by the high level signal output from the inverter 17 to generate a high level signal. The NOR gate 20 non-logically combines the high level output signal and the reset signal RESET output from the AND gate 19 to generate a low level signal to reset the T flip-flops 11, 12, 13, and 14. In this manner, after the T flip-flops 11, 12, 13, 14 are reset, the up counting as described above is repeatedly performed in response to the clock signal CLK.

That is, the counter shown in FIG. 1 is reset after counting from 0000 to 1101, and counts repeatedly from 0000 to 1101 again.

Therefore, the conventional counter is a counter that counts repeatedly from 0000 to 1101. Since only the predetermined range of values are repeatedly counted, when configuring a circuit that performs two or more counting operations, it is necessary to use as many counters as desired. Therefore, there is a problem that the circuit configuration is complicated.

In addition, the conventional counter can be used when repeatedly counting only a specific range of values, but there is a problem that cannot be used when the value to be counted is changed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a programmable counter that can count a desired value by setting a counting range.

Programmable counter of the present invention for achieving this object is a counting means consisting of n flip-flops counting by increasing the value from 0 to 2 ⁿ -1 by 1 in response to a clock signal, n of the counting means Comparison means composed of n comparators for generating n comparison output signals by comparing n output signals with n signals representing a counting range, respectively, and resetting the counting means in response to a reset signal, and a reset means for generating a control signal and resetting the counting means in response to the inverted clock signal when the n comparison output signals are the same.

1 is a circuit diagram showing the configuration of a conventional counter.

FIG. 2 is an operation timing diagram for explaining the operation of the circuit shown in FIG.

3 is a circuit diagram showing the configuration of the programmable counter of the present invention.

4 is an operation timing diagram for explaining the operation of the circuit shown in FIG.

Hereinafter, a programmable counter of the present invention will be described with reference to the accompanying drawings.

3 shows the configuration of a programmable counter according to an embodiment of the present invention, in which four T flip-flops generate a predetermined value in response to a clock signal CLK and generate output values A1, A2, A3, and A4. Counter 30 composed of fields 31, 32, 33, 34, and a counting value P1, P2, P3, P4 determined by a user, and output values A1, A2, A3, A4 of the counter 30 are compared. And a reset section 50 for resetting the counter 30 in accordance with the output signal of the comparing section 40.

The counter 30 includes a clock signal applying terminal CK to which the clock signal CLK is applied and a clock signal to which the output signals of the T flip-flop 31 and the T flip-flop 31 are applied. The T flip-flop 32 composed of the signal applying terminal CK and the output signal generating terminal Q, and the clock signal applying terminal CK and the output signal generating terminal Q to which the output signal of the T flip-flop 32 is applied. The T flip-flop 33 is composed of a clock signal application terminal CK to which the output signal of the T flip-flop 33 is applied, and a T flip-flop 34 composed of the output signal generation terminal Q.

The comparator 40 is an XNOR gate for non-exclusively ORing the output signals of the T flip-flops 31, 32, 33, and 34 and the signals P1, P2, P3, and P4 set by the user, respectively. Fields 41, 42, 43, and 44, respectively.

The reset unit 50 includes an AND gate 51 for ANDing the output signals of the XNOR gates 41, 42, 43, and 44, an inverter 52 for inverting the clock signal CLK, and an inverter 52. The D flip-flop 53 and the inverter comprising a clock signal application terminal CK to which an output signal of the signal is applied, a data input terminal D to which an output signal of the AND gate 51 is applied, and an output signal generation terminal Q. AND gate 54 for ANDing the output signal of 52 and the output signal of D flip-flop 53, and NOR gate for non-logically outputting the reset signal RESET and the output signal of AND gate 54. It consists of 55.

The reset unit 50 receives the T flip-flops constituting the counter 30 when the high level reset signal RESET from the outside is applied or the output signal of the AND gate 54 is high level. Reset the 32, 33, and 34. When the reset signal RESET becomes low and the clock signal CLK is applied, the counter 30 performs up counting in response to the clock signal CLK. The unit 40 may set the XNOR gates 41, 42, when the counting values P1, P2, P3, and P4 input by the user and the output signals A1, A2, A3, and A4 of the counter 10 are the same. The output signals of the 43 and 44 all become high level, and the output signal of the AND gate 51 becomes high level, and the D flip-flop 53 responds to the inverted clock signal output from the inverter 52. The high level signal, which is an output signal of the AND gate 51, is latched and outputted. The AND gate 54 latches the output signal of the D flip-flop 53 in response to the output signal of the inverter 52. W and outputs. The NOR gate 55 will reset the T flip-flop so that the output signal of the AND gate 54 the high level to generate an output signal of a low level constituting the counter 30.

FIG. 4 is an operation timing diagram for explaining the operation of the programmable counter of the present invention. Referring to FIG. 4, the operation of the circuit shown in FIG.

First, as shown in (d)-(g) of FIG. 4, the user sets in advance the values P1, P2, P3, and P4 to be counted, and the XNOR gates 41, 42, 43 of the comparator 40. , 44).

When the high level reset signal RESET is applied as shown in (b) of FIG. 4, the output signal of the XNOR gate 55 goes low and the T flip-flops 31, 32, and 33 forming the counter 30 are provided. , Is applied to the reset terminal of 34) to reset the T flip-flops.

After the reset, when the clock signal CLK as shown in FIG. 4A is applied to the counter 30, the T flip-flops 31, 32, 33, and 34 perform a counting operation to perform the counting operation of FIG. Generate output signals A1, A2, A3, A4 as shown in (K) in H).

The T flip-flops 31, 32, 33, and 34 perform a counting operation so that each of the output signals of the T flip-flops is equal to each of the counting values P1, P2, P3, and P4 preset in the comparator 40. Otherwise, a low level signal is generated, and in the same case, a high level signal is generated.

The reset unit 50 generates a high level signal R1 when the output signals of the comparator 40 are all high level, and is low when at least one of the output signals of the comparator 40 is a low level signal. Generate the signal R1 of the level. The AND gate 51 generates a high level signal when the output signals of the comparator 40 are all high level, and the D flip-flop 53 responds to the clock signal CLK inverted by the inverter 52. The high level signal output from the AND gate 51 is latched and output. The AND gate 54 outputs the output signal of the D flip-flop 53 in response to the high level output signal of the inverter 52. The NOR gate 55 inverts the output signal of the high level AND gate 54 to generate a low level signal. Thus, the T flip flops constituting the counter 30 are reset.

The present invention can be counted up to a range set by the user by performing the copper field in the same manner as described above.

When the output signals of the XNOR gates constituting the comparator 40 are Y1, Y2, Y3, and Y4, respectively, the output signals Y1, Y2, Y3, and Y4 can be expressed as follows.

Y4 = A4P4 + A4'P4 '

Y3 = A3P3 + A3'P3 '

Y2 = A2P2 + A2'P2 '

Y1 = A1P1 + A1'P1 '

In addition, since the counter 30 should be reset only when the output signals Y1, Y2, Y3, and Y4 of the comparator 40 are all 1, the signal R1 may be represented by the following logical expression.

R1 = Y1Y2Y3Y4

Here, the counter of the present invention is applicable to all counters of synchronous or asynchronous, and the D flip-flop 53 is a level trigger type using a latch.

Therefore, the programmable counter of the present invention can count a desired value by setting a value to be counted by the user and comparing the counted value with the set value.

The counting operation may be performed by setting a counting value in advance in an initial state according to the input data. However, the counting value may be arbitrarily determined even during the counting operation.

Claims (3)

Counting means comprising n flip-flops for counting by increasing a value from 0 to 2 ⁿ -1 by 1 in response to a clock signal; n output signals of the counting means and n signals representing a counting range, respectively Comparison means comprising n comparators for generating n comparison output signals in comparison; and n flip-flops of the counting means in response to a reset signal or n comparison output signals of the comparison means are all the same And reset means for generating a control signal in response to an inverted clock signal to reset the n flip-flops of said counting means. The programmable counter of claim 1, wherein the n comparators have n XNOR gates for non-exclusively combining the output signals of the n flip-flops and the n signals representing the counting range, respectively. 3. The gate driving circuit of claim 1, wherein the reset unit comprises: a first AND gate for ANDing the output signals of the n XNOR gates; an inverter for inverting the clock signal to generate the inverted clock signal; A D flip-flop having a data input terminal to which an output signal is applied, a clock signal input terminal to which an output signal of the inverter is applied, and a data output terminal to output data; and a D flip-flop in response to an output signal of the inverter. A second AND gate for outputting an output signal as the control signal; And a NOR gate for generating a signal for resetting the n flip-flops by non-logically combining the reset signal and the control signal.