KR0151193B1 - Semiconductor device manufacturing device - Google Patents

Abstract

The present invention relates to a method for manufacturing a highly integrated DRAM cell having a three-dimensional U-shaped capacitor capable of obtaining high cell capacitance compared to a small planar area. A method of manufacturing a DRAM cell includes the steps of forming a field oxide film on a semiconductor substrate, forming a first spacer transistor on the gate oxide film, the gate, the first and second impurity regions, and the gate sidewalls, Forming a planar insulating film, forming a bit line contact by exposing the first impurity region by removing the insulating film over the first impurity region by using a bit line tone mask pattern, and exposing the first impurity region, Forming a second spacer on the sidewall, forming a bit line on the first planarization insulating film so as to contact the first impurity region through the bit line contact, and forming an insulating film for the second planarization over the entire surface of the substrate. Removing the first and second planarization insulating films over the second impurity region to form a node contact, and discharging the second impurity region; Forming a third spacer on a sidewall of the contact, forming a primary polysilicon film for a storage node over the entire surface of the substrate so as to contact the exposed second impurity region, and sequentially forming a pillar insulating film on the primary polysilicon film; A step of removing the primary polysilicon film and the pillar insulating film and leaving only the second planarization insulating film including the node contact, and depositing and etching back the secondary polysilicon film for the storage node on the entire surface of the substrate Leaving only the sidewalls of the insulating film, removing the pillar insulating film on the primary polysilicon film to form a storage node consisting of the primary polysilicon film and the secondary polysilicon film; and forming a dielectric film on the surface of the storage node. And forming a plate node by depositing a polysilicon film over the entire surface of the substrate.

Description

Manufacturing Method of Semiconductor Device

1 (a)-(i) are manufacturing process diagrams of a conventional DRAM cell.

2 (a)-(j) are manufacturing process diagrams of a DRAM cell according to an embodiment of the present invention.

3 shows a profile of a node contact of FIG. 2;

* Explanation of symbols for main parts of the drawings

51 semiconductor substrate 53 field oxide film

55 gate oxide film 57 gate

59, 65, 82: spacer 63: insulating film for planarization

64: bit line contact 67,83,87: polysilicon film

69: silicide 70: bit line

71,72,73: Flattening oxide film / nitride film / oxide film

77 node contact 79,81 nitride / oxide film for spacer

85: oxide film for pillar 88: storage node

89 Dielectric Film 91 Plate Node

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a DRAM cell, which is advantageous for high integration having a three-dimensional U-shaped capacitor capable of obtaining high cell capacitance compared to a small planar area.

Referring to (a) of FIG. 1, the field oxide film 13 for device isolation is formed on the semiconductor substrate 11, and the gate oxide film 15 and the gate 17 are sequentially formed.

After the gate 17 is formed, impurities are implanted into the substrate 11 to form the impurity regions 19 and 20 to complete the MOS transistor of the DRAM cell. This impurity region serves as a source / drain region in the transistor of the DRAM cell. Subsequently, the interlayer insulating film 21 is formed over the entire surface of the substrate, and the bit line contact 23 is formed by removing the interlayer insulating film 21 on the impurity region 19 on which the bit line is to be formed. In this case, as the bit line contact 23 is formed, the first impurity region 19 of the impurity region is exposed.

Referring to FIG. 1 (b), the polysilicon film 25 for bit lines is heavily deposited on the entire surface of the substrate, and planarized by performing an etch back process. A silicide 27 is formed on the planarized polysilicon film 25, and an insulating film 29 made of an oxide film is formed thereon as shown in FIG. Subsequently, as illustrated in FIG. 1D, the bit line 30 is formed by patterning the insulating layer 29, the silicide 27, and the polysilicon layer 25 using a bit line mask pattern. The bit line 30 is contacted with the first impurity region through the bit line contact 23.

After depositing an insulating film 31 made of an oxide film on the entire surface of the substrate as shown in FIG. 1 (e), the structure of the node is three-dimensional (3-d) on the bit line 30 as shown in FIG. 1 (f). The pillars of the pil-ler for construction are deposited and patterned to leave the pillar material 33 only in a predetermined region, and the rest is removed.

Polyamide is used as the color material. Subsequently, as illustrated in FIG. 1D, the bit line 30 is formed by patterning the insulating layer 29, the silicide 27, and the polysilicon layer 25. The bit line 30 is contacted with the first impurity region through the bit line contact 23. After depositing an insulating film 31 made of an oxide film on the entire surface of the substrate as shown in FIG. 1 (e), the structure of the node is formed three-dimensionally (3-D) on the bit line 30 as shown in FIG. The filler material 33 is deposited and patterned to leave the filler material 33 only in a predetermined region and to remove the rest, and polyimide is used as the filler material.

Subsequently, a contact etching process is performed to form a node contact in a portion where the capacitor is to be formed. That is, the insulating layer 31 on the second impurity region 20 is removed to form the node contact 35. Referring to FIG. 1 (g), deposition is performed over the entire surface of the substrate. Subsequently, an etching process for isolating each node is performed. First, a photoresist film 39 is applied over the entire surface of the substrate, and the entire surface is etched to remove the polysilicon film 37 for the storage node on the pillar material 33. Expose

As shown in FIG. 3 (h), the polysilicon layer 37 for the storage node exposed on the pillar material 33 is etched. After etching the polysilicon layer 37 for the storage node, the photoresist layer 39 and the pillar material 33 are removed to form the storage node 38.

The storage node 38 is contacted with the second impurity region through the node contact 35. Therefore, the storage nodes 38 are isolated from each other by the above etching process. Finally, as shown in FIG. 3 (I), the capacitor dielectric film 41 and the plate node 43 made of a polysilicon film are formed to complete the capacitor. As a result, a conventional DRAM cell is obtained.

In the conventional method of manufacturing a DRAM cell as described above, as the semiconductor device is highly integrated, the size of the device is also reduced, so that not only the bit line contact can be formed by applying the existing process but also the self-aligned node contact is formed. There was a problem that the short between the electrodes could not be completely prevented.

In addition, it is difficult to accurately align the node contacts in the limited active region, and there is a problem in that node contact leakage increases due to an arbitrary increase in node contact when forming node electrodes.

In addition, since polyimide, which is an organic material, is used to form the storage of the pillar-shaped capacitor, there is a problem in that the process is restricted.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a method of manufacturing a semiconductor device which is stable in processing and easy in processing. It is another object of the present invention to provide a method for manufacturing a semiconductor device capable of obtaining a capacitance of sufficient size suitable for a highly integrated product. It is still another object of the present invention to provide a method of manufacturing a semiconductor device capable of improving device characteristics by preventing node contact leakage current by preventing an increase in node contact when forming a storage node.

The present invention for achieving the above object comprises the steps of forming a field oxide film on a semiconductor substrate, forming a transistor by forming a first spacer in the gate oxide film, the gate, the first and second impurity regions and the gate side wall; Forming a first planarization insulating film on the entire surface of the substrate, removing the insulating film on the first impurity region using a bit line contact mask pattern to form a bit line contact, and exposing the first impurity region; Forming a second spacer on a sidewall of the bit line contact; forming a bit line on the first planarization insulating layer so as to contact the first impurity region exposed through the bit line contact; Forming a node contact by removing the step of forming the insulating film for the second planarization, and removing the insulating films for the first and second planarization above the second impurity region. Exposing the reverse side, forming a third spacer on the sidewall inside the node contact, and insulating the primary polysilicon film for the storage node and the pillar insulating film over the entire surface of the substrate so as to contact the exposed second impurity region. A step of forming sequentially, removing the primary polysilicon film and the pillar insulating film and leaving only on the second planarization insulating film including the node contact, and depositing and etching back the secondary polysilicon film for the storage node on the substrate Leaving only the sidewalls of the pillar insulating film, removing the pillar insulating film on the primary polysilicon film to form a storage node composed of the primary polysilicon film and the secondary polysilicon film; And forming a plate node by depositing a polysilicon film over the entire surface of the substrate. The.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 (a)-(j) are manufacturing process diagrams of a DRAM cell according to an embodiment of the present invention.

Referring to FIG. 2A, a field oxide film 53 is formed on a semiconductor substrate 51 to form a field oxide film 53, and a gate oxide film 55 and a gate 57 are formed. Subsequently, impurities are implanted into the substrate 51 using the gate 57 as a mask to form impurity regions 59-1 and 59-2 for source / drain regions of the MOS transistor, and the first gate side wall spacer ( 59) to form a MOS transistor of the DRAM cell.

Referring to FIG. 2B, a planarization insulating film 63 is first formed on the entire surface of the substrate, and the entire surface is etched to planarize the surface of the substrate.

The insulating film 63 of the portion where the bit line is to be formed is removed to form the bit line contact 64. An oxide film is used as the planarization insulating film 63, and the first impurity region 59-1 of the impurity region is exposed. Subsequently, second spacers 65 are formed in both side walls of the planarization insulating film 63 in the bit line contact 64.

In FIGS. 2A and 2B, oxide films are used for the first and second spacers 61 and 65. The spacer 65 is to improve the insulating property between the bit line to be formed in a subsequent process and the formed gate 57.

Referring to FIG. 2 (c), a polysilicon film 67 is deposited over the entire substrate, and silicide 69 is formed thereon. The silicide 69 and the polysilicon 67 are etched using a bit line mask to form the bit line 70.

Accordingly, the bit line 70 is in contact with the impurity region 59-1 exposed through the bit line contact 64.

Referring to FIG. 2 (d), an insulating film is deposited over the entire surface of the substrate, and the surface of the substrate is secondarily planarized by etching the entire surface of the insulating film or by heat treatment. That is, multiple insulating films of the oxide film 71, the nitride film 73, and the fine oxide film 75 are used as the insulating film for secondary planarization.

Referring to FIG. 2E, the capacitor node contacts 77 are formed by removing the first and second planarization insulating layers 63, 71, 73, and 75 of the portion where the capacitor node is to be formed. At this time, the capacitor node contact exposes the second impurity regions 61-2 on both sides of the bit line 70. Subsequently, the nitride film 77 and the oxide film 81 are formed over the entire surface of the substrate and then etched back to form third spacers 82 on both sidewalls of the capacitor node contact 77.

The third spacer 82 is formed in a double structure of the nitride film 79 and the oxide film 81 so that the capacitor to be formed in the bit line 70 and the subsequent process may improve the insulating property of the storage node.

At this time, the reason why the third spacer 82 is formed into a double structure of the nitride film 79 and the oxide film 81 is that the short space between the bit line and the storage node is less than that of the single oxide film 81. (short) is difficult to occur.

Referring to FIG. 2 (f), the primary polysilicon film 83 for storage is deposited over the entire surface of the substrate, and the oxide film 85 for pillars is thickly formed.

Referring to FIG. 2 (g), the oxide film 85 and the primary polysilicon film 83 are patterned only in the capacitor region. A secondary polysilicon film 87 for the storage node is then deposited over the entire substrate. Subsequently, the secondary polysilicon film 87 is etched back to form a second polysilicon film 87 in the form of a spacer on the sidewall of the pillar oxide film 85 as shown in FIG. Accordingly, the primary polysilicon layer 83 and the secondary polysilicon layer 87 in the form of a spacer are connected to form a U-shaped storage node 88 of the capacitor, and neighboring storage nodes 88 are separated from each other.

Subsequently, as shown in FIG. 2 (i), the planarization high temperature oxide film 75 and the pillar oxide film 85 exposed during the polysilicon film etching for forming the storage node are removed. In this case, if the high temperature oxide film 75 for planarization is removed, the area of the capacitor may be further increased.

In the oxide film removing process, the nitride film 79 forming the planarization nitride film 73 and the second spacer 82 serves as an etching stopper.

The area of the storage node 88 is maximized by removing not only the pillar oxide layer 85 but also the planarization high temperature oxide layer 75 under the storage node 88, thereby facilitating an increase in capacitance.

Finally, as shown in FIG. 2 (j), the entire capacitor film 89 is formed on the exposed surface of the storage node 88, and a polysilicon film is deposited over the entire surface of the substrate to form a plate node 91. Complete the capacitor of the cell. Thus, the DRAM cell of the present invention is obtained.

3 illustrates a cross-sectional view of the node contact profile of FIG. 2.

A double spacer is formed on both sidewalls of the node contact 77 to form the nitride film 79 and the oxide film 81 to insulate the polysilicon film 83 for the storage node from the bit line 70 and the gate 57. It can be seen that the characteristics are improved. In addition, it can be seen that the polysilicon layer 83 for the storage node is completely overlapped with the node contact 77.

According to the present invention as described above, the following effects can be obtained.

First, the planarization process is performed twice, and spacers are formed on the contact of the bit line contact and the capacitor node so that not only a stable process can be performed when manufacturing a fine pattern cell but also the design rule is minimized. At the same time, it is possible to improve insulation between nations.

In addition, since the N-O structure spacer is formed in the capacitor node contact to prevent the node contact from growing arbitrarily during the node formation process, the node contact leakage current characteristic is improved, thereby improving the product characteristic (increase in refresh rate).

Second, the storage node of the capacitor not only overlaps the node contact completely, but also has a three-dimensional U-shaped structure formed in the form of a spacer, and due to the removal of the oxide layer under the storage node, the area of the storage node is maximized to provide high integration. It is advantageous to secure an advantageous large capacity capacitance.

Third, since the nitride film acts as an etch stopper during the removal of the pillar oxide film and the planarization oxide film after the formation of the storage node, the oxide film under the nitride film is protected, so that a stable process can be performed and the insulating properties between the electrodes can be further improved. .

Claims (8)

Forming a transistor by forming a gate electrode having a first sidewall spacer on a first conductive semiconductor substrate, and forming first and second impurity regions of a second conductive type on substrates on both sides of the gate electrode; Depositing and then planarizing a first planarization insulating film on the entire surface of the substrate, selectively removing the first planarization insulating film to expose the first impurity region to form a bit line contact, and forming a bit line contact inside the bit line contact Forming a second sidewall spacer on a sidewall of the substrate; forming a second planarization insulating film formed of an oxide film, a nitride film, and an oxide film on the entire surface of the substrate; and forming first and second planarization films to expose the second impurity region. Selectively removing the insulating film to form a node contact, and forming a third sidewall spacer on a sidewall inside the node contact. And forming a first polysilicon film for a storage node so as to connect with the second impurity region, and sequentially forming an insulating film for pillars on the first polysilicon film, and the second planarization insulation including the node contact. Leaving the first polysilicon and pillar insulating film on the film, forming a second polysilicon film for the storage node on the entire surface of the substrate, and leaving only the side surface of the pillar insulating film, and the pillar insulating film and the second Removing the uppermost layer of the planarization insulating film to form a storage node made of first and second polysilicon films, forming a dielectric film on the surface of the storage node, and forming a third polysilicon film on the entire surface of the substrate. And a step of forming a node. 2. The method of claim 1, wherein the nitride film of the second planarization insulating film acts as an etch stopper layer when removing the pillar insulating film for forming the storage node. 2. The method of claim 1, wherein the second planarization insulating film acts as an etch stopper layer when removing the pillar insulating film for forming the storage node. The method of claim 1, wherein the oxide layer on the nitride layer of the second planarization insulating layer is removed together when the pillar insulating layer for forming the storage node is removed. The method of claim 1, wherein the first planarization insulating film is formed by depositing an insulating film over the entire surface of the substrate and then etching the entire surface. A semiconductor device manufacturing method. The method of claim 1, wherein the staff forming the third spacer comprises: depositing a nitride film over the entire surface of the substrate, depositing an oxide film on the nitride film, and simultaneously etching back the nitride film and the oxide film to a nitride film only on a sidewall inside the node contact. A method of manufacturing a semiconductor device, comprising the step of leaving an oxide film. 7. The method of claim 6, wherein the nitride film constituting the third spacer acts as an etch stopper when removing the insulating film for forming the storage node. The method of claim 1, wherein the storage node comprises a primary polysilicon film formed by overlapping a note contact and a secondary polysilicon film formed in contact with an end of the primary polysilicon film.