KR0149705B1 - A structure of the insulated gate bipolar transistor and manufacturing method of the same - Google Patents

Abstract

The present invention relates to an insulated gate bipolar transistor, and in order to increase the latch-up current without changing the threshold voltage, a buried region having a higher concentration of impurity concentration than the body is formed in a body region under the source region that affects the latch-up. By forming by ion implantation, an insulated gate bipolar transistor in which the threshold current at which latchup occurs is increased.

Description

Structure of Insulated Gate Bipolar Transistor and Manufacturing Method Thereof

1 is a view showing a cross-sectional structure of the IGBT according to the present invention.

2 is a view showing a profile according to doping concentration in the IGBT shown in FIG.

(A) and (ba) of FIG. 3 are cross-sectional structural diagrams of a conventional IGBT that does not form a p + buried region, and a cross-sectional structural diagram of IGBTs having a p + buried region according to the present invention. (bb) is a diagram showing the vertical doping profile under the n + source region according to the incision A-A 'in Fig. 3 (aa) and (ba), respectively.

(A) and (ba) of FIG. 4 are cross-sectional structural diagrams of a conventional IGBT without forming a p + buried region and cross-sectional structural diagrams of an IGBT with a p + buried region according to the present invention. (bb) is a diagram showing a horizontal doping profile of the channel region along the incision line B-B 'of Fig. 4 (aa) and (ba), respectively.

5 is a diagram showing variation of threshold voltage and variation of latchup current density according to the ion implantation dose of a p-type body in a general IGBT having no p + buried region.

6 is a view showing a correlation between a latch-up current density and a threshold voltage for an ion implantation dose for forming a p + buried region in an IGBT according to the present invention.

7 is a view showing a correlation between a threshold voltage and a latch-up current density according to ion implantation energy for forming a p + buried region.

8 is a view comparing and comparing the values of the latchup-producing current density according to the forward voltage drop in the IGBT according to the present invention and the IGBT according to the prior art.

9 is a diagram consisting of Figure 9 (a) to Figure 9 (d) showing a step of each method for manufacturing the IGBT according to the present invention.

* Explanation of symbols for main parts of the drawings

10: p-type substrate 12: n + buffer layer

14: n-epi layer 16: p-type body region

18: n + source region 20: p + buried region

22: p ++ region 24: gate insulating film

26 gate electrode 28 insulating film

30: cathode electrode

The present invention relates to an Insulated Gate Bipolar Transistor (hereinafter referred to as IGBT), and more particularly, to a structure of an IGBT improved in latch-up characteristics and a method of manufacturing the same.

Recently, the IGBT, which has been widely applied as a power device, has an advantage of low voltage drop and easy fast switching. The biggest problem with the IGBT is that the parasitic thyristors are structurally formed, so the latch-up is very difficult. It is vulnerable, and various techniques have been developed to improve latchup accordingly. Conventional representative techniques for suppressing latchup include a method of improving latchup by reducing the resistance of the p-type body or reducing the current flowing through the p-type body. In the prior art, a method of forming a highly doped p ++ diffusion region in the center of a p-type body as an effective method of reducing resistance is disclosed on pages 192 to 198 of IEEE Transaction on Electron Device published in 1984.

However, if the above p ++ diffusion region is formed, it is difficult to control the threshold voltage of the MOS transistor, so that the p-type body cannot be formed to completely surround the p-type body. As a result, there is a limit to improving latchup.

An object of the present invention for solving the above problems is to provide a structure of the IGBT and a method of manufacturing the same that can suppress the latch-up.

Another object of the present invention is to provide an IGBT having an improved latch-up characteristic without affecting the threshold voltage.

The present invention for achieving the above object, by forming a buried region having a higher concentration of the same conductivity type impurity concentration than the body in the body region under the source region that affects the latch-up by high energy ion implantation, It is characterized in that the structure of the insulated gate bipolar transistor in which the generated threshold current is increased and its manufacturing method.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to assist the overall understanding of the present invention.

In the following, specific details such as the doping concentration of each impurity region, the length of each of the divided buffer layers, and the like are provided to help the understanding of the present invention.

Like reference numerals are used throughout the drawings to refer to like elements throughout the drawings, and also, for convenience of description, the operation of the present invention will be compared to the above-described prior art, and thus, the characteristics of the present invention will be described more clearly. .

FIG. 1 is a view showing the structure of an IGBT according to the present invention, and is a cross-sectional structure diagram of two IGBTs formed in symmetrical proximity while sharing an anode electrode and a cathode electrode. Referring to FIG. 1, p-type impurities are integrated on a doped silicon substrate 10 at a concentration of IGBT 10 ¹⁸ / cm ³ according to the present invention. The substrate 10 is connected to an anode electrode to which an operating current is supplied. An n + buffer layer 12 having an impurity concentration of 5 × 10 ¹⁶ / cm ³ is formed on the substrate 10 to a thickness of 2.5 μm, and a 5 × 10 ¹⁴ / cm ³ layer is formed on the n + buffer layer 12. An n-silicon epitaxial layer 14 doped with an impurity concentration is formed. The impurity concentration of the surface is 10 ¹⁹ / cm ³ on a part of the main surface of the n- epi layer 14, and a p ++ diffusion region 22 having a depth of 3.1 mu m from the main surface of the epi layer 14 is formed. contacting the left and right sides of the p ++ diffusion region 22, a p-type body 16, which is a diffusion region having a surface impurity concentration of 10 ¹⁶ / cm ³ and having a width of 14.8 µm and a depth of 2.4 µm, is formed. The two p-type bodies 16 are spaced apart from each other by a distance of 13 μm. The p-type body 16 operates as a source of an n-channel MOS transistor and has a high concentration of 2 × 10 ²⁰ / cm ³ and an n + source region 18 having a length of 4.4 μm. ) Is formed. A gate electrode 26 spaced apart from the gate insulating layer 24 is formed in a region where the exposed surfaces of the n− epi layer 14, the p-type body 16, and the n + source 18 are adjacent to each other next to each other. The length of the p-type body 16 positioned below the gate electrode 26, that is, the channel length of the MOS transistor, is 1.2 μm. A p + buried region 20 is formed under the n + source region 18. The p + buried region 20 is preferably formed to be in contact with the bottom surface of the n + source region 18, and has a concentration of impurity higher than at least the p-type body 16, for example, 10 ¹⁸ / cm ³ . The p ++ region 22 and the n + source region 18 are commonly connected to the cathode electrode 30. The gate electrode 26 is spaced apart from the cathode electrode 30 by an insulating film 28 such as a BPSG (Borophosphorsilicate Glass) film. The p + buried region 20 formed according to the characteristics of the present invention is formed with the p-type body 16 by ion implantation and diffusion, and then at least 1 μm with high energy (about 500 KeV) using the same mask layer. It is formed by performing deep ion implantation.

2 is a view showing a profile according to the doping concentration in the IGBT structure of FIG. 1 according to the present invention. Three boundary lines 104, 102, and 100 indicated by solid lines in FIG. 2 indicate boundary lines of regions having impurity concentrations of 10 ¹⁸ / cm ³ , 10 ¹⁷ / cm ³ , and 10 ¹⁶ / cm ³ , respectively. As shown in FIG. 2, the boundary 104 having an impurity concentration of 10 ¹⁸ / cm ³ by impurity implanted to form a p + buried well has a gate electrode more than the bottom of the n + source 18. It can be seen that it extends deep into the (26) side. Accordingly, it can be seen that the p + buried region 20 covers most of the p-type body 16 that causes the latchup, and accordingly, the latchup is suppressed by the formation of the p + buried region 20.

FIG. 3 is a view illustrating a comparison of a doping profile of a vertical structure in the structure of an IGBT having a p + buried region and a conventional IGBT having a same structure without the formation of a p + buried region according to the present invention. (A) and (ba) are cross-sectional structural diagrams of a conventional IGBT without forming a p + buried region and cross-sectional structural diagrams of an IGBT having a p + buried region according to the present invention, respectively, (ab) and (bb) of FIG. ) Is a diagram showing the vertical doping profile under the n + source region along the incision A-A 'in FIGS. 3A and 3B, respectively. In FIG. 3, compared to the doping profile between the n + source region and the p-type body of the conventional IGBT shown in FIG. 3 (ab), the n + source region in the IGBT according to the present invention shown in FIG. It can be seen that the doping concentration between the p-type bodies is greatly increased. This is due to the formation of the p + buried region, and it can be seen that the doping concentration of the region affecting the latchup is increased, and as a result, the resistance is reduced and the latchup generation is suppressed.

4 illustrates a horizontal doping profile for a portion of a channel region that affects a threshold voltage in an IGBT having a p + buried region and a conventional IGBT having only the same structure without the formation of a p + buried region according to the present invention. 4A and 4B are cross-sectional structural diagrams of a conventional IGBT having no p + buried regions and a cross-sectional structural diagram of IGBTs having a p + buried region according to the present invention. (Ab) and (bb) of FIG. 4 are diagrams showing a horizontal doping profile of the channel region according to the incision line B-B 'of (aa) and (ba) of FIG. In FIG. 4, the doping profile for the channel region of the conventional IGBT shown in FIG. 4 (ab) and the doping profile for the channel region of the IGBT according to the present invention shown in FIG. 4 (bb) are almost identical to each other. It can be seen. Therefore, even when the deep ion implantation is performed to form the p + buried region according to the present invention, it can be seen that the doping concentration of the channel region affecting the threshold voltage is hardly changed.

5 is a diagram showing the variation of the threshold voltage and the latch-up current density according to the ion implantation dose of the p-type body in the general IGBT having no p + buried region. As shown in FIG. 5, as the ion implantation amount of the p-type body increases, the latch-up current increases and the threshold voltage increases. Therefore, conventionally, increasing the ion implantation amount of the p-type body in order to increase the latch-up current has an obvious limitation in view of the relationship with the threshold voltage.

6 is a diagram showing the correlation between the latch-up current density and the threshold voltage for the ion implantation dose amount for forming the p + buried region in the IGBT according to the present invention. For example, the effect of the p-type body on ion implantation is shown. That is, in FIG. 6 (a), when the threshold voltage is set to 4.5 volts, the threshold voltage and the latch when the dose is changed from 1 × 10 ¹⁴ / cm ² to 10 × 10 ¹⁴ / cm ^{2 with} 50 KeV energy 6 (b) shows a change in dose from 1 × 10 ¹³ / cm ² to 10 × 10 ¹³ / cm ^{2 with} 50KeV energy when the threshold voltage is set to 1 volt. Fig. 11 shows changes in threshold voltage and latch-up current when they are made. In Figs. 6 (a) and 6 (b), the dose amount is zero (zero), which is a measurement result of the conventional IGBT structure in which no p + buried region is formed.

Referring to FIG. 6 (a), when the ion implantation for forming the p + buried region is performed, the latch-up current is continuously increased in conjunction with the dose, while the threshold voltage has a negligible variation. It can be seen that the level is almost constant. This indicates that by forming the p + buried region according to the present invention, the latch-up current can be improved without changing the threshold voltage. For example, when the p + buried region is formed with an ion implantation dose of 10 × 10 ¹⁴ / cm ² , a latch-up current of about 10 times higher than that of the conventional IGBT structure can be obtained without fluctuation in threshold voltage. Here, since the threshold voltage is determined by the doping concentration of the p-body, and the latch-up is determined by the doping concentration of the p + buried region, even if the doping concentration of the p + buried region is different, Threshold voltages are different.

Even when the ion implantation to form the p + buried region is performed even in the low dose amount ion implantation shown in FIG. 6 (b), the latch-up current continuously increases in conjunction with the dose amount, while the variation of the threshold voltage is approximately 0.1. It can be seen that it is almost insignificant to be negligible below V and maintains a constant level.

7 is a diagram showing the correlation between the threshold voltage and the latch-up current density according to the ion implantation energy to form the p + buried region, and FIG. 7 (a) shows the ion implantation with the dose of 1 × 10 ¹⁴ / cm ² The energy is changed to 100 to 500 KeV, and FIG. 7 (b) shows a case where the dose is set to 5 x 10 ¹⁴ / cm ² and the ion implantation energy is changed to 200 to 700 KeV.

In FIG. 7 (a), as the ion implantation energy is increased, the threshold voltage gradually decreases and is maintained at a constant level of about 4.5 volts at 200 KeV, and the latch-up current density gradually increases to a maximum value between 300 and 400 KeV. Tends to be lowered again. This is because when the implanted impurities such as boron are injected too deep, the doping concentration of the n + source is lowered. Therefore, the ion implantation energy that can obtain the maximum latchup current density is selected to improve the latchup characteristic. The same tendency as in Fig. 7 (a) is shown in Fig. 7 (b), but it can be seen that the absolute magnitude of the latch-up current density is larger than that of Fig. 7 (a). This indicates that when the ion implantation energy is the same, better latch-up characteristics can be obtained than when the dose is large.

FIG. 8 shows a comparison of current density values at which latchup occurs due to a forward voltage drop in the IGBT according to the present invention and the IGBT according to the prior art. IGBT according to the present invention is a case in which the energy and dose of 5 × 10 ¹⁴ / cm ² to the p + buried region of 500KeV, the present invention and the conventional IGBT both the p-type body is 1 × 10 ¹⁴ energy and dose of 40KeV It is a structure implanted with / cm ² . In FIG. 8, a latch-up occurs in that a negative resistance region in which a current increases with increasing voltage and then reverses and a voltage decreases appears. It can be understood that when a latch-up occurs, the current increases as the parasitic thyristor is turned on, but the voltage decreases, resulting in a negative resistance region. In FIG. 8, a conventional IGBT has a latchup at a current density of about 0.7 × 10 ³ A / cm ² , while a latchup occurs at about 4 × 10 ³ A / cm ² in an IGBT according to the present invention. Therefore, it can be seen that the threshold current of the latch-up of the IGBT according to the present invention is about 6 times higher under the same conditions.

FIG. 9 is a view of FIGS. 9 (a) to 9 (d) illustrating a method of manufacturing an IGBT according to the present invention. Referring to Figure 9 looks at the manufacturing method of the IGBT according to the present invention.

Referring first to FIG. 9 (a), an n + buffer layer 12 and an n- epi layer 14 are grown on a p-type semiconductor substrate 10, and then a device is formed on the main surface of the epi layer 14. After forming the separator 15 and patterning to form an opening, ion-implanted p-type impurities through the opening and then diffusing to form a p ++ region 22, as shown in Figure 9 (b) Likewise, the p-type body 16 is formed to be interviewed with the p ++ region 22. In this case, when the p ++ buried region is not formed without forming the p ++ region 22, the p-type body 16 is immediately formed without forming the p ++ region, and then the subsequent process is performed. In addition, the n− epitaxial layer 14 may be formed immediately without forming the n + buffer layer 12.

Referring to FIG. 9 (c), a high concentration of p + buried region 20 buried in the p-type body 16 is formed by ion implantation of p-type impurities for forming a buried region in the p-type body 16. The process is performed.

Next, referring to FIG. 9 (d), the n + source region 18 is formed on the p + buried region 20 by performing an n-type ion implantation and diffusion process by defining an upper portion of the p + buried region 20. The process of forming is performed. In this case, it is more effective to form the buried region 20 to be in contact with the bottom surface of the n + source region 18.

After the above-described processes, although not shown, the epitaxial layer 14 and the second diffusion region may be formed by the gate electrode 26 interposed between the exposed surface of the p-type body region 16 and the gate insulating layer 24. And forming a cathode electrode 30 insulated from the gate electrode 26 and commonly connected to the p-type body region 16 and the n + source region 18. By this progress, the IGBT structure of the present invention shown in FIG. 1 is formed.

In addition, in the above embodiment, the manufacturing process is illustrated and described with a focus on the formation of the diffusion regions in order to reveal the gist of the present invention. First, two gate electrodes spaced apart from each other by a predetermined distance are formed on the main surface of the n-epi layer according to a general method. Then, a p-type body and a p ++ region are formed between the gate electrodes as an ion implantation mask. The same structure can be obtained even if the p-type buried region and the n + source region are formed.

As described above, according to the present invention, by forming a p + buried region under the n + source region, a high latch-up current can be obtained without a change in threshold voltage. This results in an IGBT that can minimize the occurrence of latchup.

Claims (8)

In an insulated gate bipolar transistor integrated on a semiconductor substrate, a first conductive semiconductor substrate 10 connected to an anode electrode supplied with an operating current, and a second conductive semiconductor formed on the semiconductor substrate 10. An epitaxial layer 14, a first diffusion region 16 of the first conductivity type formed on the main surface of the epi layer 14, and a second conductive type agent formed in the first diffusion region 16; The channel of the first diffusion region 16 in the second diffusion region 18 and the first diffusion region 16 under the second diffusion region 18 so as to increase the latch-up current without changing the threshold voltage. The first conductive buried region 20 and the epitaxial layer 14 and the second diffusion region 18 are formed on a portion of the region excluding the region and have an impurity concentration higher than that of the first diffusion region 16. Formed over the top of the gate and in contact with the exposed surface of the first diffusion region 16 through the gate insulating film 24. The cathode electrode 30, which is positioned insulated over the gate electrode 26 and is in contact with the upper portion of the first diffusion region 16 and the second diffusion region 18, is formed. Insulated gate bipolar transistor, characterized in that provided. The first conductive type of claim 1, wherein the first conductive type is connected to the cathode electrode 30 and is interviewed with the first and second diffusion regions 16 and 18 and has a higher impurity concentration than the buried region 20. An insulated gate bipolar transistor further comprising three diffusion regions (22). 3. The insulating layer of claim 2, further comprising a second conductive buffer layer 12 having a higher impurity concentration than the epi layer 14 between the epi layer 14 and the semiconductor substrate 10. Gate bipolar transistor. 4. The insulated gate bipolar transistor according to claim 3, wherein the buried region (20) is in contact with a bottom surface of the second diffusion region (18). A method of manufacturing an insulated gate bipolar transistor, comprising: a first process of growing a second conductive epitaxial layer 14 on a first conductive semiconductor substrate 10, and an element on the epitaxial layer 14 A second process of forming a first diffusion region 16 by implanting and diffusing a first conductive impurity to form an opening by patterning and forming an opening after forming a separator; and forming a buried region in the first diffusion region 16 A third process of buried in the first diffusion region 16 by ion implantation of a first conductivity type impurity for forming a first conductivity type buried region 20 with a higher concentration than the first diffusion region 16; A fourth process of forming a second diffusion region 18 on the buried region 20 by limiting an upper portion of the buried region 20 and implanting and diffusing a second conductive type ion; The epitaxial layer 14 and the second diffusion region 1 interposed between the exposed surface of the semiconductor layer and the gate insulating film 24. 8 and a cathode electrode 30 insulated from the gate electrode 26 and commonly connected to the first diffusion region 16 and the second diffusion region 18. Insulating gate bipolar transistor manufacturing method comprising the step of forming a sixth process. The method of claim 5, wherein the second process is to form a third diffusion region 22 of the first conductivity type having a higher impurity concentration than the first diffusion region 16, and then the third diffusion region 22. And forming a first diffusion region (16) to be interviewed. The method of claim 6, further comprising forming a second conductive buffer layer 12 having a higher impurity concentration than the epi layer 14 on the semiconductor substrate 10 before the first process. Method of manufacturing an insulated gate bipolar transistor, characterized in that. The method of claim 7, wherein the buried region (20) is formed to be in contact with the bottom surface of the second diffusion region (18).