KR0147709B1 - Data transfer control apparatus using single buffer and its method - Google Patents

Abstract

The present invention relates to an apparatus and a method for controlling data transfer between a small computer system interface (SCSI) bus and a peripheral storage device. In particular, the present invention relates to receiving and receiving data from a SCSI bus using a single ring buffer. The present invention relates to a data transfer control apparatus and method using a single buffer that sends data to a storage device or receives data from a peripheral storage device and simultaneously sends data to a SCSI bus.

Description

Data transmission control device and method using a single buffer

1 is a block diagram of a data transmission control apparatus using a single buffer according to the present invention

Figure 2 shows ring-buffered read and write registers and peripheral circuit diagrams.

3 is a block diagram of an FSM in a buffer control circuit.

4 is a flow chart of the FSM

* Explanation of symbols for main parts of the drawings

10: SCSI disk controller 12: Microprocessor

16: Disc interface 20: High speed disc

24: SCSI bus data control section 34: Ring buffer

37: disk data controller 38: error detection / correction

50: buffer control part

The present invention relates to an apparatus and a method for controlling data transfer between a small computer system interface (SCSI) bus and a peripheral storage device. In particular, the present invention relates to receiving data from a SCSI bus using a single ring buffer, A data transfer control apparatus and method using a single buffer for sending data to or receiving data from a peripheral storage device and simultaneously sending data to a SCSI bus.

The conventional data transmission control apparatus and method uses two buffers to transmit data in another buffer which has already received data while receiving data in one buffer. When the buffers receiving data are full and the buffers sending data are completely empty, the roles of each other are reversed.

However, as described above, two or more buffers are required to transmit data, and a problem arises in that a data block and a latency period resulting from a transfer rate difference between a SCSI bus and a peripheral storage device are taken.

In order to solve the problems of the prior art as described above, the present invention provides a single ring-buffer to simultaneously read and write a plurality of buffers, thereby unifying read-pointer and write-pointer. It is an object of the present invention to provide a data transfer control apparatus and method using a single buffer to define a difference as a threshold and adjust the difference to accommodate a transfer rate difference between a peripheral storage device and a SCSI bus.

In order to achieve the above object, a data transfer control apparatus using a single buffer according to the present invention includes a SCSI bus data controller which receives a SCSI bus signal and is connected through an external microprocessor and an internal control bus; A buffer control unit connected to the SCSI bus data control unit through a serial control bus to control data transmission via a buffer; A disk data control unit connected to the buffer control unit through a serial control bus, and transmitting and receiving data to and from a buffer through a buffer input bus and a buffer output bus; An error detection and correction unit connected to the disc data controller via a serial control bus, for encoding data sent to the disc interface and decoding a signal received from the disc interface; And a single buffer for inputting or outputting data to the SCSI bus data controller and the disk data controller under the control of the buffer controller.

In addition, the present invention provides a method for controlling data transfer between a SCSI bus and a disk memory using a finite state machine (FSM) and a ring-buffer, the method comprising: initializing the FSM to a pause state; A second step of resetting the pause state by determining whether there is a data transmission command and preparing for data transmission, and returning to the first step if not; Determines the signals that can be written to the ring buffer or the signals that can be read from the ring buffer, and stores the number of data blocks and the number of bytes per block from the SCSI bus in the specified counters. A third step of branching; A fourth step of decreasing the byte counter by one; A fifth step of checking whether an error has occurred on the SCSI bus and returning to step 1, and if there is no error, checking whether there is a data transfer request from the SCSI bus; A sixth step if the transfer request is not performed after the fifth step, and if there is a transfer request, a sixth step of reading one byte from the ring-buffer or writing one byte to the ring-buffer; Determining whether the value of the byte counter is zero after performing the sixth step, and branching to the fourth step if the value is not 0, and decreasing the block counter by one if it is zero; During the block data transfer, check whether the parity error occurred on the SCSI bus or the ring-buffer data bus. If an error occurs, return to step 1. If the error does not occur, check whether all blocks have been transferred. An eighth step of branching to a third step, if present; It is determined whether all data transmission procedures have been completed, and if the transmission procedures have been completed, the method returns to the first step, and otherwise comprises a ninth step branching to the third step.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4.

1 is a block diagram of a data transmission control apparatus using a single buffer according to the present invention, 10 is a SCSI disk controller (hereinafter referred to as SDC IC), 12 is a microprocessor, 16 is a disk interface unit, 20 is a high speed A disk, 24 denotes a SCSI bus data controller, 34 denotes a ring-buffer, 37 denotes a disk data controller, 38 denotes an error detection / correction, and 50 denotes a buffer controller.

As shown in the figure, the SDC IC 10 of the present invention is connected to the microprocessor 12 through the parallel bus 14. The microprocessor 12 manages the SCSI protocol, parity check, SDC IC 10, etc., which includes the initialization of the proposed method. The SDC IC 10 and the microprocessor 12 control the disk interface unit 16 via the parallel bus 14.

The disk interface 16 is connected to the high speed disk 20 via the serial bus 18. The high speed disk 20 stores data in rotating sectors and stores up to 512 bytes according to the SCSI standard. Data is transferred between the high speed disk 20 and the disk interface 16 via the data line of the serial bus 18. Data transmitted to the disk interface is connected to the SDC IC 10 via the output serial bus 40 and the input serial bus 42.

The other side of the SDC IC 10 is connected to the SCSI bus 22. The SCSI bus 22 ultimately sends data written to the high speed disk 20 and receives data read from the high speed disk 20. These data are usually transmitted at an integer multiple of the number of bytes stored in one sector of the high speed disk 20.

In the SDC IC 10, SCSI bus signals are connected to the SCSI bus data control unit 24, where a control signal connected to the internal control bus 23 and a buffer input bus 30 and a buffer output bus 32 are connected. Divided into data connected to the ring-buffer 34.

The interface signals of the disk interface 16 are connected to the error detection / correction circuit 38 via serial buses 40 and 42. The serial bit stream is transmitted to the error detection / correction circuit 38 via the serial bus 42 when the disk 20 sends data, and via the serial bus 40 when receiving data. The error detection / correction circuit encodes the data sent to the disk interface 16 and encodes the data received at the disk interface 16.

Error free data is transmitted between the error detection / correction circuit and the disk data control unit 37 via the serial buses 44 and 46. The disk data controller 37 exchanges data with the ring buffer 34 through the buffer input bus 30 and the buffer output bus 32. The disk data controller 37 includes converting serial data between the parallel buses 30 and 32 and the serial buses 44 and 46 into parallel data and converting the parallel data into serial data.

The control information of the disc data control unit 37 is connected to the internal control bus 23. The disk data control unit 37 is connected to the buffer control unit 50 via further serial control buses 48 and 49. The buffer controller 50 is connected to the SCSI bus data controller 24 via the serial control busses 52 and 54 and controls the ring buffer 34 with the control signal 55. Thus, the input and output of the control circuits 24, 37, 50 are commonly connected to the bus 14, the microprocessor 12 and the disk interface 16.

The buffer controller 50 controls the data transmission via the ring buffer 34, and causes the ring buffer 34 to perform data transmission and reception at the same time, and sets and calculates the threshold described below. .

The overall operation of the present invention has been described above.

Next, a description will be given of the buffer control section 50, which is an important part, and the ring-buffer 34 operating under the control thereof.

The ring buffer 34 is not limited in size but is considered to be composed of 512 bytes for convenience. Each byte must be specified to be able to write and read. On some time bases, it is possible to write data to the first byte and to read the contents of the kth byte at the same time. A buffer of this structure can be implemented in a known manner, for example a register file, but need not be limited to this implementation. To specify the data to be written to, write a 10-bit write register and call its contents i. To specify the byte containing the data to read, a 10-bit read register is placed and its contents are called k. The value (i-k) is defined as the threshold. It is apparent that the number of bits of the read designation register and the write designation register is determined according to the size of the buffer, and therefore it is not necessary to limit it to 10 bits. In the present invention, a read designation register and a write designation register larger by 1 bit than the size of the buffer of 512 bytes are used to make it easy to calculate (i-k) values.

For data transmission via the ring-buffer 34, as will be mentioned later, the initialization of the relevant devices is preceded. Herein, the read designation register and the write designation register are initialized, a method of operating as the data transmission proceeds, a threshold calculation method, and the like will be described with reference to FIG.

2 is a ring-buffer related read designation register and write designation register and a peripheral circuit diagram, in which the write designation register 101 and the read designation register 102 are initialized to have the same value. If the values of each register are i and k, respectively, they are initialized to be i = k. Here, i = k = 0 for convenience. Data transfer through ring-buffer 34 begins with first receiving data and writing to the ring-buffer. When the write operation is completed, the incrementer 103 is operated to increase the value of the write designation register 101 by 1, i.e., i = i + 1. The calculator 105 calculates a difference i-k between the value of the write designation register 101 and the value of the read designation register 102. The user-specified register 107 stores a value set by the user. The first comparator 106 compares the result of the operator 105 with the value of the user-specified register 107 to obtain data from the ring-buffer 34. A read enable signal 108 is outputted to enable reading of the signal. If the result value of the operator 105 is greater than or equal to the value of the user specified register 107, the read enable signal 108 is generated.

Until the read enable signal 108 is generated, only the operation of writing to the ring-buffer 34 proceeds, so that the value of the read designation register 101 remains unchanged. When the read enable signal 108 occurs, data read from the ring-buffer 34 becomes possible, and the incrementer 104 operates by reading one byte of data, increasing the value of the read designation register 102 by one. , K = k + 1. The write designation register 101 acts like a binary increment counter in combination with the incrementer 103. Since the read designation register 102 also performs the same operation in combination with the incrementer 104, reading or writing as much data as the buffer size causes the most significant bit value of the registers 101 and 102 to be zero while reading or writing as much data as the next buffer size. Keeps changing from 1 to 1, or from 1 to 0.

Therefore, the threshold value storage device 111 is placed so that it is easy to calculate the difference between the write designation register 101 value and the read designation register 102 value by the operator 105, which is the most significant bit value of the write designation register 101. Is 0 and the most significant bit value of the read designation register 102 is changed to 1 so that the most significant bit of the write designation register 101 can be changed to 1 so that the most significant bit of the read designation register 102 can be changed to 0. Generate signal 112.

The second comparator 109 generates a write-hold signal 110 to prevent the data previously stored from being overwritten with other data before being read. If the second comparator 109 is equal to the lower 9-bit value of the write designation register 101 and the read designation register 102, the write operation is stopped.

The buffer controller 50 controls data transfer between the SCSI bus 22 and the high speed disk 20 through the ring buffer 34. In the buffer controller 50, a fine state machine (hereinafter referred to as an FSM) 200 is provided to control data transfer between the SCSI bus 22 and the disk data controller 37.

3 is a block diagram of the FSM 200. As illustrated, the FSM 200 includes a SCSI transmission signal, a SCSI reception signal, and a transfer to / from disk terminated (term) signal. , Error type (SEQRES) signal for SCSI subsystem error, Buffer Parity Error (SBPER) signal, SCSI Data Bus Parity Error (SDBPER) signal, read enable signal 108, write wait signal 110 It has 10 inputs: block counter = 0 (EOP) and SCSI bus data transfer request (SREQLS) signals.

In addition, the FSM 200 may include a bus buffer inactive signal; Storing the number of transmitted data blocks and the number of bytes per block in a designated counter (LDBTCT); Block counter decrement (DBLKC) signal; Bus byte counter decrement (DSBC) signal; A sequence end signal (RSTSR); And six outputs of bus state machine active (SSMACT).

Operation of the FSM 200 having the above input and output is as shown in the flowchart of FIG.

In the present invention, the state diagram of the FSM 200 is not separately defined, since the FSM that can be implemented from the following description may be various and also having related knowledge, one of them can be easily selected and implemented. to be. In other words, the method and the result of implementing the following description do not limit the FSM defined in the present invention.

A method of transferring data between the SCSI bus 22 and the ring buffer 34 will be described with reference to FIGS.

The microprocessor 12 initializes the entire data transmission control method 300 and automatically performs sequential operation once initialized. Subsequently, Pause = 1 of the FSM 200 is set (302) to check whether a SCSI data transfer command is issued. Check the SCSIREC command (304) and if it is a command (305), reset it to pose = 0 along the path (306) if it does not (331) check if the SCSI SEND command was issued along the path (360) , 361 resets pose = 0 along the path (362). Otherwise, set pose = 1 along the path (333) and (391) (302).

First, the case where the SCSIREC command is received at 304 is described. Along path 305, 306 outputs a pause = 0 indicating that there is data transmission. Next, at 308 along the path 307, the number of data blocks transmitted and the number of data bytes per block are written to the counter 1 and the counter 2 in the buffer control unit 50, respectively. If path 310 is reached along 310, signal 108 is generated, i.e., the threshold is greater than the value set in user-specified register 107, and thus the SCSI bus data control unit from the ring-buffer through buffer output bus 32; 24) determine whether the data can be read. Otherwise perform TERM along paths 335 and 391 or wait to 310 along path 337.

If it is determined at 310 that the signal 108 has occurred, then reach 314 along path 313 to decrement counter2 by one and if SEQRES does not occur at 316 along path 315, path 317 ) Determine the next performance according to SREQLS at 318. If SEQRES has occurred at 316, it is reset along paths 339 and 391 to reach 302 in a standby state. At 318, if SREQLS has not been generated, the SCSI bus data controller 24 waits along path 341 until it is ready to receive data, and if SREQLS is generated, along path 319 (320). 1-byte data is sent to the SCSI bus data control section 24 at the timing given by " Then, it is determined whether data of one block is transmitted at 322 along the path 321. If all data of one block is not transmitted, one-byte data transmission is repeated along the paths 343 and 309. If the data transmission of one block is completed, the block count is 1 at 324 along the path 323. Decrease by.

At 326 along path 325, a parity error has occurred during data transfer (SDBPER = 1), and if an error has occurred, it is reset along paths 345 and 391 to reach standby state 302. . Otherwise, it is determined whether there are any remaining data blocks at 328 along path 327, and if so, repeats the transmission along paths 347 and 309; otherwise, along path 329 (330). Determines if the SCSIREC procedure has finished. If SCSIREC is not terminated, a new SCSIREC is performed along paths 349 and 307; otherwise, a standby state is performed along paths 351 and 391.

Next, a case where the SCSISEND command is received at 360 will be described. Its overall implementation is similar to SCSIREC, so it only explains the differences between the two commands. First, the SCSISEND command receives data from the SCSI bus 22 and writes the data to the ring buffer 34. Therefore, at 366, the signal 110 has occurred, i.e., a space in which the data can be written without first overwriting the data waiting to be sent to the ring-buffer 34 and waiting to be transferred to the high speed disk 20 (ring-buffer). Examine the remaining (34). In operation 380, it may be determined that a parity error has occurred during transmission of the data block transmitted to the SBPER, that is, the ring buffer 34, and branches to the appropriate path.

As described above, the present invention replaces the conventional multiple buffers with a single ring-buffer, modifies the data transmission method to fit a single ring-buffer, and implements a read designation register and a write designation register related circuit according to the use of the ring buffer. . In particular, thresholds can be used to reduce latency between data blocks resulting from differences in SCSI bus and disk transfer rates. That is, the use range can be widened by reducing the number of buffers and smoothing the buffer of the difference in transmission speed than the conventional method.

Claims (5)

A SCSI bus data controller configured to receive a SCSI bus signal and be connected through an external microprocessor and an internal control bus; A buffer control unit connected to the SCSI bus data control unit through a serial control bus to control data transmission via a buffer; A disk data control unit connected to the buffer control unit via a serial control bus and transmitting and receiving data to and from a buffer through a buffer input bus and a buffer output bus; An error detection and correction unit connected to the disc data control unit via a serial control bus, for encoding data sent to the disc interface and for decoding a signal received from the disc interface; And a single buffer for inputting or outputting data to the SCSI bus data control unit and the disk data control unit under control of the buffer control unit. 2. The apparatus of claim 1, wherein the buffer control unit comprises: threshold calculation means for obtaining a difference value between two registers by adding one bit to each of the write designation register and the read designation register; Calculating means for obtaining a difference between a read designated register value and a write designated register value from the threshold value calculating means; First comparison means for generating a signal capable of preventing overwriting of data by comparing values of the read and write registers; And a second comparison means for generating a signal capable of reading data from a single buffer by comparing a result value of the calculation means with a value set by the user. The apparatus of claim 1, wherein the single buffer is a ring buffer. 4. The apparatus of claim 1 or 3, wherein the ring-buffer further comprises: threshold calculation means for obtaining a difference value between the two registers by adding one bit to the write designation register and the read designation register, respectively; Calculating means for obtaining a difference between a read designated register value and a write designated register value from the threshold value calculating means; First comparison means for generating a signal capable of preventing overwriting of data by comparing values of the read and write registers; And a second comparison means for generating a signal capable of reading data from a single buffer by comparing a result value of the calculation means with a value set by the user. A method of controlling a data transfer between a SCSI bus and a disk memory by a finite state machine (FSM), comprising: a first step of initializing the FSM to a pause state; A second step of resetting the pause state by determining whether there is a data transmission command and preparing for data transmission, and returning to the first step if not; The signal that can be written to the ring buffer or the signal that can be read from the ring buffer is judged, and the number of data blocks and the number of bytes per block are stored in the designated counter from the SCSI bus, and both signals are not generated. A third step of branching; A fourth step of decreasing the byte counter by one; A fifth step of checking whether an error has occurred on the SCSI bus and returning to step 1 if an error has occurred, and checking whether there is a data transfer request from the SCSI bus if the error has not occurred; A sixth step if the transfer request is not performed after the fifth step, and if there is a transfer request, a sixth step of reading one byte from the ring-buffer or writing one byte to the ring-buffer; Determining whether the value of the byte counter is zero after performing the sixth step, and branching to the fourth step if the value is not 0, and decreasing the block counter by one if it is zero; During the block data transfer, check whether the parity error occurred on the SCSI bus or the ring-buffer data bus. If an error occurs, return to step 1. If the error does not occur, check whether all blocks have been transferred. An eighth step of branching to a third step, if present; And a ninth step of returning to the first step if the transfer step is completed and branching to the third step if it is determined that all data transfer procedures have been completed.