KR0147428B1 - High integrated semiconductor device and the manufacturing method thereof - Google Patents
High integrated semiconductor device and the manufacturing method thereofInfo
- Publication number
- KR0147428B1 KR0147428B1 KR1019940037517A KR19940037517A KR0147428B1 KR 0147428 B1 KR0147428 B1 KR 0147428B1 KR 1019940037517 A KR1019940037517 A KR 1019940037517A KR 19940037517 A KR19940037517 A KR 19940037517A KR 0147428 B1 KR0147428 B1 KR 0147428B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor substrate
- insulating film
- gate
- source
- oxide film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000002955 isolation Methods 0.000 claims abstract description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 6
- 239000012212 insulator Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 239000007943 implant Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0151—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Landscapes
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 버즈빅에 의한 활성영역의 감소와 필드산화막과 주변의 활성영역과의 단차 발생을 방지하고, 또한 종래의 SOI(Silicon On Insulator) 소자가 가지는 장점을 유지하면서 종래 SOI 소자의 단점으로 지적되는 킨크 효과를 방지할 수 있는 고집적 반도체 소자 및 그 제조방법을 제공하고자 하는 것으로, 이를 위해 본 발명의 고집적 반도체 소자는, 소자분리절연막이 형성된 반도체기판; 상기 반도체기판에 채널을 유기하기 위하여, 상기 반도체기판 상에 형성된 게이트 전극과 상기 반도체기판 내에 형성된 소스/드레인 접합을 갖는 MOSFET; 및 상기 소스/드레인 접합에 접하면서 상기 소자분리절연막으로부터 상기 소스/드레인 하부의 상기 반도체기판 내로 확장되어 형성되며, 상기 MOSFET의 채널하부에서 오픈부를 갖는 매몰절연막을 포함하여 이루어진다. 그리고, 상기 매몰절연막은 상기 반도체기판의 활성영역 가장자리에서 상기 소자분리절연막과 접하여 형성된다.The present invention prevents the reduction of the active region and the step difference between the field oxide film and the surrounding active region by Buzzvik, and also points out the disadvantages of the conventional SOI device while maintaining the advantages of the conventional silicon on insulator (SOI) device. To provide a highly integrated semiconductor device and a method of manufacturing the same, which can prevent the kink effect, To this end, the integrated semiconductor device of the present invention, a semiconductor substrate formed with a device isolation insulating film; A MOSFET having a gate electrode formed on the semiconductor substrate and a source / drain junction formed in the semiconductor substrate to induce a channel to the semiconductor substrate; And a buried insulating film formed extending from the device isolation insulating film into the semiconductor substrate under the source / drain while being in contact with the source / drain junction and having an open portion under the channel of the MOSFET. The buried insulating film is formed in contact with the device isolation insulating film at the edge of the active region of the semiconductor substrate.
Description
제1a도 및 제1b도는 본 발명의 제1실시예에 따른 반도체소자 제조과정을 나타내는 단면도.1A and 1B are cross-sectional views illustrating a semiconductor device manufacturing process according to the first embodiment of the present invention.
제2a도 내지 제2c도는 본 발명의 제2실시예에 따른 반도체소자 제조과정을 나타내는 단면도.2A through 2C are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
제3a도 내지 제3c도는 본 발명의 제3실시예에 따른 반도체소자 제조과정을 나타내는 단면도.3A through 3C are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.
제4도는 종래의 SOI 소자 구조를 나타내는 단면도.4 is a cross-sectional view showing a conventional SOI device structure.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12,38 : 감광물질11 silicon substrate 12,38 photosensitive material
13,23,33 : 제1차 실리콘 산화막 24 : 제1차 실리콘 질화막13,23,33: primary silicon oxide film 24: primary silicon nitride film
25 : 제2차 실리콘 질화막 36 : 게이트 산화막25: secondary silicon nitride film 36: gate oxide film
37 : 다결정 실리콘 39 : 제2차 실리콘 산화막37 polycrystalline silicon 39 secondary silicon oxide film
40 : 소스/드레인 접합40: source / drain junction
본 발명은 고집적 반도체 소자 및 그 제조 방법에 관한 것이다.The present invention relates to a highly integrated semiconductor device and a method of manufacturing the same.
통상적으로, 반도체 소자 제조시 소자분리 공정을 수행함에 있어, 실리콘기판을 선택적으로 국부산화시키는 LOCOS(Local Oxidation of Silicon) 공정이 널리 이용되고 있다.In general, in performing a device isolation process in manufacturing a semiconductor device, a LOCOS (Local Oxidation of Silicon) process for selectively localizing a silicon substrate is widely used.
그런데, 산화공정에 의한 필드산화막 형성시에 발생하는 버즈빅(Bird's Beak)에 의한 활성영역의 감소와 필드산화막과 주변의 활성영역과의 단차 발생이 필연적으로 발생되므로, 이를 방지하기 위한 소자분리 방법이 절실히 요구된다.However, since the reduction of the active area and the step difference between the field oxide film and the surrounding active area occur inevitably due to the Bird's Beak generated during the formation of the field oxide film by the oxidation process, an element isolation method for preventing this This is desperately required.
한편, 제4도는 종래의 SOI(Silicon On Insulator) 소자 구조를 나타내는 단면도로서, 도면에 도시된 바와 같이 SOI 소자는 매몰된 산화막(42)이 형성된 실리콘 기판(41a,41b)을 사용하여 트랜지스터와 같은 소자를 구성한 소자이다.4 is a cross-sectional view illustrating a conventional silicon on insulator (SOI) device structure. As shown in the drawing, the SOI device is a transistor-like device using silicon substrates 41a and 41b in which an oxide film 42 is buried. It is the element which comprised the element.
그런데, 종래의 SOI 소자는 도면에 도시된 바와 같이, 필드산화막(43) 및 매몰 산화막(42)에 의해 3차원적으로 소자분리가 이루어지므로 소자분리특성이 우수하고, 소스/드레인(S/D) 접합 커패시턴스를 줄임으로써 소자의 동작속도를 향상시킬 수 있으며, 소스/드레인(S/D)의 공핍층 면적을 줄임으로써 숏채널효과를 감소시킬 수 있게 된다는 장점을 가지는 반면에, 도면에 도시된 바와 같이 트랜지스터의 몸체(Body)(41b)가 인접한 다른 트랜지스터(소자)의 몸체와 완전히 분리되어 있으므로 웰 바이어스(Well Bias)를 가하지 못함으로 인해 발생하는 킨크(Kink) 효과와 같이 소자의 정상적인동작에서 벗어난 현상이 발생될 수 있다.However, in the conventional SOI device, as shown in the drawing, since the device isolation is performed in three dimensions by the field oxide film 43 and the buried oxide film 42, the device isolation characteristics are excellent, and the source / drain (S / D By reducing the junction capacitance, the operation speed of the device can be improved, and the short channel effect can be reduced by reducing the depletion layer area of the source / drain (S / D). As described above, the body 41b of the transistor is completely separated from the body of another adjacent transistor (device), and thus, in the normal operation of the device, such as the kink effect caused by the failure of the well bias. Deviation may occur.
따라서, 본 발명은 버즈빅에 의한 활성영역의 감소와 필드산화막과 주변의 활성영역과의 단차 발생을 방지하고, 또한 종래의 SOI(Silicon On Insulator) 소자가 가지는 장점을 유지하면서 종래 SOI 소자의 단점으로 지적되는 킨크 효과를 방지할 수 있는 고집적 반도체 소자 및 그 제조 방법을 목적으로 한다.Accordingly, the present invention prevents the reduction of the active region due to Buzzvik and the generation of the step difference between the field oxide layer and the active region around it, and the disadvantages of the conventional SOI device while maintaining the advantages of the conventional silicon on insulator (SOI) device. An object of the present invention is to provide a highly integrated semiconductor device capable of preventing the kink effect, and a method of manufacturing the same.
상기 목적을 달성하기 위한 본 발명의 고집적 반도체 소자는, 소자분리절연막이 형성된 반도체기판; 상기 반도체 기판에 채널을 유기하기 위하여, 상기 반도체기판 상에 형성된 게이트 전극과 상기 반도체기판 내에 형성된 소스/드레인 접합을 갖는 MOSFET; 및 소스/드레인 접합에 접하면서 상기 소자분리절연막으로부터 상기 소스/드레인 하부의 상기 반도체 기판 내로 확장되어 형성되며, 상기 MOSFET의 채널 하부에서 오픈부를 갖는 매몰절연막을 포함하여 이루어진다. 그리고, 상기 매몰절연막은 상기 반도체 기판의 활성영역 가장자리에서 상기 소자분리절연막과 접하여 형성된다.A highly integrated semiconductor device of the present invention for achieving the above object is a semiconductor substrate formed with a device isolation insulating film; A MOSFET having a gate electrode formed on the semiconductor substrate and a source / drain junction formed in the semiconductor substrate to induce a channel in the semiconductor substrate; And a buried insulating film formed extending from the device isolation insulating film into the semiconductor substrate below the source / drain while being in contact with the source / drain junction and having an open portion under the channel of the MOSFET. The buried insulating film is formed in contact with the device isolation insulating film at the edge of the active region of the semiconductor substrate.
또한, 본 발명의 반도체 소자 제조방법은, 반도체 기판에 국부적으로 산소 이온주입 및 열처리를 실시하여 필드산화막을 형성하는 단계; 상기 반도체기판 상에 게이트 절연막 및 게이트전도막을 형성하는 단계; 상기 게이트전도막을 게이트 패턴으로 패터닝하기 위하여 상기 게이트전도막 상에 게이트 마스크 패턴을 형성하는 단계; 상기 게이트 마스크 패턴을 식각마스크로하여 상기 게이트전도막을 식각하는 단계; 상기 게이트 마스크 패턴 및 상기 필드산화막을 마스크로하여 상기 반도체 기판 내에 산소를 이온주입하는 단계; 상기 게이트 마스크 패턴을 제거하고 열처리하여 상기산소가 주입된 반도체기판을 매몰산화막으로 형성하는 단계; 및 이온주입에 의해 상기 매몰산화막과 상기 반도체기판 표면 간에 소스/드레인 접합을 형성하는 단계를 포함하여 이루어진다. 바람직하게 상기 게이트 마스크 패턴은 포토리소그라피 공정에 의해 형성된 포토레지스트 패턴으로 형성한다.In addition, the method of manufacturing a semiconductor device of the present invention comprises: forming a field oxide film by performing oxygen ion implantation and heat treatment on a semiconductor substrate; Forming a gate insulating film and a gate conductive film on the semiconductor substrate; Forming a gate mask pattern on the gate conductive film to pattern the gate conductive film into a gate pattern; Etching the gate conductive layer using the gate mask pattern as an etching mask; Implanting oxygen into the semiconductor substrate using the gate mask pattern and the field oxide film as a mask; Removing the gate mask pattern and performing heat treatment to form the oxygen-implanted semiconductor substrate as a buried oxide film; And forming a source / drain junction between the buried oxide film and the surface of the semiconductor substrate by ion implantation. Preferably, the gate mask pattern is formed of a photoresist pattern formed by a photolithography process.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
먼저, 제1a 도 및 제1b도는 O2임플란트 및 열처리에 의한 필드산화막이 제조과정을 나타내는 공정 단면도로서 각 단계를 설명하면 다음과 같다.First, Figures 1a and 1b is a cross-sectional view showing the manufacturing process of the field oxide film by O 2 implant and heat treatment will be described as follows.
제1a도는 실리콘 기판(11) 상부에 마스크를 사용하여 산화막을 형성할 부분 이외에 감광물질(12)을 형성한 후, O2임플란트를 한 후의 단면도이고, 제1b도는 실리콘 기판(11)에 주입된 산소(O2)를 열처리를 통해 실리콘 산화막(13)으로 만든 후의 단면도이다. 이와 같이 O2임플란트를 이용하여 필드산화막을 형성함으로써 기존의 산화막공정에 의한 산화막 형성시 발생되는 버즈빅 형상에 의한 활성영역의 감소를 없애고 또한 활성영역과 필드산화막과의 단차도 없앨 수 있다.FIG. 1A is a cross-sectional view after the photosensitive material 12 is formed on the silicon substrate 11 in addition to the portion where an oxide film is to be formed using the mask, and then an O 2 implant is formed. FIG. 1B is injected into the silicon substrate 11. oxygen (O 2) it is a sectional view after made of a silicon oxide film 13 through heat treatment. By forming the field oxide film using the O 2 implant as described above, it is possible to eliminate the decrease of the active area due to the buzz big shape generated when the oxide film is formed by the conventional oxide film process and also eliminate the step between the active area and the field oxide film.
다음, 제2a도 내지 제2c도는 소자분리 마스크의 측벽에 스페이서를 형성한 후, O2임플란트 및 열처리에 의해 필드산화막을 형성하는 제조과정을 나타내는 단면도로서 각 단계를 설명하면 다음과 같다.Next, FIGS. 2A to 2C are cross-sectional views illustrating a manufacturing process of forming a field oxide film by forming an spacer on a sidewall of an isolation mask and then performing an O 2 implant and heat treatment.
제2a도는 실리콘 기판(21) 상부에 산화막을 형성할 부분 이외에 제1차 실리콘 질화막(24)을 형성한 후, 제2차 실리콘 질화막을 사용하여 제1차 실리콘 질화막 측면에 스페이서(25)를 형성한 후의 단면도이다. 이때 형성되는 제2차 실리콘 질화막은 이후에 형성될 필드산화막의 영역을 줄임으로써 활성영역을 증가시킬 수 있게 한다. 제2b도는 제1차 실리콘 질화막 및 제2차 실리콘 질화막에 의해 덮히지 않은 실리콘 기판(21)에 O2임플란트를 한 후의 단면도이고, 제2c도는 열처리를 통해 산소 이온주입부위를 실리콘 산화막(23)으로 만든 후의 단면도이다.FIG. 2A illustrates the formation of the first silicon nitride film 24 in addition to the portion of the silicon substrate 21 on which the oxide film is to be formed, and then the spacer 25 is formed on the side of the first silicon nitride film using the second silicon nitride film. This is a cross section after. The secondary silicon nitride film formed at this time can increase the active area by reducing the area of the field oxide film to be formed later. FIG. 2B is a cross-sectional view after the O 2 implant is applied to the silicon substrate 21 not covered by the primary silicon nitride film and the secondary silicon nitride film. FIG. The cross-sectional view after making.
본 발명은 이상에서 설명한 바와 같이, 산소 이온주입 및 열처리에 의해 버즈빅이 거의 발생되지 않는 소자분리막을 형성하는 동시에, 기존의 SOI 소자가 가지고 있는 장점을 그대로 구현하면서 기존의 SOI 소자가 갖는 단점인 킨크 효과를 방지할 수 있는, 반도체 소자 및 그 제조 방법을 제공하고자 하는 것으로, 이를 제3a도 내지 제3c도를 참조하여 구체적으로 설명한다.As described above, the present invention provides a device isolation film which hardly generates buzz big by oxygen ion implantation and heat treatment, and at the same time realizes the advantages of the existing SOI device while maintaining the advantages of the existing SOI device. It is intended to provide a semiconductor device and a method of manufacturing the same, which can prevent the kink effect, which will be described in detail with reference to FIGS. 3A to 3C.
먼저, 제3a도는 앞서 설명한 바와 같은 방법으로 실리콘기판(31)에 필드산화막(33)을 형성한 후, 게이트 산화막(36)과 예컨대 다결정실리콘막(37)과 같은 게이트전도층을 증착하고, 게이트 마스크로서 감광물질(38)을 형성한 다음, 다결정실리콘막을 식각한 상태에서, O2임플란트를 실시한 후의 단면도이다. O2임플란트시 그 에너지를 조절하여 산소 주입층은 예정된 소스 및 드레인 영역의 하부에 형성되도록 한다. 즉, 게이트 마스크(즉, 감광물질(38)) 및 필드산화막(33)이 O2임플란트시 마스크 역할을 하고 있으므로, 그 에너지를 조절하면 소스 및 드레인이 형성될 영역 하부에 산소주입층을 형성할 수 있다.First, in FIG. 3A, the field oxide film 33 is formed on the silicon substrate 31 in the same manner as described above. Then, the gate oxide layer 36 and the gate conductive layer such as the polysilicon film 37 are deposited, and the gate is formed. as a mask to form a photosensitive material 38. in the following, the etched polysilicon film state, O is a sectional view after subjected to the second implant. The energy is controlled during the O 2 implant so that an oxygen injection layer is formed below the predetermined source and drain regions. That is, since the gate mask (that is, the photosensitive material 38) and the field oxide film 33 serve as a mask for the O 2 implant, the oxygen injection layer may be formed under the region where the source and drain will be formed by controlling the energy. Can be.
이어서, 제3b도는 제3a도에서 형성한 감광물질을 제거한 후, 열처리하여 실리콘 기판(31)의 산소 주입 영역을 실리콘 산화막(39)으로 만든 후의 단면도이고, 제3c도는 이온주입에 의해 소스 및 드레인 접합을 만든 후의 단면도이다.Subsequently, FIG. 3B is a cross-sectional view after removing the photosensitive material formed in FIG. 3A and heat treatment to make the oxygen injection region of the silicon substrate 31 into the silicon oxide film 39. FIG. 3C is a source and a drain by ion implantation. Sectional view after making a joint.
이상에서 설명한 바와 같이, 본 발명의 반도체 소자는 종래의 SOI 소자와는 달리, MOSFET의 채널을 제공하는 트랜지스터의 몸체(Body) 부분 아래에서 실리콘 산화막(39)이 열려있기 때문에 웰 바이어스(Well Bias)를 용이하게 가할 수 있어 킨크 효과 등을 방지할 수 있다. 또한, 소스/드레인(40)의 하부가 실리콘 산화막(39)과 접촉되어 있어 소스/드레인 접합 커패시턴스를 줄일 수 있는 등 종래의 SOI 소자가 갖는 장점을 그대로 유지하고 있다. 즉, 본 발명은 SOI 소자의 장점을 유지하면서 SOI 소자의 단점을 없애준다.As described above, the semiconductor device of the present invention is different from the conventional SOI device because the silicon oxide film 39 is opened under the body portion of the transistor providing the MOSFET channel. Can be easily added to prevent the kink effect. In addition, the lower part of the source / drain 40 is in contact with the silicon oxide film 39 to reduce the source / drain junction capacitance, thereby maintaining the advantages of the conventional SOI device. That is, the present invention eliminates the disadvantages of the SOI device while maintaining the advantages of the SOI device.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
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| KR100400918B1 (en) * | 2001-06-28 | 2003-10-10 | 동부전자 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR100727525B1 (en) * | 2004-08-26 | 2007-06-14 | 샤프 가부시키가이샤 | A manufacturing method of a semiconductor device, and a semiconductor device |
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| KR100727525B1 (en) * | 2004-08-26 | 2007-06-14 | 샤프 가부시키가이샤 | A manufacturing method of a semiconductor device, and a semiconductor device |
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