KR0146305B1 - Automatic recognition method of main memory size - Google Patents

Abstract

The present invention relates to a method for automatically recognizing a main memory device size by automatically recognizing its entire size as the memory size of the main memory device of the system is changed in various ways, and the size according to various sizes of memory. In this case, a special setting is required according to the CPU so that the CPU can recognize that the memory size has changed. In the present invention, the CPU can change the total memory size according to the memory size change of the main memory device. By providing a program for automatically recognizing, the entire memory size of the DRAM can be automatically recognized so that only the memory size required can be used and no special setting is required.

Description

Automatic recognition method of main memory size

1 is a configuration diagram of a memory map of a general CPU,

2 is an operation flowchart for automatic recognition of the main memory size of the present invention.

The present invention relates to a method for automatically recognizing the main memory size so that the total size is automatically recognized as the memory size of the main memory device of the system is variously changed so that no special setting is necessary.

1 shows a general memory map configuration of a central processing unit and an address corresponding thereto.

The central processing unit assigns an appropriate address to each part to control each part, that is, DRAM, VRAM, ROM, input / output, and the like. Addresses shown in the figures are binary.

Generally, Programmable Array Logic (PAL) is used to construct a memory map as shown in FIG. By the way, the memory map for the DRAM must be specially configured because the different sizes of memory can be used for each bank constituting the DRAM.

That is, each bank constituting the DRAM is composed of two, and each bank uses an 8-bit shim having the same memory size. In other words, one bank is composed of 16 bits.

Here, the first bank located at the initial address where the DRAM starts can use one of the 256 KB and 1 MB shims, and the second bank can be configured to follow the first bank and use one of 256 KB, 1 MB, and 4 MB.

Because of this, the minimum memory size of the first bank is 256KB, which is 512KB, or about 0.5MB, and the maximum memory size is 2MB, which is the combination of two 1MB.

Similarly, the second bank is at least 0 KB and at most 8 MB, so the total memory size is at least 0.5 MB and at most 10 MB.

As can be seen from the above, it can be seen that there must always be a memory in the first bank and not the second bank.

When changing the size according to the memory of various sizes as described above, it was necessary for a special setting according to the CPU so that the CPU can recognize that the memory size has changed.

In view of this, the present invention is characterized in that the central processing unit provides a program for automatically recognizing the total memory size according to the memory size change of the main memory device, so that no special setting is required.

In other words, the DRAM, the main memory device, is composed of two banks, and each bank is composed of two 8-bit SIMs having the same memory size. The first bank uses one of 256KB and 1MB SIMs, and the second bank. The SIM uses one of 256KB, 1MB and 4MB sims to recognize the total memory size from 0.5MB up to 10MB and automatically set the memory size of the first bank where the memory of the DRAM starts. Assuming 2MB, a first step of determining an initial expected address at which the second bank starts, a second step of inputting an arbitrary number other than the initial DRAM address and the initial address plus 512KB of the minimum memory size of the first bank; A value input again to the value input to the initial address in the second step and the value input to the initial address in the memory A third step of judging whether or not to coincide, a fourth step of inputting an arbitrary number to the initial address of the second bank determined by the memory size of the first bank determined in the third step, the value and the memory entered in the fourth step A fifth step of determining whether or not the value read back to the initial address is identical to the second address; a sixth step of storing the initial address of the second bank if the value is identical in the fifth step; and 512 KB from the start address of the second bank. A seventh step of inputting arbitrary data while increasing an address, and an eighth step of determining whether the value input in the seventh step and the value read back from the memory are identical.

If it does not match in the third step, it is determined that the first bank has 512 KB of memory, and 512 KB is added to the initial DRAM address of the second bank.

If there is no coincidence in the fifth step, there is no memory in the second bank, and the address into which arbitrary data is input in the fourth step becomes the total memory size.

If the data is not matched in the eighth step, the memory is recognized as an upper level of the address to which any data is input in the seventh step, and the address value increased in the seventh step becomes the total memory size.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a flowchart illustrating an operation of recognizing a total memory size varying according to a memory size of a shim mounted in each bank of a DRAM, which is a main memory device having a special configuration in a central processing unit.

Before describing the automatic recognition operation of the CPU, the DRAM will be described.

The DRAM is configured as in the central processing unit that constructs the memory map in the Programmable Array Logic (PAL) method, which is a general configuration: two banks, each bank of eight bits with the same memory size. Use a shim. In other words, one bank is composed of 16 bits.

Here, the first bank located at the initial address where the DRAM starts can use one of the 256 KB and 1 MB shims, and the second bank can be configured to follow the first bank and use one of 256 KB, 1 MB, and 4 MB.

As a result, the minimum memory size of the first bank is 256KB, which is 512KB, or about 0.5KB, and the maximum memory size is 2MB, which is two 1MB.

The address where each bank for such a memory is located is allocated as follows.

1) For the first bank

For 256KB Sim: Binary 0200 0000 ~ 023F FFFF

For 1MB Sim: Binary 0200 0000 ~ 02FF FFFF

2) For the second bank

① When there is 256KB shim in the first bank

For 256KB Sim: Binary 0240 0000 ~ 027F FFFF

In case of 1MB Sim: Binary 0240 0000 ~ 033F FFFF

For 4MB Sim: Binary 0240 0000 ~ 063F FFFF

②When there is 1MB shim in the second bank

For 256KB Sim: Binary 0300 0000 ~ 033F FFFF

In case of 1MB Sim: Binary 0300 0000 ~ 03FF FFFF

For 4MB Sim: Binary 0300 0000 ~ 06FF FFFF

As described above, a method for recognizing an address corresponding to each memory size will be described with reference to FIG.

In this case, in the programmable array logic (PAL) method, MEMSIZE is set to 0 when the memory size of the first bank is 2MB and 1 when 512KB.

First, assuming that there is a 1 MB shim in the first bank, the expected initial address (XX) of the second bank is equal to the initial address of the DRAM (DRAMBASE = binary 0200 0000) plus the home memory size (2 MB) of the first bank. (Step S1). Then, random numbers different from each other are inputted to the address obtained by adding the initial address (DRAMBASE) of the DRAM and 512 KB (step S2). 512 KB is the minimum memory size that can be loaded in the first bank. And each other arbitrary number is made into a binary number, and is mutually opposite, and makes it easy to recognize. For example, if you enter 0101 1010 1111 0000 (5AF0 in hexadecimal) and 1010 0101 0000 1111 (A50F in hexadecimal) in binary, it is easy to compare.

In the above, if the first bank has 256 KB instead of 1 MB shim, the data A50F input at the 512KB position from the first address is overwritten to the first address. Because the address starts at 0, in the first bank having a total of 512 KB of memory, there is no address at the location where 512 KB is added to the first address. Therefore, the data entered at the first address is erased and the overwritten data remains.

As a result, the data inputted to the initial address (DRAMBASE) of the first bank is read again to confirm whether or not the data 5AF0 inputted to the first address is matched in the step S2 (step S3). If it matches in step S3, the fact assumed in step S1 is correct, and the process enters the step of checking the memory size of the next second bank. If they do not match in step S3, it is confirmed that there is actually 256 KB because the fact assumed in step S1 is wrong. Therefore, it is confirmed that the 256 KB shim is attached to the first bank, and accordingly, the initial address XX of the second bank is determined to be 512 KB added to the initial address DRAMRAM of the DRAM (step S4).

On the other hand, when the memory size of the first bank is determined as described above, the memory size of the second bank should be checked. First, an arbitrary number 5AF0 is input to the initial address XX of the second bank (step S5). Then, the data inputted to the initial address XX of the second bank is read again to confirm whether it matches the data 5AF0 input in the step (step S5) (step S6).

If it does not match, there is no memory in the second bank, and the input data is destroyed because no address exists in the second bank. Thus, the initial address XX of the second bank becomes the entire memory of the DRAM.

If it matches in step S6, a memory exists in the second bank, and the initial address XX is stored (step S7). Then, random data 5AF0 is inputted from the value YY in which the initial address of the second bank is stored, increasing the address by 512 KB, which is the smallest memory size that can be loaded in the second bank (step S8). ). In step S8, the address YY to which the data 5AF0 is input is read again to confirm whether the input data and the input data 5AF0 match (step S9). If they match, the steps (S8, S9) are repeated again with the memory present. If it does not match, there is no more memory above the address YY increased in step S8, and the address YY increased in step S8 becomes the total memory size.

This will automatically recognize the total memory size of the DRAM.

As described above, according to the present invention, the entire memory size of the DRAM can be automatically recognized so that only the memory size necessary can be used, and accordingly, no special setting is required.

Claims (4)

The DRAM, a main memory device, consists of two banks, each bank consisting of two 8-bit shims with the same memory size. The shim in the first bank uses either 256KB or 1MB shim, and the shim in the second bank By using one of 256KB, 1MB and 4MB shims to recognize the total memory size that varies from 0.5MB up to 10MB and automatically set the memory size of the first bank where the memory of the DRAM starts is 2MB, the maximum memory size. A first step of determining an initial expected address at which the second bank starts, a second step of inputting an arbitrary number other than the initial DRAM address and the initial address plus 512 KB, which is the minimum memory size of the first bank, Read back the value input to the initial address in the second step and the value input to the initial address in the memory A third step of determining whether the values match, a fourth step of inputting an arbitrary number to an initial address of the second bank determined by the memory size of the first bank determined in the third step, and the value input in the fourth step And a fifth step of determining whether or not the value read back to the initial address from the memory is identical, a sixth step of storing the initial address of the second bank if the fifth step is identical, and starting from the start address of the second bank. And a seventh step of inputting arbitrary data while increasing the address by 512 KB, and an eighth step of determining whether the value input in the seventh step and the value read back from the memory match with each other. Automatic Recognition of Main Memory Size. 2. The main memory size according to claim 1, wherein if it does not match in the third step, it is determined that the first bank has 512 KB of memory, and the initial address of the second bank is set to 512 KB plus the initial DRAM address. Automatic recognition method. The method of claim 1, wherein if there is no coincidence in the fifth step, there is no memory in the second bank, and the address to which any data is input in the fourth step is the total memory size. The method of claim 1, wherein if the data is not matched in the eighth step, it is recognized that there is no memory above the address to which any data is input in the seventh step. Automatic recognition method of main memory size, characterized in that.