KR0143034B1 - Flash memory apparatus - Google Patents
Flash memory apparatusInfo
- Publication number
- KR0143034B1 KR0143034B1 KR1019940037295A KR19940037295A KR0143034B1 KR 0143034 B1 KR0143034 B1 KR 0143034B1 KR 1019940037295 A KR1019940037295 A KR 1019940037295A KR 19940037295 A KR19940037295 A KR 19940037295A KR 0143034 B1 KR0143034 B1 KR 0143034B1
- Authority
- KR
- South Korea
- Prior art keywords
- erase mode
- circuit
- flash memory
- erase
- row
- Prior art date
Links
- 238000001514 detection method Methods 0.000 claims description 9
- 238000012790 confirmation Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 238000012795 verification Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
Landscapes
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
본 발명은 플래쉬 메모리장치에 관한 것으로서 섹터소거모드시 페이지 모드형태의 소거모드확인을 통해 선별적인 로우별 소거모드 시행을 하도록 하여 제품의 신뢰성 향상과, 소거모드 시간을 단축시키도록 한 플래쉬 메모리 장치에 관한 것이다.The present invention relates to a flash memory device, which performs a selective row-by-row erase mode by checking a page mode type erase mode in a sector erase mode, thereby improving reliability of a product and reducing an erase mode time. It is about.
Description
제1도는 본 발명에 따른 플래쉬 메모리 장치의 회로도.1 is a circuit diagram of a flash memory device according to the present invention.
제2도 및 제 3 도는 제 1 도의 동작을 설명하기 위한 제 1 및 제 2 상세회로도.2 and 3 are first and second detailed circuit diagrams for explaining the operation of FIG.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:로우별 래치회로 및 워드라인 선택회로 2:소거모드확인 풀-업 회로1: Row-specific latch circuit and word line selection circuit 2: Erasure mode check pull-up circuit
3: 소거모드 검증회로 4:메모리셀군3: erase mode verification circuit 4: memory cell group
5:로우별 래치회로 6:워드라인 선택회로5: Latch Circuit by Row 6: Word Line Selection Circuit
본 발명은 플래쉬 메모리장치에 관한 것으로, 특히 섹터소거모드시 페이지 모드(page mode) 형태의 소거모드확인을 통해 선별적인 로우별 소거 모드 시행이 가능하도록 하고 테스트타임이 단축되도록 한 플래쉬 메모리 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device, and more particularly, to a flash memory device capable of selectively performing row-by-row erasing mode by checking a page mode erasing mode and reducing a test time. will be.
일반적으로 스텍 메모리셀(stack memory cell)을 이용하는 플래쉬 메모리(Flash memory)제품에 있어서, 종래의 소거모드 시행 알고리즘 인터페이스 회로에서는 임의의 섹터 및 블럭에 있는 모든 메모리셀을 프로그램한 후 소거모드를 시행하여 소거모드확인을 통해 그 결과를 검중한다. 이때 메모리셀이 소거모드 상태로 되어있지 않으면 계속해서 소거모드를 시행하게 되며 시행하는 과정에서 오버 이레이즈(Over erase)현상이 발생되어 제품의 신뢰성 및 동작에 문제점이 있고, 소거모드확인시 바이트모드(Byte mode)로 검증하므로써 소거모드확인시간이 많은 소비되는 단점이 있다.Generally, in a flash memory product using a stack memory cell, a conventional erase mode enforcement algorithm interface circuit performs an erase mode after programming all memory cells in an arbitrary sector and a block. Check the erase mode to check the result. At this time, if the memory cell is not in the erase mode, the erase mode continues to be executed. During the process, the over erase phenomenon occurs, causing problems in reliability and operation of the product. The verification in (Byte mode) consumes a lot of time to check the erase mode.
따라서 본 발명은 상술한 단점을 해결하기 위해 섹터소거모드시 페이지 모드 형태의 소거모드확인를 통해 선별적인 로우별 소거모드시행이 가능하도록 하고 테스트타임의 단축되도록한 플래쉬 메모리장치를 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a flash memory device which enables selective row-by-row erase mode execution and shortened test time by checking page mode erase mode in a sector erase mode. .
상술한 목적을 달성하기 위한 본 발명은 소거모드확인 풀-업 회로 및 소거모드 검증회로간에 접속되며 상기 소거모드 검증회로의 출력인 검출 신호에 따라 동작되는 로우별 래치회로 및 워드라인 선택회로를 입력으로 하는 메모리셀군으로 굿어되는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a row-by-row latch circuit and a word line selection circuit connected between an erase mode check pull-up circuit and an erase mode verify circuit and operated according to a detection signal which is an output of the erase mode verify circuit. Characterized in that the memory cell group to be good.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제 1 도는 본 발명에 따른 플래쉬 메모리장치의 회로도로서 동작을 설명하면 다음과 같다.1 is a circuit diagram of a flash memory device according to the present invention.
소거모드확인 풀-업회로(2) 및 소거모드검증회로(3) 사이에 메모리셀군(4)이 접속되며, 소거모드 검증회로(3)의 출력인 검출신호(S1)가 로우별 래치회로 및 워드라인선택회로(1)로 공급되도록 구성된 회로도로서, 소거모드확인에서 소거모드확인 풀-업회로(2) 및 소거모드 검증회로(3)에 의해 선택되어지는 임의의 워드라인(WL1)에 접속되어 있는 모든 메모리셀(MC11 내지 MC1n)의 소거모드 상태를 한꺼번에 검증한다. 이때 검증된 검출신호(S1)가 선택된 워드라인(WL1)에 래치(Latch)되어 다음의 소거모드에서 소거모드 시행여부를 결정해준다. 즉, 선택된 워드라인(WL1)에 접속되어 있는 모든 메모리셀(WC11 내지 WCC1n)이 소거모드상태로 되어 있으면, 소거모드확인시 소거모드확인 풀-업회로(2) 및 소거모드 검증회로(3)에 의해 출력되는 검출신호(S1)가 로우별 래치회로 및 워드라인선태고히로(1)에 래치된다. 이 래치된 검출신호(S1)에 의해 다음의 소거모드에서 소거모드 환경을 제공하지 않는다. 상대적으로 워드라인(WL1)에 접속된 어느한 메모리 셀이라도 프로그램 모드 상태로 되어있으면 소거모드 검증회로(3)의 검출신호(S1)에 의해 다음의 소거모드에서 워드라인(WL1)에 접속된 메모리셀(WL1 내지 WLn)에 소거모드 환경을 제공하여 소거모드 시행이 반복된다.The memory cell group 4 is connected between the erase mode check pull-up circuit 2 and the erase mode verify circuit 3, and the detection signal S1, which is an output of the erase mode verify circuit 3, is a latch circuit for each row; A circuit diagram configured to be supplied to the word line selection circuit 1, connected to an arbitrary word line WL1 selected by the erasing mode confirmation pull-up circuit 2 and the erasing mode verification circuit 3 in the erasing mode check. The erase mode states of all the memory cells MC11 to MC1n are verified at a time. At this time, the verified detection signal S1 is latched to the selected word line WL1 to determine whether to perform the erase mode in the next erase mode. That is, when all the memory cells WC11 to WCC1n connected to the selected word line WL1 are in the erase mode, the erase mode check pull-up circuit 2 and the erase mode verification circuit 3 at the time of erasing mode check are performed. The detection signal S1 outputted by the L1 is latched in the row-by-row latch circuit and the word line line height 1. The latched detection signal S1 does not provide an erase mode environment in the next erase mode. If any of the memory cells connected to the word line WL1 is in the program mode state, the memory is connected to the word line WL1 in the next erase mode by the detection signal S1 of the erase mode verification circuit 3. The erase mode trial is repeated by providing the erase mode environment for the cells WL1 to WLn.
제 2 도 및 제 3 도는 제 1 도의 ㅣ동작을 설명하기 위한 제 1 및 제 2 상세회로도로서 그 동작을 살펴보면 다음과 같다.2 and 3 are first and second detailed circuit diagrams for explaining the operation of FIG. 1 and the operation thereof is as follows.
소거모드확인에서 워드라인(WL1)이 선택되었다고 가정하면, 소거확인 인에이블 신호(R)에 동작되는 소거모드확인 풀-업 회로(2)인 NMOS트랜지스터(NU1 내지 NUn)가 메모리셀(MC11 내지 MC1n)에 전류를 공급한다.Assuming that the word line WL1 is selected in the erase mode check, the NMOS transistors NU1 through NUn, which are the erase mode check pull-up circuit 2 operated on the erase check enable signal R, are stored in the memory cells MC11 through. Supply current to MC1n).
이때 모든 메모리셀이 소거모드 상태로 되어 있으면 비트라인(BL1)은 저전위(Vss)가 된다. 또한 소거확인 인에이블 신호(R)에 따라 동작되는 NMOS트랜지스터(NΦ)가 턴온되고, 비트라인(BL1)을 입력으로 하는 NMOS 트랜지스터(NN1)가 턴오프되어 노드(x)의 검출신호(S1)가 고전위(Vcc)상태로 유지된다. 이때 유지된 고전위 검출신호(S1)는 워드라인 선택회로(6)에 의해 인에이블 되는 NMOS 트랜지스터(N1) 및 소거확인 인에이블 신호(R)에 따라 동작되는 NMOS 트랜지스터(N2)를 통해 노드(y)로 공급되며, 반전게이트소자(I1 및 I2) 및 PMOS 트랜지스터(P1)로 구성된 로우별 래치회로(5)에 의해 노드(z)의 전위가 저전위로 래치된다. 그러므로 다음의 소거모드시에 소거모드 환경을 워드라인(WL1)에 공급하지 않게된다. 반대로 소거모드확인시 워드라인(WL1)에 접속된 어느한 메모리셀이라도 프로그램 상태로 되어 있으며, 노드(x)가 저전위의 검출신호(S1)를 유지하게 되어 결국 노드(z)가 고전위로 래치되어 다음의 소거모드시에 소거모드 환경을 워드라인(WL1)에 공급하여 소거모드 시행을 반복하게 된다.At this time, when all the memory cells are in the erase mode, the bit line BL1 becomes the low potential Vss. In addition, the NMOS transistor NΦ operated according to the erasing confirmation enable signal R is turned on, and the NMOS transistor NN1 which inputs the bit line BL1 is turned off to detect the signal S1 of the node x. Is maintained at the high potential (Vcc) state. At this time, the held high potential detection signal S1 is connected to the node N through the NMOS transistor N1 enabled by the word line selection circuit 6 and the NMOS transistor N2 operated according to the erase confirmation enable signal R. supplied to y), the potential of the node z is latched to low potential by the row-by-row latch circuit 5 composed of the inverting gate elements I1 and I2 and the PMOS transistor P1. Therefore, the erase mode environment is not supplied to the word line WL1 in the next erase mode. On the contrary, any memory cell connected to the word line WL1 is in the program state when the erasure mode is checked, and the node x maintains the low potential detection signal S1, so that the node z is latched to the high potential. In the next erase mode, the erase mode environment is supplied to the word line WL1 to repeat the erase mode.
상술한 바와같이 본 발명에 의하여 섹터소거모드시 페이지모드 형태의 소거모드확인을 통해 선별적인 소거모드 시행을 하도록 하므로써 오버이레이즈(Over erase)현상을 감소시키므로 제품의 신뢰성을 향상시키고, 소거모드확인시간이 단축되어 원가절감에 큰 효과가 있다.As described above, by performing the selective erase mode through the page mode type erase mode check in the sector erase mode, the over erase phenomenon is reduced, thereby improving the reliability of the product and the erase mode check time. This shortening has a great effect on cost reduction.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037295A KR0143034B1 (en) | 1994-12-27 | 1994-12-27 | Flash memory apparatus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037295A KR0143034B1 (en) | 1994-12-27 | 1994-12-27 | Flash memory apparatus |
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| Publication Number | Publication Date |
|---|---|
| KR960025752A KR960025752A (en) | 1996-07-20 |
| KR0143034B1 true KR0143034B1 (en) | 1998-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019940037295A KR0143034B1 (en) | 1994-12-27 | 1994-12-27 | Flash memory apparatus |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980082679A (en) * | 1997-05-08 | 1998-12-05 | 김영환 | Data verification method of flash memory device |
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1994
- 1994-12-27 KR KR1019940037295A patent/KR0143034B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980082679A (en) * | 1997-05-08 | 1998-12-05 | 김영환 | Data verification method of flash memory device |
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| KR960025752A (en) | 1996-07-20 |
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