KR0142471B1 - Duty regulating circuit of the clock generator - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duty control circuit that is applied to a clock generator to allow a duty of a clock generated by a user to be variable in generating a clock in which a master clock and a synchronization are identical. A divider which receives a master clock and divides the predetermined number of times; A reference voltage generating circuit for generating a reference voltage having a magnitude corresponding to the external switching signal; An integrator for integrating a master clock to generate an integrated voltage having a slope corresponding to a reference voltage of the reference voltage generating circuit; Latch means for latching a clock output from the divider at a time when the integrator output voltage rises or falls; An exclusive inversion logical sum means for performing an exclusive inversion logic sum operation on the output clock of the divider and the output clock of the latching means to generate a clock having a high level period between the two clocks; By fine-tuning the duty of the clock with which synchronization is matched, it is possible to generate a clock whose exact rise time matches the fall time.

Description

Duty control circuit of clock generator

1 is a waveform diagram illustrating a duty control concept.

2 is a detailed circuit diagram of a duty control circuit according to an embodiment of the present invention,

3 is a waveform diagram of each part of FIG.

4 is a waveform diagram according to a change in the integral voltage slope of the operational amplifier of FIG.

5 is a circuit diagram for generating the reference voltage of FIG.

* Explanation of symbols for main parts of the drawings

1, 2: flip-flop 3, 5: inverting element

4: comparator 6: exclusive inverting logic element

R: Resistor C: Capacitor

The present invention relates to a duty control circuit that is applied to a clock generator. More specifically, a master clock generated in a clock generator and a clock having a different synchronization and a different synchronization may be used. It relates to a duty control circuit that allows the duty to be fine-tuned in generating.

A typical digital system requires a clock having various kinds of frequencies for operating circuit elements such as flip-flops. As a method for generating such a clock, each clock is generated by using an oscillator and one master. It is possible to divide the clock to generate the required clock.

In this method, the clock required by the above-mentioned division is generated. In order to generate a clock that is synchronized with the master clock of the clock generator and has a different duty, the master clock generated by the clock generator is divided by a division circuit. A method of properly dividing and signal processing the divided clock to generate a clock having an intended duty ratio has been used.

At this time, in order for the frequency of the clock which is synchronized with the master clock and the duty to be several megahertz (MHz), the frequency of the master clock must be at least 4 to 5 times the frequency, and the divided clock is properly signaled. shall.

In this way, if the rising time or falling time of the last generated clock is not correct, it may be necessary to change the master clock again to accurately adjust the duty ratio of the generated clock. do.

FIG. 1 shows a waveform diagram illustrating the duty control concept performed by this invention.

(A) of FIG. 1 is a master clock, and (b) of FIG. 1 is a waveform diagram of a clock with a duty controlled. As shown in FIG. 1, the synchronization between the master clock and the generated clock coincides, and the duty of the generated clock can be finely adjusted by the duty control circuit of the present invention.

SUMMARY OF THE INVENTION An object of the present invention is to solve a conventional technical problem as described above, and to provide a duty control circuit capable of finely adjusting the duty of a clock in generating a clock synchronized with a master clock of a clock generator.

As a means for achieving the above object, the configuration of the present invention comprises: a divider which receives a master clock and divides it a predetermined number of times; A reference voltage generating circuit for generating a reference voltage having a magnitude corresponding to an external switching signal; An integrator for integrating a master clock to generate an integrated voltage having a slope corresponding to a reference voltage of the reference voltage generating circuit; Latch means for latching a clock output from the divider at a time when the integrator output voltage rises or falls; And an exclusive inversion logic unit for performing an exclusive inversion logic operation on the output clock of the divider and the output clock of the latching means to generate a clock having a high level section of the overlapping section of the two clocks.

In the above configuration of the present invention, the reference voltage of the reference voltage generating circuit is variable by the user's switching signal selection, and the slope of the integral voltage is determined by the reference voltage.

Accordingly, since the inclination of the integrated voltage is variable so that the rising or falling time of the integrated voltage can be adjusted, the overlapping period between the output clock of the divider and the output clock of the latch circuit can be adjusted.

In addition, since the output clock of the exclusive inversion logic sum means is generated by an exclusive inversion logic sum operation, the synchronization with the divider output clock coincides with the synchronization signal, and thus the synchronization with the master clock which is the divider input signal.

As a result, the clock obtained by the exclusive inverse logic means can be synchronized with the master clock while its duty ratio can be adjusted by the user.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

2 is a detailed circuit diagram of a duty control circuit according to an embodiment of the present invention,

3 is a waveform diagram of each part of FIG.

4 is a waveform diagram according to a change in the integral voltage slope of the operational amplifier of FIG.

5 is a circuit diagram for generating the reference voltage of FIG.

First, the configuration of the duty control circuit according to the embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 2, the duty control circuit according to the embodiment of the present invention includes two flip-flops 1 and 2, an inverting element 3 and 5, an operational amplifier 4, a resistor R, and a capacitor ( C) and the exclusive inversion logic element 6.

The flip-flop 1 is applied with a master clock CLK to the clock terminal CK, and has an inverted output terminal to operate in a divider. ) Is connected to the input terminal (D).

The master clock CLK is applied to the inverting element 3, and the output terminal of the inverting element 3 is connected to the inverting terminal of the operational amplifier 4 with the resistor R therebetween. The reference voltage Vref generated by the reference voltage generator is applied to the non-inverting terminal of the operational amplifier 4, and a capacitor C is connected between the inverting terminal of the operational amplifier 4 and the output terminal.

The inverting element 5 is connected to the output terminal of the operational amplifier 4, and the output terminal of the inverting element 5 is connected to the clock terminal CK of the flip-flop 2. The input terminal D of the flip-flop 2 is connected to the output terminal Q of the flip-flop 1, and the input terminal of the exclusive inversion logic element 6 is the output terminal of the flip-flop 1 and the flip-flop 2. Connected to Q), an output signal OUT is provided at the output terminal of the exclusive inversion logic element 6.

The reset signal RN is applied to the reset terminal R of each of the flip-flops 1 and 2.

In the configuration of the duty control circuit according to the embodiment of the present invention described above, the flip-flop 1 is configured to operate with a divider and the flip-flop 2 is configured to operate with a latch. Therefore, the technical scope of this invention includes all the conventional configurations of the divider and latch which are not disclosed in the Example.

Next, the operation of the duty control circuit according to the embodiment of the present invention will be described with reference to FIGS.

The vertical axis of the waveform diagram shown in FIG. 3 is voltage and the horizontal axis is time.

When power is applied to start the operation of the circuit, a reset signal RN is applied to reset each flip-flop 1 and 2.

Next, the master clock CLK as shown in FIG. 3A is input to the clock terminal CK of the flip-flop 1 and the inverting element 3. Flip-flop (1) is the inverting output stage ( ) And the input terminal D are connected, and the output terminal voltage is inverted at each falling point of the master clock CLK. As a result, a clock divided by two of the master clock CLK is generated at the output terminal Q. The waveform of the two-divided output clock of the flip-flop 1 is shown in FIG. 3B and is applied to the input terminal D of the flip-flop 2. The frequency of dividing in the flip-flop 1 operating as a divider is not limited to the technical scope of the present invention.

The master clock CLK inverted by the inverting element 3 is applied to the inverting terminal of the operational amplifier 4 operating as an integrator.

The resistor R, the condenser C, and the operational amplifier 4 operate as integrators and perform an integral operation on the inverted master clock CLK. In FIG. 3C, the waveform of the integrated voltage provided at the output terminal of the operational amplifier 4 is shown. In this case, the slope of the integral voltage provided at the output terminal of the operational amplifier 4 is determined by the capacitance of the resistor R and the capacitor C and the reference voltage applied to the non-inverting terminal of the operational amplifier 4. In the present invention, the reference voltage is varied to adjust the slope of the integrated voltage, which will be described later with reference to FIG. 4 for generating the reference voltage.

In order to adjust the capacitance of the capacitor and the size of the resistor in order to change the slope of the integrated voltage, the error occurs during the semiconductor manufacturing process even though the proper capacitor value and the resistance value are set in consideration of the clock to be generated. The value of the resistance cannot be obtained.

The waveform of the integral voltage obtained by the integration operation of the operational amplifier 4 is as shown in Fig. 3C.

The output signal of the operational amplifier 5 is input to the inverting element 5 and inverted, and the signal obtained at the output terminal of the inverting element 5 is a square wave. That is, the output signal of the inverting element 5 becomes low level when the input voltage is less than or equal to the predetermined threshold voltage and becomes high level if it is more than or equal to the predetermined threshold voltage. At this time, the high level or low level transition time point of the output signal of the inverting element 5 changes according to the slope of the output signal of the operational amplifier 4. 4 shows a waveform diagram illustrating this.

The output signal of the inverting element 5 is applied to the clock terminal of the flip-flop 2, and in the flip-flop 2, the input terminal D at the time of falling from the high level to the low level of the output signal of the inverting element 5. The operation of latching data is performed.

The output terminal Q waveform of the flip-flop 2 is as shown in (d) of FIG. 3, which is a waveform whose predetermined time is delayed compared to the input terminal D waveform.

The output signals of the flip-flop 1 and the flip-flop 2 are input to the exclusive inversion logic element 6, and the exclusive inversion logic operation on the two signals is performed by the exclusive inversion logic element 6. .

The output signal of the exclusive inversion logic element 6 becomes high level at the high level overlapping interval of the two input signals, and its waveform is as shown in (e) of FIG.

The signal output from the exclusive inversion logic element 6 is a clock and has a waveform in which the duty is converted while synchronizing with the master clock. As described above, the duty of the exclusive inversion logic element 6 output signal is changed in accordance with the reference voltage of the operational amplifier 4.

The reference voltage is generated in the reference voltage generating circuit shown in FIG. 5, and a value thereof may be changed by a user's selection.

Next, the reference voltage generating circuit will be described with reference to FIG.

As shown in FIG. 5, PMOS (P-type Metal Oxide Semiconductor) transistors MP1 and MP2 having a configuration of a conventional current mirror are connected to the current source 8.

An NMOS N-type transistor MN1 is connected to the drain of the PMOS transistor MP2, and four NMOS transistors MN3 and MN5 having a mirror relationship with the NMOS transistor MN1. , MN7, MN9) are connected.

Four NMOS transistors MN2, MN4, MN6, and MN8, to which user inputs A0 to A3 are applied, are connected to the drains of the NMOS transistors MN3, MN5, MN7, and MN9. The drains of the NMOS transistors MN2, MN4, MN6, and MN8 are connected in common.

The PMOS transistor MP3 and the PMOS transistor MP4 having a mirror relationship are connected to the common contact of the NMOS transistors MN2, MN4, MN6, and MN8, and the drain of the PMOS transistor MP4 is It is connected to the current controlled voltage source (CCVS) 7.

At the output terminal of the current control voltage source 7 a reference voltage Vref is generated, which is provided to the non-inverting terminal of the operational amplifier 4.

Referring to the operation, in the drain of the PMOS transistor MP2, a current equal to the drain current of the PMOS transistor MP1 is generated by the mirror relationship.

Similarly, due to the mirror relationship between the NMOS transistor MN1 and the four NMOS transistors MN3, MN5, MN7, and MN9, the current having the same magnitude as the drain current of the NMOS transistor MN1 is each NMOS transistor MN3. , MN5, MN7, MN9).

At this time, whether the drain current of each of the NMOS transistors MN3, MN5, MN7, and MN9 is generated is determined according to the on / off states of the NMOS transistors MN2, MN4, MN6, and MN8 connected thereto.

The on / off state of each of the NMOS transistors MN2, MN4, MN6, and MN8 is determined by gate voltages A0 to A3 selected by the user. For example, when the user input A0 is at a high level, the NMOS transistor MN2 is turned on and a current flows in the drain of the NMOS transistor MN3.

Accordingly, the sum of the currents flowing in the paths of the respective NMOS transistors MN2, MN4, MN6, and MN8 flows in the drain of the PMOS transistor MP3.

The drain current of the PMOS transistor MP3 appears at the drain of the PMOS transistor MP4, and the drain current of the PMOS transistor MP4 is applied to the current control voltage source 7.

In the current control voltage source 7, a reference voltage Vref corresponding to the magnitude of the input current is generated.

In the reference voltage generating circuit shown in FIG. 5, since four user inputs A0 to A3 are four, four reference voltages Vref may be generated. However, the technical scope of the present invention is not limited thereto, and by increasing the user input and adding a corresponding NMOS transistor, a larger number of reference voltages can be generated.

As described above, in the embodiment of the present invention, a clock generator for generating a clock capable of matching an accurate rise time or fall time by varying the duty of the generated clock in generating a clock synchronized with the master clock. The duty control circuit of can be provided.

Claims (7)

A divider which receives a master clock and divides it a predetermined number of times; A reference voltage generating circuit for generating a reference voltage having a magnitude corresponding to the external switching signal; An integrator for integrating a master clock to generate an integrated voltage having a slope corresponding to a reference voltage of the reference voltage generating circuit; Latch means for latching a clock output from the divider at a time when the integrator output voltage rises or falls; And an exclusive inversion logic unit for generating a clock having an overlapping section of the two clocks as a high level section by performing an exclusive inversion logical sum operation on the output clock of the divider and the output clock of the latching means. Duty control circuit. 2. The duty cycle control device as claimed in claim 1, wherein the frequency divider comprises a flip-flop for generating a clock at the output terminal, the master clock being applied to the clock terminal and the inverting output terminal connected to the input terminal. Circuit. 2. The duty control circuit of claim 1, wherein the integrator integrates the voltage of the inverting terminal and comprises an operational amplifier such that the integrated voltage corresponds to a reference voltage applied to the non-inverting terminal. The duty control circuit according to claim 1, further comprising inverting means for inverting an output signal of the integrator between the integrator and the latching means. The input terminal according to claim 1 or 4, wherein the latching means causes the output of the inverting means to be applied to the clock terminal and the output of the divider to be applied to the input terminal. A duty canceling circuit comprising a flip-flop for latching a signal. 4. The apparatus of claim 1 or 3, wherein the reference voltage generating circuit comprises: first mirror means for causing a current generated from a current source to flow in a predetermined number of paths, respectively; Switching means connected to each of the paths to turn on / off current flow of each path according to a user input; Second mirror means connected to said switching means to provide a total of currents flowing in each path; And a current control voltage source connected to the second mirror means to generate a voltage corresponding to the sum of the currents flowing through the respective paths, and to provide the generated voltage to the non-inverting terminal of the operational amplifier. Duty control circuit. 7. The duty control circuit according to claim 6, wherein the number of said paths is expandable.