KR0120601B1 - Digital voice signal matching device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital voice signal matching device. The present invention relates to a timing switch of a switch to provide a conventional analog telephone service (POTS) to a remote subscriber of a pair gain system or a subscriber of a digital subscriber network. A central processing unit (48) for controlling each component to provide a digital voice signal matching device for directly matching digital PSHW 2.048 Mb / s signals transmitted and received from a subscriber matching circuit pack; Switching means 41 for rearranging and outputting the time slots of the digital voice signal PSHW and for rearranging and outputting the time slots of the voice channel; Matching means 42 for rearranging and outputting signaling signals and matching data; PCM matching means 44 for constructing a frame and matching voice signals; Decode the address signal LS [3: 0] to generate the circuit pack enable signal and decode the control signal SI [15: 0], / RD [0: 1] to generate the subscriber enable signal. Generating means 43; And a clock supply means 45 for extracting the reference clock to generate the clock, thereby increasing the system subscriber capacity in a single location, thereby improving the price / performance ratio and easily maintaining the system.

Description

Digital Voice Signal Matching Device

1 is a block diagram of a central station to which the present invention is applied.

2 is a block diagram of a speech matching self to which the present invention is applied.

3 is a signal configuration diagram of a speech matching self to which the present invention is applied.

4 is a block diagram of the present invention.

* Explanation of symbols for main parts of the drawings

41: digital time switch 42: signal and data matching unit

43: address decoding section 44: PCM matching section

45: clock supply unit

The present invention provides digital transmission / reception from a timing switch of an exchange to a subscriber matching circuit pack in order to provide a conventional analog telephone service (POTS) to a remote subscriber of a pair gain system or a subscriber of a digital subscriber network. The present invention relates to a digital voice signal matching device that directly matches a PSHW 2.048 Mb / s signal.

The conventional digital voice signal matching device matches an analog voice signal with a subscriber matching part of a switch and a 2-wire tip / ring signal, converts the signal into a 4-wire digital voice signal, and converts the signal into a transmission frame. Multiplexed and sent to the power.

However, in the conventional digital voice signal matching device as described above, the analog subscriber matching circuit pack and the two-wire signal matching circuit pack of the exchange are configured as SLIC (Subscriber Line Interface Card), codec / filter as they are matched with analog 2-wire voice signals. Subscribers whose numbers of subscribers are connected as digital signals in switched locations because they mainly use analog devices such as (Codec / Filter), relay, 2-4 wire hybrid conversion circuit and network balance circuit. Relatively smaller than the number, the cost-to-performance ratio was low, and maintenance was difficult.

Accordingly, the present invention devised to solve the above problems is a central office terminal (COT) of a pair gain system (COT) or a central office of a digital cable T.V. (CATV) network (CO: Central Office) It is an object of the present invention to provide a digital voice signal matching device for directly matching a digital voice signal of 2.048Mb / s transmitted and received from the time switch of the switch to the subscriber matching circuit pack.

In order to achieve the above object, the present invention provides a control apparatus comprising: central processing means for controlling each component via an address bus and a data bus according to data of a control program and a data memory mounted in a program memory; Under the control of the central processing means, the first clocks 2MCLK and 4MCLK and the frame synchronization signal FS are received from the outside, and the time slots of the digital voice signals PSHW received from the outside are rearranged and output. Switching means for inputting (4 MHz) and rearranging time slots of the input voice channel and outputting them externally; Matching means for rearranging and outputting a signaling signal input from the outside under the control of the central processing means, and matching data input / output with the outside; PCM matching means for receiving the output of the switching means and the matching means to form a frame according to a third clock (2MHz) and to output the outside, and to receive a voice signal from the outside and to output to the switching means; Retransmission to MLIB-B via the matching means, retransmission to MLIB-B via the matching means, and control signals (SI [15: 0], / RD [0) input from MLIB-B via the matching means. Decoding means for decoding the 1]) to generate a subscriber enable signal and to transmit it to the subscriber through the switching means and PCM matching means; And clock supply means for extracting a reference clock from the PCM matching means to generate and output the second and third clocks.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a configuration diagram of a central station to which the present invention is applied.

As shown in the drawing, the analog line matching device (ALID) 11 includes 16 analog subscriber matching circuit packs (GSLB), a power supply unit (SSPB-B: Source Subscribsr Power Board-B), and a CPB. -B (Common Processor Board-B) and MLIB-B (Memory and Line Interface Board-B) are installed to match existing analog 2-wire voice signals to provide services. The General Subscriber Line Board accommodates 16 channels per circuit pack. Therefore, since there are 32 voice channels per PSHW signal that matches the Digital Line Control Division (DLCD), there are eight RSHW signals per ALID block. The ALID backboard is intended to accept one PSHW signal per two analog subscriber circuit packs.

However, the digital voice matching self 12, which mounts two digital voice matching units, a power supply unit, CPB-B and MLIB-B, and directly matches the PSHW signal in a digital matching method, has at least four PSHW signals, Accommodates up to eight.

The MLIB-B circuit pack 13 is a circuit pack used in the conventional electronic switch, and performs a line matching function for operating the PSHW signal provided from the DLCD block in each GSLB circuit pack, and the CPB-B circuit pack ( 13) transmits and receives each signaling and maintenance signal from the ALID to the main processor (SLP: Subscriber Line Processor) using IPC, and the SSPB-B circuit pack 13 supplies power. The existing MLIB-B and CPB-B circuit packs are used to replace the GSLB circuit packs with digital voice matching circuit packs without modifying the unique functions of the exchanger, thereby implementing interworking between the public switched telephone network (PSTN) and the optical CATV network.

The analog two-wire matcher 14 has been used additionally by making an analog two-wire match but can remove this match and replace GSLB with the digital voice matcher.

The 45M multiple device 15 is a channel bank system for transmitting a bidirectional communication channel to a large station in an optical CATV network.

2 is a block diagram of a digital speech matching self to which the present invention is applied.

As shown in the figure, the signal matching 21 between the DLCD and the digital voice matching circuit section is composed of a bidirectional PSHW 2.048 Mb / s signal, a frame synchronizing signal FS, and clocks 2MCLK and 4MCLK. The PSHW 2.048Mb / s signal contains 32 64Kb / s voice PCM (Pulse Code Modulation) data information and accepts 8 PSHW signals per ALID block itself. The frame sync signal FS is a signal that designates the first time slot of the PSHW signal so that 32 audio channels can be separated from the PSHW signal. 2MCLK and 4MCLK are the clock sources needed for the circuit in the circuit pack. These signals electrically limit the distance between the DLCD block and the ALCD block at the TTL (Transister Transister Losic) level. Therefore, in order to use the existing DLCD block without modification, the digital matching circuit pack must be installed in the existing ALID block self position.

In addition, the signal matching 22 between the MLIB-B and the digital voice matching circuit section is a signal transmitted / received from the MLIB-B circuit pack for controlling the call path of the subscriber matching circuit pack, and is a line control data bus (D [7: 0]). Line selection control address bus (LS [3: 0]), time slot selection control signal (SI [15: 0]), codec control serial data (Dc), clock (Dclk), control signal (/ RD [0: 1], / WR). In this way, the signals of the MLIB-B and DLCD blocks are directly matched to the digital voice matching circuit, so that the voice time slot and signaling scheme is adapted to fit the voice signals and signaling signals required by the analog subscriber matching circuit pack (GSLB) to the optical CATV network. Reconstituted.

3 is a signal configuration diagram of a voice matching self according to the present invention, and will be described in comparison with a signal configuration in a case where a conventional analog subscriber matching circuit pack is mounted. The example presented here is a backboard with two digital voice circuits in the ALID block, accepting four PSHW signals per digital voice matching circuit.

The data bus (D [7: 0]) and the line control address bus (LS [3: 0]) 31 provided by MLIB-B transmit and receive from the backboard to each circuit pack, and control signals (/ RD [1: (0), / WR) (32) provided / RD [1: 0] signals per two subscriber matching circuit packs on the existing backboard, but the digital voice matching circuit vault received the / RD [1: 0] signals directly. The time slot control signal (SI [15: 0]) 33 is transmitted from the back board to each circuit pack, and the PSH W signal 34 transmitted / received from the DLCD is one per two subscriber matching circuit packs in the existing ALID back board. The PSHW signal was accepted, but the digital voice matching circuit section received four PSHW signals per sheet.

4 is a block diagram of the present invention.

As shown in the figure, the digital time switch 41, which rearranges the time slots so that the signals transmitted from the DLCD block can be used in the optical CATV network, converts the PSHW signal, which is a 32 voice channel, into a European-like pseudo-synchronous system using a channel associated signaling (CAS) method. After relocating to a channel suitable for a CEPT frame, the channel is transmitted to the voice channel of the CEPT framer mounted in the PCM matching unit 44. In addition, the minimum PSHW signal that can be accommodated by the digital time switch 41 can operate 128 audio channels, and the clocks (2MCLK, 4MCLK) and frame synchronization signals (required to transmit and receive PSHW signals with the DLCD block) can be used. FS) is used and used in the digital time switch to achieve digital synchronization with the DLCD.

The signal and data matching unit 42 rearranges the signaling signals transmitted from the MLIB-B circuit pack to suit the optical CATV network, and matches data between the CPU of the MLIB-B circuit pack and the digital matching circuit pack CPU. do. In the existing ALID block, the MLIB-B circuit pack controls 16 analog subscriber matching circuit packs. The address bus (NS [3: 0]) is used as a signal for controlling 14 circuit packs. Since at least 8 analog subscriber matching circuit packs are operated from one digital voice matching circuit pack, the address decoding unit 43 In order to accommodate 8 analog subscriber matching circuit pack enable signals required to operate one digital voice matching circuit pack.

The address decoding unit 43 is for generating a circuit pack enable signal and a subscriber enable signal for designating a subscriber matching circuit in the circuit pack. The circuit pack enable signal is an address signal transmitted from the MLIB-B. LS [3: 0]) is decoded and transmitted to the MLIB-B through the signal and data matching section 42, and the subscriber enable signal is transmitted from the MLIB-B circuit pack (SI [15: 0]). , / RD [0: 1]) is decoded and transmitted to the subscriber device through the digital time switch 41 and the PCM matching unit 44. Accordingly, the SI [15: 0] × / RD [1: 0] signal is received in LS0, and the SI [15: 0] × / RD [1: 0] signal is also received in LS1, LS2, and LS3, respectively.

The PCM matching unit 44 receives the voice channel output from the digital time switch 41 and the signaling channel output from the signal and data matching unit 42 to form a CEPT frame, and pairs the high density pair of electrical signals for PCM matching. Coded as 3 parts of the polarity (HDB3) signal. In addition, the voice signal received from the subscriber side is matched to the frame and transmitted to the digital time switch 41 and the signal and data matching unit 42. In order to prevent clock slip between the switch and the optical CATV network, a two-frame elastic buffer is provided. Use

The clock supply unit 47 extracts a reference clock from the PCM line of the PCM matching unit 44, generates a clock required for PCM line matching, and supplies a 4 MHz clock to the digital time switch 41, and supplies the clock to the PCM matching unit 44. Awesome 2MHz clock.

The central processing unit 48 converts the PSHW 2M voice signal input from the DLCD to the digital time switch 41 into a European pseudo-synchronous signaling signal, transmits it to the PCM matching unit 44, and transmits the signaling signal transmitted from the MLIB-B to the CAS. The time slot of the digital time switch 41 to be accommodated in such a manner. In addition, the signal and data matching unit 42 is controlled so that the signaling signal transmitted from the MLIB-B to the signal and data matching unit 42 is converted into the signaling scheme of the optical CATV network.

The program memory 46 mounts a program for performing the control function of the digital time switch 41, the control function of the signal and data matching unit 42, and the signal processing function in the central processing unit 48.

The data memory 47 is a memory for storing data in the central processing unit 48.

The address bus 49 and the data bus 50 are used to control the signal and data matching section 42, the data memory 47, the address decoding section 43, the program memory 46, and the digital time switch 41. As the signal line, the data bus 50 accesses the address area designated by the address bus 49 so that the central processing unit 48 performs each function of the digital voice matching unit.

As described above, the present invention provides a two-line matching circuit pack and an existing subscriber matching circuit additionally required to match an existing analog two-wire voice signal by directly matching a digital voice signal (PSHW) to accommodate an analog telephone service of an exchange. Eliminating the pack increases the capacity of a single site's system subscribers, improving the price / performance ratio and making it easier to maintain.

Claims (1)

Central processing means (48) for controlling each component via an address bus and a data bus in accordance with a control program mounted in the program memory 46 and data of the data memory 47; Under the control of the CPU 48, the first clocks 2MCLK and 4MCLK and the frame sync signal FS are received from the outside, and the time slots of the digital voice signals PSHW received from the outside are rearranged and output. Switching means (41) for receiving the second clock (4MHz) and rearranging the time slot of the input voice channel and then outputting it to the outside; Matching means (42) for rearranging and outputting a signaling signal input from the outside under the control of the central processing means (48), and matching data input / output with the outside; Receiving the output of the switching means 41 and the matching means 42 to form a frame according to the third clock (2MHz) and output to the outside, and receives a voice signal from the outside and outputs to the switching means 41 PCM matching means 44; Decode the address signal LS [3: 0] input from the MLIB-B through the matching means 42 to generate a circuit pack enable signal, and retransmit it to the MLIB-B through the matching means 42. And decoding the control signals SI [15: 0], / RD [0: 1] input from MLIB-B through the matching means 42 to generate a subscriber enable signal, thereby switching the switch 41. Decoding means 43 for transmitting to the subscriber via the PCM matching means 44; And a clock supply means (45) for extracting a reference clock from the PCM matching means (44) to generate and output the second and third clocks.