KR0116474Y1 - Data test circuit in an exchanger - Google Patents

Abstract

The present invention relates to a data transmission sequence violation monitoring circuit of an electronic exchange, and more particularly, to a data transmission sequence violation monitoring circuit of an electronic exchange configured to eliminate a source side error caused by bit stuffing of transmission data.

The data transmission sequence violation monitoring circuit of the present invention prevents the occurrence of a transmission data error interrupt signal (INTTERR ^* ) when an address inserted with zeros after five consecutive ones can be accurately monitored. have.

Description

Data transmission sequence violation monitoring circuit of the electronic exchange

1 is a block diagram of a data transmission sequence violation monitoring circuit of a conventional electronic exchange.

2 is a frame format diagram of a signal message used in the data transmission sequence violation monitoring circuit shown in FIG.

3 is a view for explaining the operation of the data transmission sequence violation monitoring circuit shown in FIG.

4 is a block diagram of a data transmission sequence violation monitoring circuit of an electronic exchange according to the present invention.

5 is a timing diagram for explaining the operation of the data transmission sequence violation monitoring circuit shown in FIG.

＊ Explanation of symbols for main parts of drawing

410: address latch circuit 420: flag latch circuit

430: comparator 440: interrupt generation circuit

450: down counter 460: sending address latch circuit

470: delivery counter latch circuit 500: stuffing processing circuit

The present invention relates to a data transmission sequence violation monitoring circuit of an electronic exchange, and more particularly, to a data transmission sequence violation monitoring circuit of an electronic exchange configured to eliminate a source side error caused by bit stuffing of transmission data.

In general, an electronic exchange includes a plurality of signal terminal controllers in a single signal terminal group, and only one signal controller transmits data at a time when transmitting. The signal terminal maintenance device detects a failure of a signal terminal in real time. In order to maximize the reliability of the common line signaling device by performing a quick diagnosis and diagnosis, a data transmission sequence violation monitoring circuit must be provided to monitor whether data is transmitted in a round robin manner as described above.

Patent Publication No. 92-7140 proposes a data transmission sequence violation monitoring circuit of an electronic exchange as shown in FIG.

As shown in FIG. 1, the conventional data transmission sequence violation monitoring circuit includes an address latch circuit 410, a plug latch circuit 420, a comparator 430, an interrupt generating circuit 440, a down counter 450, A sending address latch circuit 460 and a sending counter latch circuit 470 are provided.

The address latch circuit 410 includes a shift register 411 connected to a clock generation circuit and a signal terminal bus matching circuit, a clock generation circuit, a shift register 412 connected to a shift register 411, a clock generation circuit, and a shift register ( A shift register 413 connected to 412 and a D flip-flop circuit 414 connected to the shift register 411 are configured.

The shift register 411 latches the source address (A3 in FIG. 2), the shift register 412 latches the destination node address (A2 in FIG. 2), and the shift register 413 the destination address (A1 in FIG. 2). Replace).

Further, the signal terminal transmission data is sent to the signal terminal network node matching circuit side through the shift register 411, and the source address A3 is output on the sending address bus inside the monitoring circuit via the D flip-flop 414.

The flag latch circuit 420 is composed of a shift register 421, which is connected to the click register circuit and the shift register 413 of the address latch circuit 410, and connects the flag (F in FIG. 2). Latch it.

The down counter 450 is composed of four bit UP / Down counters 451 and 452, each of which has an input connected to a clock generation circuit and a signal terminal bus matching circuit and an output connected to a comparator. 430 and the output counter latch circuit 47.

As the address latch circuit 410 extracts the address of the message on the transmission data bus, the down counter 450 clocks the data transmission occupancy signal TXAST ^* and the synchronization signal NSYNC ^* from the signal terminal bus matching circuit. When the signal terminal bus clock (NCLKI ^* ) from the generation circuit is counted and the address of the transmission bus occupancy device is generated. The initial value is 0 to start counting down, and the specific signal terminal is transmitting data. Stops counting and continues counting.

The comparator 430 is composed of an 8-bit address comparator 431 connected to a sending address bus inside the supervisory circuit and an output terminal of the down counter 450. The comparator 430 is an originating address (A3: D flip-flop) of a message being transmitted to the data transmitting bus. The output of the circuit 414 and the output address of the down counter 450 are inputted, and when the two addresses are different from each other, the transmission match signal MATCHTX ^* is negated and output.

The interrupt generation circuit 440 includes a NAND gate 441 connected to an output terminal of the shift register 413 of the address latch circuit 410, a NAND gate 442 connected to an output of the shift register 421 of the flag latch circuit 420, and a NAND signal. An inverter 443a connected to the output terminal of the gate 441, an OR gate 444 connected to the output terminal of the inverter 443a and the NAND gate 442, and a data input terminal D connected to an output terminal of the OR gate 444. And a D flip-flop connecting the inverter 443d connected to the clock generation circuit to the clock input terminal CK, and connecting the output terminal Q to the D flip-flop circuit 414 of the address latch circuit 410 to the clock input terminal CK. 445), the D flip-flop 446, which connects the data input terminal D to the output terminal of the comparator 430, and the clock input terminal CK to the output terminal Q of the D flip-flop 445, and the data input terminal to a 5V power supply. Connect (D), connect the clock input terminal (CK) to the output terminal (Q) of the D flip-flop 446, and send the output terminal (Q). Transmission error from the D flip-flop 447 and the interrupt control circuit connected to the clock input terminal CK of the address latch circuit 460 and the output counter latch circuit 470 and the output terminal Q connected to the interrupt control circuit. And an inverted signal terminal bus configured to AND the signal TXERR ^* and the reset signal RESET ^* and output them to the reset input terminal R of the D flip-flop 446. The clock NCLK1 ^* is used to latch the input data combining the flag F and the destination address A1 to send the source address A3, and to send the match signal MATCHTX ^* from the comparator 431. The output data latch signal TXLATCH is outputted to the sending address latching circuit 460 and the sending counter latching circuit 470 by using the output data error interrupt signal INTTXERR * to the interrupt control circuit. Reference numerals 443b and 443c are inverters.

The sending address circuit 460 is composed of an 8-bit latch circuit 471 having input terminals D1 to D8 connected to a sending address bus inside the sensing circuit and output terminals Q1 to Q8 connected to an internal data bus. The source address A3 output through the D flip-flop circuit 414 of 410 is latched.

The output counter latch circuit 470 includes an 8-bit latch circuit 471 having input terminals D1 to D8 connected to the down counter 450 and output terminals Q1 to Q8 connected to an internal data bus. Latches the transmission address sent from

In the electronic exchange, the transmitter and the receiver of the data transmission bus are operated by HDLC (High Level Data Link Control) .When the transmitter transmits 5 flags (F) after data transmission, it outputs 0 afterwards. When the receiver detects the flag F and examines the bit stream, if 1 is inputted 5 consecutively, the next bit is examined, and if it is 0, this bit is removed and if it is 1 and the next bit is 0, it is sent to the flag. I admit it.

For example, as shown in (A) of FIG. 3, the calling unit has 40 and 2F of the destination address A1 and the destination node address A2, respectively, and each of the source address A3 and the source node address A4. In the case where the 83 and 5 data are to be sent to the called party, the calling unit inserts 0 after the continuous 1 because there are five 1s consecutively between the destination node address (A2) 2F and the calling address (A3) 83. send. Therefore, as shown in FIG. 3B, the bits are shifted left by one digit, and the destination node address A2 2F becomes 4F and the destination address A1 40 is converted to 80 and sent to the destination side. At this time, the destination node address A2 2F is supplied from the down counter 450 to the input terminals AΦ to A7 of the comparator 431 and the D flip-flop circuit 414 to the input terminals BΦ to B7 of the comparator 431. Since the destination node address 4F is supplied from and the address mismatch occurs, the comparator 431 outputs the transmission match signal MATCHTX ^* to the interrupt generating circuit 440, and the interrupt generating circuit 440 violates the transmission order. The notifier outputs a transmission data error interrupt signal (INTTXERR ^* ) to the interrupt control circuit.

Therefore, the data transmission sequence violation monitoring circuit of FIG. 1 has a problem in that the transmission data error interrupt signal INTTXERR ^* is output even though no transmission sequence violation has occurred, so that the data transmission sequence violation cannot be accurately monitored.

The present technology has been devised to solve the problem as described above, and it is an object of the present invention to provide a data transmission sequence violation monitoring circuit of an electronic exchange that can accurately monitor a data transmission sequence violation even when a bit insertion occurs in the transmission data. There is this.

In order to achieve the above object, the present invention provides an address latch circuit 410, a flag latch circuit 420, a comparator 430, an interrupt generation circuit 440, a down counter 450, a sending address latch circuit 460, and In a data transmission sequence violation monitoring circuit of an electronic exchange having a sending counter latch circuit (470), a transmission address (TXD) is supplied from a signal single bus matching circuit and a signal terminal bus clock (NCLK1 *) is supplied from a clock generation circuit. If the predetermined address is inserted into the transmission address TXD, the stuffing process outputs the transmission address TXD of the remaining bits excluding the predetermined bit to the D flip-flop circuit 414 of the address latch circuit 410. It provides a data transmission sequence violation monitoring circuit of the electronic exchange further comprising a circuit (500).

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The data transmission sequence violation monitoring circuit of the electronic switch according to the present invention includes an address latch circuit 410, a flag latch circuit 420, a comparator 430, an interrupt generation circuit 440, and a down as shown in FIG. A counter 450, a sending address latch circuit 460, a sending counter latch circuit 470, and a stuffing processing circuit 500 are provided.

The data transmission sequence violation monitoring circuit of the present invention is constructed by partially modifying the data transmission sequence violation monitoring circuit of FIG. 1. The address latch circuit 410 shift register 411 and the D flip-flop circuit 414 shown in FIG. It is made by further comprising a stuffing processing circuit (500) between.

Therefore, since the description of the other circuit unit has been described above, the description thereof will be omitted and the description of the stuffing processing circuit 500 will be described.

The stuffing control circuit 500 includes a shift register 501, a NAND gate 502, an AND gate 503, and a shift register 504.

The shift register 501 has a signal terminal bus matching circuit connected to the enable terminal En, a clock generation circuit connected to the clock input Ck, a + 5V power supply connected to the input terminals A and B, and an output terminal. The NAND gate 502 is connected to Q0 to Q4.

The AND gate 503 has a clock generation circuit connected to an input terminal and an output terminal of the NAND gate 502 connected thereto.

The shift register 504 has an output terminal of the NAND gate 503 connected to the clock terminal Ck, a signal terminal bus matching circuit connected to the input terminals A and B, and an address latch circuit 410 at the output terminals Q0 to Q7. D flip-flop circuit 410 is connected.

The signal terminal bus clock NCLKI * as shown in FIG. 5 from the signal terminal bus matching circuit is supplied to the clock input terminal Ck of the shift register 501 and shown in FIG. 5 from the clock generation circuit. When the transmission address TXD as described above is supplied to the enable end En of the shift register 501, the address bit ABT1 of FIG. 5 is transmitted to the enable end En. If five 1s are present in succession, the shift register 501 outputs all of the output terminals Q0 to Q4.

Accordingly, the NAND gate 502 outputs a low signal as shown in FIG. 5A.

The AND gate 503 logically ANDs signals such as the signal terminal bus clock NCLK1 ^* as shown in FIG. 5 supplied from the clock generation circuit and A of FIG. 5 supplied from the NAND gate 502. Is generated and output to the clock input terminal Ck side of the shift register 504.

The shift register 504 enters the clock input terminal from the AND gate 503 when five 1s are continuously present in the address bits ABT1 of the transmission address TXD supplied to the input terminals A and B from the signal terminal matching circuit. In accordance with a signal such as B of FIG. 5 supplied to Ck, zeros inserted after five consecutive ones of the address bits ABT1 are not output to the D flip-flop circuit 414 side. Output the same address as ABT2).

Therefore, even if bit 0 is inserted into the transmission address TXD, the input terminal AΦ of the comparator 431 is supplied from the address shift register 414 supplied from the down counter 450 to the input terminals BΦ to B7 of the comparator 431. Since the addresses supplied to ˜A7) coincide with each other, it is possible to prevent the generation of the transmission data error interrupt signal INTTXERR ^* caused by the insertion of bit 0 into the transmission address TXD.

As described above, the data transmission sequence violation monitoring circuit of the present invention prevents the generation of the transmission data error interrupt signal INTTERR * when an address inserted with 0 after five consecutive ones is supplied. Accurately monitor violations.

Claims (2)

An address latch circuit 41, a flag latch circuit 420, a comparator 430, an interrupt generating circuit 440, a down counter 450, a feed address latch circuit 460 and a feed counter latch circuit 470; In the data transmission sequence violation monitoring circuit of an electronic switch, a transmission address (TXD) is supplied from a signal terminal bus matching circuit and a signal terminal bus clock (NCLK1 ^* ) is supplied from a clock generation circuit, and the transmission address (TXD) is supplied. And a stuffing processing circuit 500 for outputting the transmission address TXD of the remaining bits excluding the predetermined bits to the D flip-flop circuit 414 side of the address latch circuit 410 when a predetermined bit is inserted into the. A data transmission sequence violation monitoring circuit according to an electronic exchange. The stuffing processing circuit 500 of claim 1, wherein the terminal bus matching circuit is connected to an enable terminal En, the clock generation circuit is connected to a clock terminal Ck, and the input terminals A and B are connected to each other. A shift register 501 connected to a 5V power supply, a NAND gate 502 connected to an output terminal of the shift register 501 at an input terminal, and an AND gate 503 at which an output terminal of the NAND gate 502 and an clock generation circuit are connected to an input terminal of the shift register 501. And an output terminal of the AND gate 503 is connected to a clock input terminal Ck, and the signal terminal bus matching circuit is connected to input terminals A and B, and the D flip-flop circuit 414 is connected to output terminals Q1 to Q7. And a shift register (504) connected to the input terminals (D1 to D8) of the control unit.