JPWO2023143130A5 - - Google Patents

Description

This application is Chinese Patent Application No. 202210109956 entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS" filed with the State Intellectual Property Office of the People's Republic of China on January 28, 2022. No. X; Chinese Patent Application No. 202210290887.7, entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the State Intellectual Property Office of the People's Republic of China on March 23, 2022; Chinese Patent Application No. 202211065772.4, entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the State Intellectual Property Office of the People's Republic of China on September 1, 2022; Chinese Patent Application No. 202211305113.3, entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the State Intellectual Property Office of the People's Republic of China on October 24, 2022; Chinese Patent Application No. 202211305113.3, entitled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the State Intellectual Property Office of the People's Republic of China on November 18, 2022 This application claims priority from Chinese Patent Application No. 202211448533.7 entitled "A SYSTEM FOR IMPROVING HYDRAULIC PHOTOMETRY AND HYDRATED PHOTOMETRY APPARATUS," the entire contents of which are incorporated herein by reference.

This application relates to the communications field, and in particular to a data processing method and a data processing device.

With the continued proliferation of 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTN) are evolving to feature higher capacity and faster speeds. Forward error correction (FEC) coding is used to correct transmitted data, resolve transmitted bit errors, and recover the original data sent by the transmitter from the received data.

Currently, a concatenated FEC transmission solution has been proposed. In this solution, a sending device is connected to a sending processing module via an attachment unit interface (AUI). The sending device performs a first FEC encoding on the data to be transmitted and transmits the data obtained by the first FEC encoding to the sending processing module. The sending processing module performs a second FEC encoding on the data obtained by the first FEC encoding and transmits the data obtained by the second FEC encoding to a data receiving side via a channel. Specifically, the sending processing module receives multiple data streams, first performs convolutional interleaving on the multiple data streams separately, and then performs a second FEC encoding on each data stream obtained by the convolutional interleaving. It should be understood that, to improve performance, one data stream involved in the second FEC encoding needs to be from multiple codewords obtained by the first FEC encoding. However, this must be done using convolutional interleaving, which involves long latency, and adaptive behavior is not ideal for scenarios requiring low latency.

Embodiments of the present application provide a data processing method and a data processing device. In low-latency scenarios, better performance than the concatenated FEC solution can be obtained.

According to a first aspect, the present application provides a data processing method. The method includes the following steps: first, convolutional interleaving is performed separately on n lane data streams to obtain n first data streams, where n is an integer greater than 1; and first FEC encoding is performed on all of the n lane data streams; each a codeword obtained by the first FEC encoding is distributed among b lane data streams, where a≦b≦n, and n can be exactly divided by b, where a is an integer greater than or equal to 1; z consecutive symbols in each of the first data streams are from z different codewords, where z is an integer greater than 1; then, every K first data streams of the n first data streams are multiplexed to obtain one second data stream, resulting in a total of m second data streams; the n first data streams include G first data stream subsets, where symbols in different first data stream subsets are from different codewords, where m=n/K, where K is an integer greater than 1, and G is an integer greater than 1. The y consecutive symbols in each second data stream are from y different codewords, where y>z. If K≦G, the K first data streams are from K first data stream subsets, respectively. If K>G, the K first data streams include K/G first data streams in each first data stream subset.

In this embodiment, all n lane data streams are outer-code encoded codeword streams. Convolutional interleaving is performed separately on the n data streams, and data stream multiplexing is performed on the n data streams obtained by convolutional interleaving to obtain m second data streams, after which inner-code encoding is performed. The data interleaving and multiplexing processing solution provided in this application can implement the following cases with low latency: multiple symbols consecutively output from the m multiplexed data streams are from codewords of multiple different outer codes. As a result, the concatenated FEC solution helps reduce the latency of data interleaving while ensuring good performance. In other words, the combined solution of convolutional interleaving and data multiplexing in this application can reduce the overall latency of the concatenated FEC solution and is more applicable to scenarios requiring low latency.

In some possible implementations, the step of performing convolutional interleaving on one lane data stream to obtain one first data stream includes delaying the one lane data stream based on p delay lines to obtain one first data stream, where p is an integer greater than 1 and each delay line includes a different number of storage units. The delay line with the fewest number of storage units includes 0 storage units, the difference between the number of storage units of every two adjacent delay lines is Q, each storage unit is configured to store d symbols, and z = p * d. Symbols in each lane data stream are input sequentially to the p delay lines based on their sequence numbers, each delay line inputs d symbols once and outputs d symbols once, and p * d consecutive symbols in the first data stream include d symbols output from the delay line. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. In this implementation, a specific implementation of convolutional interleaving is provided, thereby improving the practicality of this solution.

In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units. d(p*Q+1)≧a*N/b, d≦a, N is the length of the codeword, and z consecutive symbols in each first data stream can be from z different codewords.

In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units. d(p*Q-1)≧a*N/b, d≦a, where N is the length of the codeword, and z consecutive symbols in each first data stream can be from z different codewords.

In some possible implementations, if K≦G, then y = K*z; or if K>G, then y = G*z. Such multiplexing schemes are used to ensure that y>z can be implemented in multiple different application scenarios, allowing the concatenated FEC solution to be implemented with better performance and lower latency.

In some possible implementations, each second data stream includes multiple second data stream symbol subsets, each second data stream symbol subset including K symbol groups, each symbol group including Δ symbols. Two adjacent symbol groups within each second data stream symbol subset are from different first data stream subsets. If K≦G, Δ is a submultiple of z; or if K>G, Δ=z.

In this embodiment, two adjacent symbol groups in each second data stream symbol subset are from different first data stream subsets, so that y consecutive symbols in the second data stream obtained by multiplexing are from y different code words, where y > z (y = K * z or y = G * z). It should be understood that when only convolutional interleaving is performed, a long latency is required to implement the case where y consecutive symbols in the output data stream are from y different code words. In this solution, the duration of the convolutional interleaving is shortened, but equivalent performance can still be achieved by combining convolutional interleaving and multiplexing. Also, by combining convolutional interleaving and multiplexing, equivalent performance can be achieved with a shorter duration of multiplexing and shorter latency.

In some possible implementations, the jth symbol group of each second data stream symbol subset is from the jth first data stream of the K first data streams involved in the multiplexing, where 0≦j≦K−1. In the above manner, rules are provided for selecting the K first data streams involved in the multiplexing to ensure that two adjacent symbol groups in each second data stream symbol subset are from different first data stream subsets.

In some possible implementations, when K>G, two adjacent first data streams of the K first data streams involved in the multiplexing are from different first data stream subsets. In the above manner, in a scenario where K>G, a rule is provided for selecting the K first data streams involved in the multiplexing, ensuring that y=G*z.

In some possible implementations, every G consecutive first data streams involved in the multiplexing are from different first data stream subsets when K>G. In the above manner, in the scenario where K>G, a rule is provided for selecting the K first data streams involved in the multiplexing, further ensuring that y=G*z.

In some possible implementations, n = 32 and K = 2, 4, or 8. In the above manner, several specific types of multiplexers are provided, expanding the application scenarios of this solution.

In some possible implementations, n = 32, p = 2, 3, 4, 6, or 8, and d = 1 or 2. In the above manner, several specific types of convolutional interleavers are provided, expanding the application scenarios of this solution.

In some possible implementations, a = 1 or 2, and b = 4, 8, or 16. The above scheme provides several distribution patterns for lane data streams, expanding the application scenarios of this solution.

In some possible implementations, prior to the step of separately performing convolutional interleaving on the n lane data streams to obtain n first data streams, the method further includes the step of performing lane reordering on the n lane data streams such that the n lane data streams are arranged in a preset sequence.

In some possible implementations, before the step of separately performing convolutional interleaving on the n lane data streams to obtain the n first data streams, the method further includes the step of performing lane deskew on the n lane data streams. In this embodiment, a specific implementation of lane data alignment is provided, thereby improving the feasibility of this solution.

In some possible implementations, before separately performing convolutional interleaving on the n lane data streams to obtain the n first data streams, the method further includes aligning the n lane data streams such that symbols within the n lane data streams are aligned. This implementation provides another specific implementation of lane data alignment, thereby improving the flexibility of this solution.

In some possible implementations, after a total of m second data streams have been obtained, the method further includes separately performing second FEC encoding on the m second data streams. The length of the information bits of the second FEC encoding is less than or equal to y symbols.

According to a second aspect, the present application provides a data processing device. The data processing device includes a convolutional interleaver and a multiplexer. The convolutional interleaver is configured to separately perform convolutional interleaving on n lane data streams to obtain n first data streams, where n is an integer greater than 1, and first FEC encoding is performed on all of the n lane data streams. Each a codeword obtained by the first FEC encoding is distributed among b lane data streams, where a≦b≦n, n is exactly divisible by b, and a is an integer greater than or equal to 1. Z consecutive symbols in each of the first data streams are from z different codewords, where z is an integer greater than 1. The multiplexer is configured to multiplex every K first data streams of the n first data streams to obtain one second data stream, to obtain a total of m second data streams. The n first data streams include G first data stream subsets, where symbols in different first data stream subsets are from different codewords, and m=n/K, where K is an integer greater than 1, and G is an integer greater than 1. The y consecutive symbols in each second data stream are from y different codewords, and y>z. If K≦G, the K first data streams are from K first data stream subsets, respectively. If K>G, the K first data streams include K/G first data streams in each first data stream subset.

In some possible implementations, the convolutional interleaver is specifically configured to delay one lane data stream based on p delay lines to obtain one first data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the fewest number of storage units includes 0 storage units, the difference between the number of storage units of every two adjacent delay lines is Q, and each storage unit is configured to store d symbols, where z = p * d. The symbols in each lane data stream are input sequentially to the p delay lines based on their sequence numbers, where d symbols are input to each delay line once and d symbols are output from the delay line once, and p * d consecutive symbols in the first data stream include d symbols output from the delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and d(p * Q + 1) ≥ a * N/b, where N is the length of the codeword and d ≤ a.

In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and d(p*Q-1)≧a*N/b, where N is the length of the codeword and d≦a.

In some possible implementations, if K≦G, then y = K*z; or if K>G, then y = G*z.

In some possible implementations, each second data stream includes multiple second data stream symbol subsets, each second data stream symbol subset including K symbol groups, each symbol group including Δ symbols. Two adjacent symbol groups within each second data stream symbol subset are from different first data stream subsets. If K≦G, Δ is a submultiple of z; or if K>G, Δ=z.

In some possible implementations, the jth symbol group of each second data stream symbol subset is from the jth first data stream of the K first data streams involved in the multiplexing, where 0≦j≦K−1.

In some possible implementations, if K>G, two adjacent first data streams of the K first data streams involved in the multiplexing are from different first data stream subsets.

In some possible implementations, if K>G, every G consecutive first data streams involved in the multiplexing are from different first data stream subsets.

In some possible embodiments, n = 32 and K = 2, 4, or 8.

In some possible embodiments, n = 32, p = 2, 3, 4, 6, or 8, and d = 1 or 2.

In some possible embodiments, a = 1 or 2 and b = 4, 8, or 16.

In some possible implementations, the data processing device further includes a lane reordering unit. Before convolutional interleaving is separately performed on the n lane data streams to obtain the n first data streams, the lane reordering unit is configured to perform lane reordering on the n lane data streams such that the n lane data streams are arranged in a preset sequence.

In some possible implementations, the data processing apparatus further includes a lane data alignment unit. The lane data alignment unit is configured to perform lane deskew on the n lane data streams before convolutional interleaving is separately performed on the n lane data streams to obtain the n first data streams.

In some possible implementations, the data processing apparatus further includes a lane data alignment unit. Before convolutional interleaving is separately performed on the n lane data streams to obtain the n first data streams, the lane data alignment unit is configured to align the n lane data streams such that symbols within the n lane data streams are aligned.

In some possible implementations, the data processing apparatus further includes an encoder. After a total of m second data streams are obtained, the encoder is configured to separately perform second FEC encoding on the m second data streams, where the length of the information bits of the second FEC encoding is less than or equal to y symbols.

According to a third aspect, the present application provides a data processing method, the method including the following steps: performing interleaving on n lane data streams to obtain m target data streams, where n is a multiple of 4; performing first forward error correction (FEC) encoding on all of the n lane data streams, and distributing every a codeword obtained by the first FEC encoding into b lane data streams, where a≦b≦n and n can be exactly divided by b; F consecutive symbols in each target data stream are from F different codewords, where F>a; F consecutive symbols in each target data stream are from at least K1 different lane data streams, and F consecutive symbols in each target data stream are from up to K2 symbols within n aligned symbols of the n lane data streams, where K1 and K2 are submultiples of n and K2 is a submultiple of K1; up to K3 symbols within F consecutive symbols in each target data stream are from the same lane data stream;
represents the integer obtained by rounding up the quotient of F/K1, and any two of the K3 symbols are separated by at least K4 symbols on the same lane data stream, where K4 ≥ a*N*K2/n, and N is the length of the codeword.

In some possible implementations, K1 = n/4 and K2 = n/16.

In some possible implementations, performing interleaving on the n lane data streams to obtain m target data streams comprises separately performing convolutional interleaving on the n lane data streams to obtain n first data streams, wherein z consecutive symbols in each of the first data streams are from at least e different codewords, z is an integer greater than 1, a≦e≦F, and e*k≧F, and at most k/k symbols in the z consecutive symbols in each of the first data streams are from the same codeword; and performing block interleaving on every K1 first data stream of the n first data streams to obtain S target data streams, where S is an integer greater than or equal to 1, m=S*n/K1, S≧k1/k2, the n first data streams include K1 first data stream groups, every two first data stream symbols in the same first data stream group are from the same codeword, and the K1 first data streams are each from the K1 first data stream groups.

In some possible implementations, performing convolutional interleaving on one lane data stream to obtain one first data stream includes delaying the one lane data stream based on p delay lines to obtain one first data stream, where p is an integer greater than 1 and p*a≧F/k2, each delay line includes a different number of storage units, the delay line with the fewest number of storage units includes zero storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store d symbols, and z=p*d. Symbols in each lane data stream are input sequentially to the p delay lines based on sequence numbers of the p delay lines, d symbols are input to each delay line once and d symbols are output from the delay lines once, and p*d consecutive symbols in the first data stream include d symbols output from the delay lines, where Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d≦a.

In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and d(p * Q + 1) ≥ K4.

In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and d(p * Q - 1) ≥ K4.

In some possible implementations, the K first data streams involved in block interleaving include a first symbol matrix, the first symbol matrix including K rows and B columns of symbols, where B = R*p*d, where R is an integer greater than or equal to 1, and the S target data streams obtained by block interleaving include a second symbol matrix, the second symbol matrix including S rows and F columns of symbols, where K*B = S*F. The symbols in the first symbol matrix are from at least F different codewords, and up to R*K1/K2 symbols in the first symbol matrix are from the same codeword.

In some possible implementations, the F symbols in each row of the second symbol matrix are at least
column, and each
At most K2 symbols are selected in the column,
represents the integer obtained by rounding up the quotient of F/K2. The F symbols in each row of the second symbol matrix are the same as those in each row of the first symbol matrix.
symbols,
represents the integer obtained by truncating the quotient of F/K1, and F symbols in each row of the second symbol matrix are at most F in each row of the first symbol matrix.
symbols,
denotes the integer obtained by rounding up the quotient of F/K.

In some possible implementations, in each row of the second symbol matrix, symbols from odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix. In each row of the second symbol matrix, symbols from even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix.

In some possible implementations, the symbols output from the delay line having the same delay value and in each row of the second symbol matrix are from different rows of the first symbol matrix.

In some possible implementations, up to K3 symbols in each row of the second symbol matrix are from the same row of the first symbol matrix, and any two of the K3 symbols are output from two delay lines, respectively, with a delay difference greater than or equal to 2*Q*d.

In some possible implementations, performing interleaving on the n lane data streams to obtain m target data streams includes performing first block interleaving on the n lane data streams to obtain T first data streams, where C consecutive symbols in each of the first data streams are from at least E different codewords, T = n/K1, C is a multiple of a, and E >= K2 * a; performing convolutional interleaving on the T first data streams to obtain T second data streams, where H consecutive symbols in each of the second data streams are from at least F different codewords, F >= E, and up to K1/K2 symbols of the H consecutive symbols in each of the second data streams are from the same codeword; and performing second block interleaving on each of the T second data streams to obtain S target data streams, obtaining a total of m target data streams, where m = T * S and S >= k1/K2.

In some possible implementations, the n lane data streams involved in the first block interleaving include a third symbol matrix, the third symbol matrix including n rows and A columns of symbols, where A is a multiple of a, and the T first data streams obtained by the first block interleaving include a fourth symbol matrix, the fourth symbol matrix including T rows and C columns of symbols, where T is a submultiple of n, such that n*A=T*C. Every T consecutive symbols in a column of the third symbol matrix is a symbol submatrix, and the T symbols in each column of the fourth symbol matrix correspond one-to-one to each symbol submatrix in the third symbol matrix.

In some possible implementations, the symbol submatrices of the third symbol matrix are arranged in a first sequence, and the first to nth rows of each column of the third symbol matrix include the first to (n/T)th symbol submatrices arranged in the first sequence, and the (n/T)th symbol submatrices in the preceding column and the first symbol submatrices in the succeeding column of two adjacent columns of the third symbol matrix are two consecutive symbol submatrices arranged in the first sequence, and T symbols in the first column of the fourth symbol matrix are from the first symbol submatrices in the third symbol matrix arranged in the first sequence, and the remaining T symbols in the Cth column of the fourth symbol matrix are deduced by analogy until they are from the last symbol submatrices in the third symbol matrix arranged in the first symbol submatrices. Alternatively, it can be deduced by analogy that the symbol submatrices of the third symbol matrix are arranged in a second sequence, and the first to A columns of every T rows of the third symbol matrix include the first to A symbol submatrices arranged in the second sequence, and the A symbol submatrix in the first T rows and the first symbol submatrix in the next T rows of two consecutive T rows of the third symbol matrix are two consecutive symbol submatrices arranged in the second sequence, and the T symbols in the first column of the fourth symbol matrix are arranged in the second sequence and are from the first symbol submatrix in the third symbol matrix, and the remaining T symbols in the C column of the fourth symbol matrix are arranged in the second sequence and are from the last symbol submatrix in the third symbol matrix.

In some possible implementations, the step of performing convolutional interleaving on one first data stream to obtain one second data stream includes delaying the one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1 and p*E≧F, each delay line includes a different number of storage units, the delay line with the fewest number of storage units includes 0 storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store C symbols, p*C=H, symbols in each first data stream are input sequentially to the p delay lines based on their sequence numbers, each delay line inputs C symbols once and outputs C symbols once, and p*C consecutive symbols in the second data stream include C symbols output from the delay lines, and Q is an integer greater than or equal to 1.

In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and C(p * Q + 1) ≥ K1 * K4.

In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and C(p*Q-1) ≥ K1*K4.

In some possible implementations, each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output from p delay lines respectively, the symbols in each symbol set are from at least F different codewords, and each target data stream includes F symbols, where R*p*C=S*F, and R is a greater than or equal integer. The F symbols in the target data stream are at least
are from different symbol subsets,
each of the different symbol subsets having at most K2*a symbols;
represents the integer obtained by rounding up the quotient of F/(K2*a).

In some possible implementations, the F symbols in the target data stream include a first symbol group from a first symbol subset and a second symbol group from a second symbol subset, the first symbol subset and the second symbol subset belong to the same symbol set, the first symbol subset and the second symbol subset are output from two adjacent delay lines, respectively, the symbols in the first symbol subset and the symbols in the second symbol subset are sequentially arranged separately, and the ranking of the first symbol group in the first symbol subset is determined by the ranking of the second symbol group in the second symbol subset. or the F symbols in the target data stream include a third symbol group from the third symbol subset and a fourth symbol group from the fourth symbol subset, the third symbol subset and the fourth symbol subset belong to different symbol sets, the third symbol subset and the fourth symbol subset are output from the same delay line, the symbols in the third symbol subset and the symbols in the fourth symbol subset are sequentially arranged separately, and the ranking of the third symbol group in the third symbol subset is different from the ranking of the fourth symbol group in the fourth symbol subset.

In some possible implementations, the maximum number of symbols in each target data stream is
symbols are from the same symbol set,
represents the integer obtained by rounding up the quotient of F/R.

In some possible implementations, after a total of m target data streams is obtained, the method further includes the step of performing second FEC encoding separately on the m target data streams, wherein the length of the information bits of the second FEC encoding is equal to F symbols.

According to a fourth aspect, the present application provides a data processing device, the data processing device including an interleaving module. The interleaving module is configured to perform interleaving on n lane data streams to obtain m target data streams, where n is a multiple of 4, and a first forward error correction (FEC) encoding is performed on all of the n lane data streams, and every a codeword obtained through the first FEC encoding is distributed among b lane data streams, where a≦b≦n, and n can be exactly divisible by b. F consecutive symbols in each target data stream are from F different codewords, where F>a. The F consecutive symbols in each target data stream are from at least K1 different lane data streams, and the F consecutive symbols in each target data stream are from up to K2 symbols within n aligned symbols of the n lane data streams, where K1 and K2 are submultiples of n and K2 is a submultiple of K1. Up to K3 symbols within the F consecutive symbols in each target data stream are from the same lane data stream.
represents the integer obtained by rounding up the quotient of F/K1, and any two of the K3 symbols are separated by at least K4 symbols on the same lane data stream, where K4 ≥ a*N*K2/n, and N is the length of the codeword.

In some possible implementations, K1 = n/4 and K2 = n/16.

In some possible implementations, the interleaving module includes a convolutional interleaver and a block interleaver. The convolutional interleaver is configured to separately perform convolutional interleaving on the n lane data streams to obtain n first data streams, where z consecutive symbols of each of the first data streams are from at least e different codewords, z is an integer greater than 1, a≦e≦F, e*k2≧F, and at most k1/k2 symbols among the z consecutive symbols of each of the first data streams are from the same codeword. The block interleaver is configured to perform block interleaving on every K1 first data streams of the n first data streams to obtain a total of m target data streams, where S is an integer greater than or equal to 1, m = S * n/K1, and S ≥ k1/k2, the n first data streams include K1 first data stream groups, symbols for every two first data streams in the same first data stream group are from the same codeword, and the K1 first data streams are each from the K1 first data stream groups.

In some possible implementations, the convolutional interleaver is specifically configured to delay one lane data stream based on p delay lines to obtain one first data stream, where p is an integer greater than 1 and p*a≧F/k2, the number of storage units included in each delay line is different, the delay line with the fewest number of storage units includes 0 storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store d symbols, and z=p*d. The symbols in each lane data stream are input sequentially to the p delay lines based on their sequence numbers, where d symbols are input to each delay line once and d symbols are output from the delay line once, and p*d consecutive symbols in the first data stream include d symbols output from the delay line, where Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d≦a.

In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and d(p * Q + 1) ≥ K4.

In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and d(p * Q - 1) ≥ K4.

In some possible implementations, the K first data streams involved in block interleaving include a first symbol matrix, the first symbol matrix including K rows and B columns of symbols, where B = R*p*d, where R is an integer greater than or equal to 1, and the S target data streams obtained by block interleaving include a second symbol matrix, the second symbol matrix including S rows and F columns of symbols, where K*B = S*F. The symbols in the first symbol matrix are from at least F different codewords, and up to R*K1/K2 symbols in the first symbol matrix are from the same codeword.

In some possible implementations, the F symbols in each row of the second symbol matrix are at least
column, and each
At most K2 symbols are selected in the column,
represents the integer obtained by rounding up the quotient of F/K2. The F symbols in each row of the second symbol matrix are the same as those in each row of the first symbol matrix.
symbols,
represents the integer obtained by truncating the quotient of F/K1, and F symbols in each row of the second symbol matrix are at most F in each row of the first symbol matrix.
symbols,
denotes the integer obtained by rounding up the quotient of F/K.

In some possible implementations, in each row of the second symbol matrix, symbols from odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix, and in each row of the second symbol matrix, symbols from even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix.

In some possible implementations, the symbols output from the delay line having the same delay value and in each row of the second symbol matrix are from different rows of the first symbol matrix.

In some possible implementations, up to K3 symbols in each row of the second symbol matrix are from the same row of the first symbol matrix, and any two of the K3 symbols are output from two delay lines, respectively, with a delay difference greater than or equal to 2*Q*d.

In some possible implementations, the convolutional interleaving module includes a first block interleaver, a convolutional interleaver, and a second block interleaver. The first block interleaver is configured to perform first block interleaving on the n-lane data stream to obtain T first data streams, where C consecutive symbols of each of the first data streams are from at least E different codewords, T = n/K1, C is a multiple of a, and E >= K2 * a. The convolutional interleaver is configured to perform convolutional interleaving on the T first data streams to obtain T second data streams, where H consecutive symbols of each of the second data streams are from at least F different codewords, F >= E, and up to K1/K2 symbols within the H consecutive symbols of each of the second data streams are from the same codeword. The second block interleaver is configured to perform second block interleaving on each of the T second data streams to obtain S target data streams, where m=T*S and S≧k1/K2, to obtain a total of m target data streams.

In some possible implementations, the n lane data streams involved in the first block interleaving include a third symbol matrix, the third symbol matrix including n rows and A columns of symbols, where A is a multiple of a, and the T first data streams obtained by the first block interleaving include a fourth symbol matrix, the fourth symbol matrix including T rows and C columns of symbols, where T is a submultiple of n, such that n*A=T*C. Every T consecutive symbols in a column of the third symbol matrix is a symbol submatrix, and the T symbols in each column of the fourth symbol matrix correspond one-to-one to each symbol submatrix in the third symbol matrix.

In some possible implementations, the symbol submatrices of the third symbol matrix are arranged in a first sequence, and the first to nth rows of each column of the third symbol matrix include the first to (n/T)th symbol submatrices arranged in the first sequence, and the (n/T)th symbol submatrices in the preceding column and the first symbol submatrices in the succeeding column of two adjacent columns of the third symbol matrix are two consecutive symbol submatrices arranged in the first sequence, and T symbols in the first column of the fourth symbol matrix are from the first symbol submatrices in the third symbol matrix arranged in the first sequence, and the remaining T symbols in the Cth column of the fourth symbol matrix are deduced by analogy until they are from the last symbol submatrices in the third symbol matrix arranged in the first symbol submatrices. Alternatively, it can be deduced by analogy that the symbol submatrices of the third symbol matrix are arranged in a second sequence, and the first to A columns of every T rows of the third symbol matrix include the first to A symbol submatrices arranged in the second sequence, and the A symbol submatrix in the first T rows and the first symbol submatrix in the next T rows of two consecutive T rows of the third symbol matrix are two consecutive symbol submatrices arranged in the second sequence, and the T symbols in the first column of the fourth symbol matrix are arranged in the second sequence and are from the first symbol submatrix in the third symbol matrix, and the remaining T symbols in the C column of the fourth symbol matrix are arranged in the second sequence and are from the last symbol submatrix in the third symbol matrix.

In some possible implementations, the convolutional interleaver is specifically configured to delay one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1 and p*E≧F, each delay line includes a different number of storage units, the delay line with the fewest number of storage units includes 0 storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store C symbols, and p*C=H. The symbols in each first data stream are input sequentially to the p delay lines based on their sequence numbers, where C symbols are input to each delay line once and C symbols are output from the delay line once, and p*C consecutive symbols in the second data stream include C symbols output from the delay line, and Q is an integer greater than or equal to 1.

In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, and C(p * Q + 1) ≥ K1 * K4.

In some possible implementations, the delay line with the smallest sequence number among the p delay lines contains 0 storage units, and C(p*Q-1) ≥ K1*K4.

In some possible implementations, each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output from p delay lines respectively, the symbols in each symbol set are from at least F different codewords, and each target data stream includes F symbols, where R*p*C=S*F, and R is a greater than or equal integer. The F symbols in the target data stream are at least
are from different symbol subsets,
each of the different symbol subsets having at most K2*a symbols;
represents the integer obtained by rounding up the quotient of F/(K2*a).

In some possible implementations, the F symbols in the target data stream include a first symbol group from a first symbol subset and a second symbol group from a second symbol subset, the first symbol subset and the second symbol subset belong to the same symbol set, the first symbol subset and the second symbol subset are output from two adjacent delay lines, respectively, the symbols in the first symbol subset and the symbols in the second symbol subset are sequentially arranged separately, and the ranking of the first symbol group in the first symbol subset is determined by the ranking of the second symbol group in the second symbol subset. or the F symbols in the target data stream include a third symbol group from the third symbol subset and a fourth symbol group from the fourth symbol subset, the third symbol subset and the fourth symbol subset belong to different symbol sets, the third symbol subset and the fourth symbol subset are output from the same delay line, the symbols in the third symbol subset and the symbols in the fourth symbol subset are sequentially arranged separately, and the ranking of the third symbol group in the third symbol subset is different from the ranking of the fourth symbol group in the fourth symbol subset.

In some possible implementations, the maximum number of symbols in each target data stream is
symbols are from the same symbol set,
represents the integer obtained by rounding up the quotient of F/R.

In some possible implementations, the data processing apparatus further includes an encoder. After a total of m target data streams are obtained, the encoder is configured to perform second FEC encoding separately on the m target data streams, where the length of the information bits of the second FEC encoding is equal to F symbols.

According to a fifth aspect, the present application provides a data processing method, which includes the following steps: first, block interleaving is performed on every t lane data streams of n lane data streams to obtain s first data streams, to obtain a total of m first data streams, where n = q * t and m = q * s, where n is an integer greater than 1, n is exactly divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1; first forward error correction (FEC) encoding is performed on all n lane data streams, and every a codewords obtained by the first FEC encoding are distributed among b lane data streams, where a ≦ b ≦ n, n is exactly divisible by b, and a is an integer greater than or equal to 1; every a consecutive symbols in each lane data stream are from different codewords, and every L1 consecutive symbols in each lane data stream are from at least different codewords, where L1 = N * a/b, where N represents the length of the codeword. The t lane data streams include a total of t*a symbols , which are consecutive symbols in each lane data stream, and the t*a symbols include a total of D bits , for Δ bits in each symbol, D=Δ*t*a, where D bits are consecutive in any one of the s first data streams, and Δ=M/s, where M represents the number of bits in one symbol. Convolutional interleaving is then performed separately on the m first data streams to obtain m second data streams.

In some possible implementations, every d consecutive symbols in each first data stream are from v different codewords, and every L2 consecutive symbols in each first data stream are from at least v different codewords, where v is exactly divisible by a, L2 = t/s * L1, and d = D/M.

In some possible implementations, n=32, 16 lane data streams in the odd-numbered lanes of the n lane data streams are from the same codeword, 16 lane data streams in the even-numbered lanes of the n lane data streams are from the same codeword, and the data streams in the odd-numbered lanes of the n lane data streams and the data streams in the even-numbered lanes of the n lane data streams are from different codewords.

In some possible implementations, t = 2, s = 1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on the (2*i)-th lane data stream and the (2*i+1)-th lane data stream to obtain one first data stream, where 0≦i< 16. Two consecutive symbols in the (2*i)-th lane data stream and two consecutive symbols in the (2*i+1)-th lane data stream are consecutive in the first data stream obtained via block interleaving, and every fourth consecutive symbol in the first data stream obtained via block interleaving are from four different codewords.

In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the jth bit of the
) lane data stream of 20 consecutive bits (
) is from a bit of
represents truncation, 0≦j<40, and β is 1, 2, 4, 5, 10, or 20.

In some possible implementations, t = 2, s = 1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on the (2*i)-th lane data stream and the (2*i+1)-th lane data stream to obtain one first data stream, where 0≦i< 16. The j-th consecutive β bit groups in the (2*i)-th lane data stream and the j-th consecutive β bit groups in the (2*i+1)-th lane data stream are consecutive in the first data stream obtained via block interleaving, j≧0, β is 1, 2, 4, 5, 10, or 20, and every fourth consecutive symbols in the first data stream obtained via block interleaving are from four different codewords.

In some possible implementations, t=2, s=2, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes the step of performing block interleaving on the (2*i)-th lane data stream and the (2*i+1)-th lane data stream to obtain the (2*i)-th first data stream and the (2*i+1)-th first data stream, where 0≦i<16. Four symbols : 5 bits in each of two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream, for a total of 20 bits consecutive in the (2*i)th first data stream, with every 20 consecutive bits in the (2*i)th first data stream being from four different codewords; Four symbols : another 5 bits in each of two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream , for a total of 20 bits consecutive in the (2*i+1)th first data stream, with every 20 consecutive bits in the (2*i+1)th first data stream being from four different codewords.

In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (
) lane data stream of 20 consecutive bits (
) bits, with 0≦f<20, and 0≦g<2.

In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (
) lane data stream of 20 consecutive bits (
) bits, with 0≦f<20, and 0≦g<2.

In some possible implementations, t=4 and s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams comprises performing block interleaving on a total of four lane data streams: a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, and a (4*i+3)th lane data stream to obtain one first data stream, wherein 0≦i≦7; two consecutive symbols included in each of the four lane data streams , a total of eight symbols , are consecutive in the first data stream obtained by block interleaving; and every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 272 consecutive symbols are from at least four different code words, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words.

In some possible implementations, t=4 and s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams comprises performing block interleaving on a total of four lane data streams, namely, the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream, to obtain one first data stream, wherein 0≦i≦7; a total of eight symbols, which are jth two consecutive symbol groups included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, and the jth two consecutive symbol groups included in each of the four lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 272 consecutive symbols are from at least four different code words, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words.

In some possible implementations, t=4, s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes the step of performing block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream, to obtain one first data stream, where 0≦i≦7, a total of four symbols, that is, the jth symbol included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and every fourth consecutive symbol in the first data stream obtained by block interleaving is from four different codewords.

In some possible implementations, t=8 and s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes performing block interleaving on a total of eight lane data streams, namely, an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3 , a total of 16 consecutive symbols are included in each of the eight lane data streams in the first data stream obtained by block interleaving, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 544 consecutive symbols are from at least four different codewords, and the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, t=8 and s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes:
performing block interleaving on a total of eight lane data streams, including the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the ( 8 *i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, a total of 16 symbols being jth two consecutive symbol groups included in each of the eight lane data streams in the first data stream obtained by block interleaving are consecutive, and the jth two consecutive symbol groups included in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 544 consecutive symbols are from at least four different codewords, and the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, t=8 and s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams comprises performing block interleaving on a total of eight lane data streams, namely, an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3; a total of eight symbols, the jth symbol included in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, every eighth consecutive symbols in the first data stream obtained by block interleaving are from four different codewords, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, n = 32, and the 16 consecutive lane data streams sorted before the n lane data streams are from the same codeword, the 16 consecutive lane data streams sorted after the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted before the n lane data streams and the 16 consecutive lane data streams sorted after the n lane data streams are from different codewords.

In some possible implementations, t = 2, s = 1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain one first data stream, where 0≦i< 16. Two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream are consecutive in the first data stream obtained via block interleaving, and every fourth consecutive symbol in the first data stream obtained via block interleaving are from four different codewords.

In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the jth bit of the
) lane data stream of 20 consecutive bits (
) is from a bit of
represents truncation, 0≦j<40, and β is 1, 2, 4, 5, 10, or 20.

In some possible implementations, t = 2, s = 1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes: performing block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain one first data stream, where 0≦i< 16. The j-th consecutive β bit groups in the i-th lane data stream and the j-th consecutive β bit groups in the (i+16)-th lane data stream are consecutive in the first data stream obtained via block interleaving, j≧0, β is 1, 2, 4, 5, 10, or 20, and every fourth consecutive symbols in the first data stream obtained via block interleaving are from four different codewords.

In some possible implementations, t=2, s=2, and the step of performing block interleaving on every t lane data stream of the n lane data streams to obtain s first data streams includes the step of: performing block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain the (2*i)-th first data stream and the (2*i+1)-th first data stream, where 0≦i<16. Four symbols : 5 bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits consecutive in the (2*i)-th first data stream, where every 20 consecutive bits in the (2*i)-th first data stream are from four different codewords; Four symbols : 5 bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits consecutive in the (2*i+1)-th first data stream, where every 20 consecutive bits in the (2*i+1)-th first data stream are from four different codewords.

In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (
) lane data stream of 20 consecutive bits (
) bits, with 0≦f<20, and 0≦g<2.

In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (
) lane data stream of 20 consecutive bits (
) bits, with 0≦f<20, and 0≦g<2.

In some possible implementations, t=4 and s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams comprises performing block interleaving on a total of four lane data streams, namely, a (2*i)th lane data stream, a (2*i+1)th lane data stream, a (2*i+16)th lane data stream, and a (2*i+17)th lane data stream, to obtain one first data stream, where 0≦i≦7; a total of eight symbols, two consecutive symbols included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, every eighth consecutive symbol in the first data stream obtained by block interleaving is from at least four different codewords, all 272 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 4th, 5th, 6th, and 7th symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, t=4 and s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams comprises performing block interleaving on a total of four lane data streams, namely, the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream, to obtain one first data stream, wherein 0≦i≦7; jth two consecutive symbol groups included in each of the four lane data streams , a total of eight symbols , are consecutive in the first data stream obtained by block interleaving, and the jth two consecutive symbol groups included in each of the four lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 272 consecutive symbols are from at least four different code words, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words.

In some possible implementations, t=4, s=1, and the step of performing block interleaving on every tth lane data stream of the n lane data streams to obtain s first data streams includes the step of performing block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream, to obtain one first data stream, where 0≦i≦7, a total of four symbols, that is, the jth symbol included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and every fourth consecutive symbol in the first data stream obtained by block interleaving is from four different codewords.

In some possible implementations, t=8 and s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes performing block interleaving on a total of eight lane data streams to obtain one first data stream: a (4*i)-th lane data stream, a (4*i+1)-th lane data stream, a (4*i+2)-th lane data stream, a (4*i+3)-th lane data stream, a (4*i+16)-th lane data stream, a (4*i+17)-th lane data stream, and a (4*i+18)-th lane data stream. performing block interleaving on the first data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream, where 0≦i≦3, and two consecutive symbols included in each of the eight lane data streams in the first data stream obtained by block interleaving are consecutive, a total of 16 symbols , and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 544 consecutive symbols are from at least four different codewords, and the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, t=8 and s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes performing block interleaving on a total of eight lane data streams to obtain one first data stream: a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream. performing block interleaving on the data stream, where 0≦i≦3, and where j-th two consecutive symbol groups included in each of the eight lane data streams in the first data stream obtained by block interleaving are consecutive, a total of 16 symbols , and where the j-th two consecutive symbol groups included in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and where every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 544 consecutive symbols are from at least four different codewords, and the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, t=8 and s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams comprises performing block interleaving on a total of eight lane data streams, namely, a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream, to obtain one first data stream, wherein 0≦i≦3; a total of eight symbols, the jth symbol included in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, the zeroth symbol, the first symbol, the second symbol, and the third symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the fourth symbol, the fifth symbol, the sixth symbol, and the seventh symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, the step of performing convolutional interleaving on one first data stream to obtain one second data stream includes delaying the one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the fewest number of storage units includes 0 storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store d symbols, the symbols in each lane data stream are input to the p delay lines sequentially based on their sequence numbers, each delay line inputs d symbols once and outputs d symbols once, and p*d consecutive symbols in the second data stream include d symbols output from the delay line, and Q is an integer greater than or equal to 1.

In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, d(p*Q+1)≧L2, and L2=t/s*L1; or the delay line with the lowest sequence number among the p delay lines contains 0 storage units, d(p*Q-1)≧L2, and L2=t/s*L1.

In some possible implementations, after the step of separately performing convolutional interleaving on the m first data streams to obtain m second data streams, the method further includes separately performing second FEC encoding on the m second data streams to obtain m coded data streams. The information data having a length of K symbols in each coded data stream is from at most K different code words, where K≧p*d.

In some possible implementations, performing convolutional interleaving on a first data stream to obtain a second data stream includes delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, with the delay line having the fewest number of storage units including 0 storage units; The difference in the number of storage units between every two adjacent delay lines is Q, and each storage unit is configured to store four symbols; the symbols in each lane data stream are input sequentially to the p delay lines based on sequence numbers of the p delay lines, and each delay line inputs four symbols once and outputs four symbols once; p*4 consecutive symbols in the second data stream include the four symbols output from the delay line, and Q satisfies 4(p*Q-1)≧272, 4(p*Q-1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544.

In some possible implementations, after the step of separately performing convolutional interleaving on the m first data streams to obtain m second data streams, the method further includes the step of separately performing second FEC encoding on the m second data streams to obtain m coded data streams, wherein the information data of length K symbols in each coded data stream is from up to K different codewords, where K≧p*4.

In some possible implementations, performing convolutional interleaving on a first data stream to obtain a second data stream includes delaying the first data stream based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, with the delay line having the fewest number of storage units including 0 storage units; The difference in the number of storage units between every two adjacent delay lines is Q, wherein each storage unit is configured to store 34 bits, and the bits in each lane data stream are input sequentially to p delay lines based on the sequence numbers of the p delay lines, with 34 bits input once to each delay line and 34 bits output once from each delay line, so that p*34 consecutive bits in one second data stream comprise the 34 bits output from the delay lines; or wherein each storage unit is configured to store 68 bits, and the bits in each lane data stream are input sequentially to p delay lines based on the sequence numbers of the p delay lines, with 68 bits input once to each delay line and 68 bits output once from each delay line, so that p*68 consecutive bits in one second data stream comprise the 68 bits output from the delay lines.

In some possible implementations, p = 2 and each storage unit is configured to store 68 bits, or p = 4 and each storage unit is configured to store 34 bits.

According to a sixth aspect, the present application provides a data processing device. The data processing device includes a block interleaver and a convolutional interleaver. The block interleaver is configured to perform block interleaving on every t lane data streams of n lane data streams to obtain a total of m first data streams, where n=q*t and m=q*s, where n is an integer greater than 1, n is exactly divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. A first forward error correction (FEC) encoding is performed on all n lane data streams, and every a codeword obtained by the first FEC encoding is distributed to b lane data streams, where a≦b≦n, n is exactly divisible by b, and a is an integer greater than or equal to 1. Every a consecutive symbol in each lane data stream is from a different codeword, and all L1 consecutive symbols in each lane data stream are from at least different codewords, where L1 = N*a/b, and N represents the length of the codeword. The t lane data streams include a total of t*a consecutive symbols in each lane data stream, and the t*a symbols include a total of D bits with Δ bits in each symbol, where D = Δ*t*a, and the D bits are consecutive in any one of the s first data streams, and Δ = M/s, and M represents the number of bits in a symbol. The convolutional interleaver is configured to separately perform convolutional interleaving on the m first data streams to obtain m second data streams.

In some possible implementations, every d consecutive symbols in each first data stream are from v different codewords, and every L2 consecutive symbols in each first data stream are from at least v different codewords, where v is exactly divisible by a, L2 = t/s * L1, and d = D/M.

In some possible implementations, n=32, 16 lane data streams in the odd-numbered lanes of the n lane data streams are from the same codeword, 16 lane data streams in the even-numbered lanes of the n lane data streams are from the same codeword, and the data streams in the odd-numbered lanes of the n lane data streams and the data streams in the even-numbered lanes of the n lane data streams are from different codewords.

In some possible implementations, t = 2 and s = 1, and the block interleaver is specifically configured to perform block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain one first data stream, where 0≦i< 16. Two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream are consecutive in the first data stream obtained via block interleaving, and every fourth consecutive symbol in the first data stream obtained via block interleaving is from four different codewords.

In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the jth bit of the
) lane data stream of 20 consecutive bits (
) is from a bit of
represents truncation, 0≦j<40, and β is 1, 2, 4, 5, 10, or 20.

In some possible implementations, t = 2 and s = 1, and the block interleaver is specifically configured to perform block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain one first data stream, where 0≦i< 16. The jth consecutive β bit groups in the (2*i)th lane data stream and the jth consecutive β bit groups in the (2*i+1)th lane data stream are consecutive in the first data stream obtained via block interleaving, where j≧0, β is 1, 2, 4, 5, 10, or 20, and every fourth consecutive symbols in the first data stream obtained via block interleaving are from four different codewords.

In some possible implementations, t=2, s=2, and the block interleaver is specifically configured to perform block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain the (2*i)th first data stream and the (2*i+1)th first data stream, where 0≦i<16. Four symbols : 5 bits in each of two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream, for a total of 20 bits consecutive in the (2*i)th first data stream, with every 20 consecutive bits in the (2*i)th first data stream being from four different codewords; Four symbols : another 5 bits in each of two consecutive symbols in the (2*i)th lane data stream and two consecutive symbols in the (2*i+1)th lane data stream , for a total of 20 bits consecutive in the (2*i+1)th first data stream, with every 20 consecutive bits in the (2*i+1)th first data stream being from four different codewords.

In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (
) lane data stream of 20 consecutive bits (
) bits, with 0≦f<20, and 0≦g<2.

In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (
) lane data stream of 20 consecutive bits (
) bits, with 0≦f<20, and 0≦g<2.

In some possible implementations, t=4 and s=1, the block interleaver performs block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream, to obtain one first data stream, where 0≦i≦7, two consecutive symbols included in each of the four lane data streams , a total of eight symbols , are consecutive in the first data stream obtained by block interleaving, and every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, Specifically configured such that every 272 consecutive symbols are from at least four different code words, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words.

In some possible implementations, t=4 and s=1, the block interleaver performs block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream, to obtain one first data stream, where 0≦i≦7, where jth two consecutive symbol groups included in each of the four lane data streams , a total of eight symbols , are consecutive in the first data stream obtained by block interleaving, where jth two consecutive symbol groups included in each of the four lane data streams are consecutive in the first data stream obtained by block interleaving, where j≧0, and every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, Specifically configured such that every 272 consecutive symbols are from at least four different code words, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words.

In some possible implementations, t=4, s=1, the block interleaver is specifically configured to perform block interleaving on a total of four lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream to obtain one first data stream, where 0≦i≦7, a total of four symbols , the jth symbol included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, where j≧0, and every fourth consecutive symbol in the first data stream obtained by block interleaving is from four different codewords.

In some possible implementations, t=8 and s=1, the block interleaver performs block interleaving on a total of eight lane data streams, including the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream, to obtain one first data stream, where 0≦i≦3, and two consecutive symbols included in each of the eight lane data streams in the first data stream obtained by block interleaving are 16 consecutive symbols in total , and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; Specifically configured such that every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, where 0≦i j≦3, j-th two consecutive symbol groups comprised in each of the eight lane data streams in the first data stream obtained by block interleaving are consecutive, for a total of 16 symbols , and the j-th two consecutive symbol groups comprised in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; Specifically configured such that every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, where 0≦i≦3; Specifically configured such that a total of eight symbols, the jth symbol included in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, every eighth consecutive symbols in the first data stream obtained by block interleaving are from four different codewords, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, n = 32, and the 16 consecutive lane data streams sorted before the n lane data streams are from the same codeword, the 16 consecutive lane data streams sorted after the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted before the n lane data streams and the 16 consecutive lane data streams sorted after the n lane data streams are from different codewords.

In some possible implementations, t = 2 and s = 1, and the block interleaver is specifically configured to perform block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i< 16. Two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream are consecutive in the first data stream obtained via block interleaving, and every fourth consecutive symbol in the first data stream obtained via block interleaving is from four different codewords.

In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by block interleaving is the jth bit of the
) lane data stream of 20 consecutive bits (
) is from a bit of
represents truncation, 0≦j<40, and β is 1, 2, 4, 5, 10, or 20.

In some possible implementations, t = 2 and s = 1, and the block interleaver is specifically configured to perform block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i< 16. The jth consecutive β bit groups in the ith lane data stream and the jth consecutive β bit groups in the (i+16)th lane data stream are consecutive in the first data stream obtained via block interleaving, where j≧0, and β is 1, 2, 4, 5, 10, or 20, and every fourth consecutive symbol in the first data stream obtained via block interleaving is from four different codewords.

In some possible implementations, t=2, s=2, and the block interleaver is specifically configured to perform block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain the (2*i)-th first data stream and the (2*i+1)-th first data stream, where 0≦i<16. Four symbols : 5 bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits consecutive in the (2*i)-th first data stream, where every 20 consecutive bits in the (2*i)-th first data stream are from four different codewords; Four symbols : 5 bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits consecutive in the (2*i+1)-th first data stream, where every 20 consecutive bits in the (2*i+1)-th first data stream are from four different codewords.

In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (
) lane data stream of 20 consecutive bits (
) bits, with 0≦f<20, and 0≦g<2.

In some possible implementations, the fth bit of 20 consecutive bits in the (2*i+g)th first data stream is the (
) lane data stream of 20 consecutive bits (
) bits, with 0≦f<20, and 0≦g<2.

In some possible implementations, t=4 and s=1, the block interleaver performs block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream, to obtain one first data stream, where 0≦i≦7, two consecutive symbols included in each of the four lane data streams , a total of eight symbols , are consecutive in the first data stream obtained by block interleaving, and every eighth consecutive symbol in the first data stream obtained by block interleaving is from at least four different codewords, Specifically configured such that every 272 consecutive symbols are from at least four different code words, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words.

In some possible implementations, t=4 and s=1, the block interleaver performs block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream, to obtain one first data stream, where 0≦i≦7, where jth two consecutive symbol groups included in each of the four lane data streams , a total of eight symbols , are consecutive in the first data stream obtained by block interleaving, where jth two consecutive symbol groups included in each of the four lane data streams are consecutive in the first data stream obtained by block interleaving, where j≧0, and every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, Specifically configured such that every 272 consecutive symbols are from at least four different code words, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every 8th consecutive symbols in the first data stream obtained by block interleaving are from different code words.

In some possible implementations, t = 4, s = 1, the block interleaver is specifically configured to perform block interleaving on a total of four lane data streams: the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream, to obtain one first data stream, where 0≦i≦7, a total of four symbols , the jth symbol included in each of the four lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, and every fourth consecutive symbol in the first data stream obtained by block interleaving is from four different codewords.

In some possible implementations, t=8 and s=1, the block interleaver performs block interleaving on a total of eight lane data streams, including the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream, to obtain one first data stream, where 0≦i≦3, and there are two consecutive symbols included in each of the eight lane data streams in the first data stream obtained by block interleaving, for a total of 16 consecutive symbols , and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; Specifically configured such that every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream to obtain one first data stream, and ≦i≦3, and j-th two consecutive symbol groups included in each of the eight lane data streams in the first data stream obtained by block interleaving are consecutive , a total of 16 symbols , and the j-th two consecutive symbol groups included in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; Specifically configured such that every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, t=8 and s=1, and the block interleaver performs block interleaving on a total of eight lane data streams: a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream to obtain one first data stream, where 0≦i≦3; Specifically configured such that a total of eight symbols, the jth symbol included in each of the eight lane data streams, are consecutive in the first data stream obtained by block interleaving, j≧0, every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords.

In some possible implementations, the convolutional interleaver is specifically configured to delay one first lane data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the fewest number of storage units includes 0 storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store d symbols, the symbols in each lane data stream are input sequentially to the p delay lines based on their sequence numbers, d symbols are input to each delay line once, and d symbols are output from the delay line once, p*d consecutive symbols in the second data stream include d symbols output from the delay line, and Q is an integer greater than or equal to 1.

In some possible implementations, the delay line with the highest sequence number among the p delay lines contains 0 storage units, d(p*Q+1)≧L2, and L2=t/s*L1; or the delay line with the lowest sequence number among the p delay lines contains 0 storage units, d(p*Q-1)≧L2, and L2=t/s*L1.

In some possible implementations, the data processing apparatus further includes an encoder. After the m second data streams are obtained, the encoder is configured to separately perform second FEC encoding on the m second data streams to obtain m encoded data streams. The information data having a length of K symbols in each encoded data stream is from at most K different code words, where K≧p*d.

In some possible implementations, the convolutional interleaver delays one first lane data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, with the delay line with the fewest number of storage units including zero storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store four symbols, the symbols in each lane data stream are input sequentially to the p delay lines based on their sequence numbers, four symbols are input to each delay line once, and four symbols are output from the delay line once, p*4 consecutive symbols in the second data stream include four symbols output from the delay line, and Q is specifically configured to satisfy 4(p*Q-1)≧272, 4(p*Q+1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544.

In some possible implementations, the data processing apparatus further includes an encoder. After the m second data streams are obtained, the encoder is configured to separately perform second FEC encoding on the m second data streams to obtain m encoded data streams, where the information data having a length of K symbols in each of the encoded data streams is from up to K different code words, where K≧p*4.

In some possible implementations, the convolutional interleaver delays one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and each delay line includes a different number of storage units, with the delay line having the fewest number of storage units including 0 storage units; The difference in the number of storage units between every two adjacent delay lines is specifically configured to be Q, and each storage unit is configured to store 34 bits, and the bits in each lane data stream are input sequentially to p delay lines based on the sequence numbers of the p delay lines, with 34 bits input once to each delay line and 34 bits output once from each delay line, and p*34 consecutive bits in one second data stream comprising 34 bits output from the delay lines; or each storage unit is configured to store 68 bits, and the bits in each lane data stream are input sequentially to p delay lines based on the sequence numbers of the p delay lines, with 68 bits input once to each delay line and 68 bits output once from each delay line, and p*68 consecutive bits in one second data stream comprising 68 bits output from the delay lines.

In some possible implementations, p = 2 and each storage unit is configured to store 68 bits, or p = 4 and each storage unit is configured to store 34 bits.

According to a seventh aspect, the present application provides a data processing method, which includes the following steps: first, n lane data streams are separately delayed based on p delay lines to obtain n first data streams; first forward error correction (FEC) encoding is performed on all of the n lane data streams, where p is an integer greater than 1, each delay line includes a different number of storage units, with the delay line with the fewest number of storage units including 0 storage units; the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store U bits; bits in each lane data stream are input sequentially to the p delay lines based on sequence numbers of the p delay lines, U bits are input to each delay line once, and U bits are output from the delay lines once; p*U consecutive bits in one second data stream include U bits output from the delay lines, where Q is an integer greater than or equal to 1, and U is an integer greater than or equal to 1; then, second FEC encoding is performed separately on the n first data streams to obtain n second data streams. The information data of each codeword in the second data stream obtained by the second FEC encoding is p*U bits that are output once from the p delay lines.

In some possible embodiments, p*U = 120, 136, or 160.

According to an eighth aspect, the present application provides a data processing device, the data processing device including a convolutional interleaver and an encoder, the convolutional interleaver configured to separately delay n lane data streams using p delay lines to obtain n first data streams, a first forward error correction (FEC) encoding is performed on all of the n lane data streams, p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the fewest number of storage units includes 0 storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store U bits, bits in each lane data stream are input sequentially to the p delay lines based on sequence numbers of the p delay lines, U bits are input to each delay line once, and U bits are output from the delay lines once, p*U consecutive bits in one second data stream include U bits output from the delay lines, Q is an integer greater than or equal to 1, and U is an integer greater than or equal to 1. Then, the encoder is configured to separately perform second FEC encoding on the n first data streams to obtain n second data streams, and the information data of each codeword in the second data streams obtained by the second FEC encoding is p*U bits, which is output once from the p delay lines.

In some possible embodiments, p*U = 120, 136, or 160.

According to a ninth aspect, the present application provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by hardware, some or all of the steps of the method according to the first, third, fifth, or seventh aspect can be performed.

In an embodiment of the present application, all n lane data streams are outer-code encoded codeword streams. Convolutional interleaving is performed separately on the n data streams, and data stream multiplexing is performed on the n data streams obtained by convolutional interleaving to obtain m second data streams, after which inner-code encoding is performed. The data interleaving and multiplexing processing solution provided in the present application can implement the following cases with low latency: multiple symbols consecutively output from the m multiplexed data streams are from codewords of multiple different outer codes. As a result, the concatenated FEC solution helps reduce the latency of data interleaving while ensuring good performance. In other words, the combined solution of convolutional interleaving and data multiplexing in the present application can reduce the overall latency of the concatenated FEC solution and is more applicable to application scenarios requiring low latency.

1 is a schematic diagram of a communication system according to an embodiment of the present application; 2 is a schematic diagram of a data transmission process in the communication system shown in FIG. 1; FIG. 2 is a schematic diagram of a first type of data processing by a sender processing module according to an embodiment of the present application; FIG. 10 is a schematic diagram of a second type of data processing by a sender processing module according to an embodiment of the present application; FIG. 10 is a schematic diagram of a third type of data processing by a sender processing module according to an embodiment of the present application. FIG. 10 is a schematic diagram of a fourth type of data processing by a sender processing module according to an embodiment of the present application. FIG. 2 is a schematic diagram of lane data alignment according to an embodiment of the present application. FIG. 10 is a schematic diagram of a fifth type of data processing by a sending-side processing module according to an embodiment of the present application. FIG. 10 is a schematic diagram of a sixth type of data processing by a sending-side processing module according to an embodiment of the present application. FIG. 10 is a schematic diagram of a seventh type of data processing by a sending-side processing module according to an embodiment of the present application. FIG. 10 is a schematic diagram of an eighth type of data processing by a sending-side processing module according to an embodiment of the present application. FIG. 2 is a schematic diagram of a first type of data processing by a receiver processing module according to an embodiment of the present application; FIG. 10 is a schematic diagram of a second type of data processing by a receiver processing module according to an embodiment of the present application. FIG. 10 is a schematic diagram of a third type of data processing by a receiver processing module according to an embodiment of the present application. FIG. 1 is a schematic diagram of 32 PCS lane data streams corresponding to a 1×800G interface used by a transmitting device. FIG. 1 is a schematic diagram of 32 PCS lane data streams corresponding to 2×400G interfaces used by a transmitting device. FIG. 1 is a schematic diagram of 32 PCS lane data streams corresponding to a 4×200G interface used by a transmitting device. FIG. 1 is a schematic diagram of 32 FEC lane data streams corresponding to an 8×100G interface used by a transmitting device. FIG. 10 is another schematic diagram of 32 FEC lane data streams corresponding to an 8×100G interface used by a transmitting device. 1 is a schematic flowchart of a data processing method according to an embodiment of the present application; FIG. 2 is a schematic diagram of a structure in which convolutional interleaving is performed separately on n-lane data streams according to an embodiment of the present application. 2 is a schematic diagram of a first structure of a convolutional interleaver according to an embodiment of the present application; FIG. 2 is a schematic diagram of a second structure of a convolutional interleaver according to an embodiment of the present application; 2 is a schematic diagram of a structure in which multiplexing is performed on n first data streams according to an embodiment of the present application; FIG. 2 is a schematic diagram of a first structure of a multiplexer according to an embodiment of the present application; FIG. 2 is a schematic diagram of a structure in which FEC encoding is performed on m second data streams according to an embodiment of the present application; FIG. 10 is a schematic diagram of a third structure of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of a fourth structure of a convolutional interleaver according to an embodiment of the present application; FIG. 2 is a schematic diagram of a second structure of a multiplexer according to an embodiment of the present application; FIG. 10 is a schematic diagram of a third structure of a multiplexer according to an embodiment of the present application; FIG. 10 is a schematic diagram of a fourth structure of a multiplexer according to an embodiment of the present application; FIG. 10 is a schematic diagram of a fifth structure of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of a sixth structure of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of a seventh structure of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of an eighth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 10 is a schematic diagram of a ninth structure of a convolutional interleaver according to an embodiment of the present application; FIG. 16 is a schematic diagram of a tenth structure of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of a fifth structure of a multiplexer according to an embodiment of the present application. FIG. 16 is a schematic diagram of an eleventh structure of a convolutional interleaver according to an embodiment of the present application. FIG. 10 is a schematic diagram of a sixth structure of a multiplexer according to an embodiment of the present application. FIG. 12 is a schematic diagram of a twelfth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 13 is a schematic diagram of a thirteenth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 14 is a schematic diagram of a fourteenth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 15 is a schematic diagram of a fifteenth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 16 is a schematic diagram of a sixteenth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 17 is a schematic diagram of a seventeenth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 18 is a schematic diagram of an eighteenth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 19 is a schematic diagram of a nineteenth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 10 is a schematic diagram of a twentieth structure of a convolutional interleaver according to an embodiment of the present application. FIG. 21 is a schematic diagram of a 21st structure of a convolutional interleaver according to an embodiment of the present application. FIG. 22 is a schematic diagram of a 22nd structure of a convolutional interleaver according to an embodiment of the present application. FIG. 23 is a schematic diagram of a 23rd structure of a convolutional interleaver according to an embodiment of the present application. 2 is a schematic diagram of a structure in which block interleaving is performed on n first data streams according to an embodiment of the present application; FIG. 1 is a schematic diagram of the structure of a block interleaver according to an embodiment of the present application; 1 is a schematic diagram of the structure of a data processing apparatus according to an embodiment of the present application; 1 is a schematic flowchart of interleaving according to an embodiment of the present application; 2 is a schematic diagram of a structure in which block interleaving is performed on n first data streams according to an embodiment of the present application; FIG. FIG. 2 is a schematic diagram of an implementation of performing block interleaving according to an embodiment of the present application; 1 is a schematic diagram of a lane-aligned data stream format for a 2×400GbE host interface. FIG. 1 is a schematic diagram of an implementation of block interleaving. FIG. 10 is a schematic diagram of another embodiment of block interleaving. FIG. 10 is a schematic diagram of another embodiment of block interleaving. FIG. 10 is a schematic diagram of another embodiment of block interleaving. 10 is another schematic flowchart of interleaving according to an embodiment of the present application; FIG. 2 is a schematic diagram of an implementation of performing first block interleaving according to an embodiment of the present application. FIG. 10 is a schematic diagram of an implementation of performing second block interleaving according to an embodiment of the present application. FIG. 10 is a schematic diagram of a specific implementation of performing second block interleaving according to an embodiment of the present application. FIG. 1 is a schematic diagram of a first block interleaving implementation. FIG. 1 is a schematic diagram of an implementation of convolutional interleaving. FIG. 10 is a schematic diagram of another embodiment of convolutional interleaving. FIG. 10 is a schematic diagram of a second block interleaving embodiment. FIG. 10 is a schematic diagram of another embodiment of convolutional interleaving. FIG. 10 is a schematic diagram of another embodiment of convolutional interleaving. FIG. 10 is a schematic diagram of another embodiment of a second block interleave. FIG. 10 is a schematic diagram of another embodiment of a second block interleave. FIG. 10 is a schematic diagram of another embodiment of a second block interleave. FIG. 10 is a schematic diagram of another embodiment of first block interleaving. FIG. 2 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application; FIG. 2 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application; 1 is a schematic flowchart of a data processing method according to an embodiment of the present application; FIG. 2 is a schematic diagram of a structure in which block interleaving is performed on n-lane data streams according to an embodiment of the present application. FIG. 2 is a schematic diagram of an application scenario of block interleaving according to an embodiment of the present application; 3A-3C are schematic diagrams of several specific embodiments of block interleaving according to embodiments of the present application; FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; 3A-3C are schematic diagrams of several specific embodiments of block interleaving according to embodiments of the present application; FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; FIG. 10 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application; 2 is a schematic diagram of a structure in which convolutional interleaving is performed separately on m first data streams according to an embodiment of the present application; FIG. 1 is a schematic diagram of an embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 10 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application; FIG. 2 is a schematic diagram of an implementation of inner code encoding according to an embodiment of the present application. 1 is a schematic diagram of the structure of a data processing apparatus according to an embodiment of the present application; 4 is another schematic flowchart of a data processing method according to an embodiment of the present application; FIG. 2 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application; FIG. 2 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application;

Embodiments of the present application provide a data processing method and a data processing device such that better performance of a concatenated FEC solution can be achieved in low-latency scenarios. It should be noted that in the specification, claims, and accompanying drawings of this application, the terms "first," "second," etc. are intended to distinguish between similar objects, but do not necessarily indicate a specific order or sequence. It should be understood that the foregoing terms are interchangeable under appropriate circumstances, and thus, the embodiments described herein may be performed in orders other than those described herein. Furthermore, the terms "include," "have," or any other variants thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units is not limited to the explicitly recited steps or units, but may include other steps and units not explicitly recited or inherent to the process, method, product, or device.

FIG. 1 is a schematic diagram of a communication system according to an embodiment of the present application. As shown in FIG. 1, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. For example, the communication system is a data center network. The transmitting device 01 and the receiving device 05 may be devices such as a switch or a router, the transmitting device 01 is also called a host chip located in the transmitter, the receiving device 05 is also called a host chip located in the receiver, and the channel transmission medium 03 may be optical fiber. The host chip is also called a host device. The transmitting device 01 may be connected to the transmitting processing module 02 via an attachment unit interface (AUI), and the receiving device 05 may be connected to the receiving processing module 04 via the AUI. The transmitting processing module 02 and the receiving processing module 04 may each be an optical module, an electrical module, a connector, or another module that processes data in the data transmission process. For example, the processing module may be an 800LR module (an 800LR module, which is a coherent optical module). Furthermore, the transmitting device 01, the transmitting processing module 02, the channel transmission medium 03, the receiving processing module 04, and the receiving device 05 in the communication system may all support bidirectional or unidirectional transmission. This is not specifically limited herein.

Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1. As shown in Figure 2, in the process of transmitting data from a transmitting device 01 to a receiving device 05, the transmitting device 01 is configured to perform outer code encoding on the data and then transmit the outer code encoded data to a transmitting processing module 02. The transmitting processing module 02 is configured to perform inner code encoding on the outer code encoded data to obtain outer code encoded and inner code encoded data and transmit the outer code encoded and inner code encoded data to a channel transmission medium 03. The channel transmission medium 03 is configured to transmit the outer code encoded and inner code encoded data to a receiving processing module 04. The receiving processing module 04 is configured to perform inner code decoding on the outer code encoded and inner code encoded data and transmit the inner code decoded data to a receiving device 05. The receiving device 05 is configured to perform outer code decoding on the inner code decoded data.

It should be understood that the distinction between "internal" in the internal code and "external" in the external code is based solely on the distance between the execution entity that performs operations on the data and the channel transmission medium 03. The execution entity that performs operations on the internal code is closer to the channel transmission medium, while the execution entity that performs operations on the external code is farther from the channel transmission medium. In an embodiment of the present application, data is transmitted from the sending device 01 to the channel transmission medium 03 via the sending processing module 02, and then transmitted from the channel transmission medium 03 to the receiving device 05 via the receiving processing module 04. The distance traveled by data encoded by the sending device 01 on the channel transmission medium 03 is longer than the distance traveled by data encoded by the sending processing module 02, and the distance traveled by data decoded by the receiving device 05 on the channel transmission medium 03 is longer than the distance traveled by data decoded by the receiving processing module 04. Thus, data encoded by the transmitting device 01 is referred to as outer-code-encoded data, data encoded by the transmitting processing module 02 is referred to as inner-code-encoded data, data decoded by the receiving device 05 is referred to as outer-code-decoded data, and data decoded by the receiving processing module 04 is referred to as inner-code-decoded data. In a possible implementation, both the inner code encoding and the outer code encoding use an FEC encoding style to form a concatenated FEC transmission solution. For example, the transmitting device 01 may perform the outer code encoding using an RS code, and the transmitting processing module 02 may perform the inner code encoding using a Hamming code. As another example, the transmitting device 01 may perform the outer code encoding using an RS code, and the transmitting processing module 02 may perform the inner code encoding using a Bose-Chaudhuri-Hocquenghem (BCH) code.

Please note that the above is an exemplary description of application scenarios of the data interleaving method provided in the embodiments of this application, and does not constitute any limitations on the application scenarios of the data interleaving method. Those skilled in the art can know that as service requirements change, the application scenarios of the data interleaving method can be adjusted based on the applicable requirements. In the embodiments of this application, not every application scenario is listed.

In the aforementioned concatenated FEC transmission solution, a data processing solution including "convolutional interleaving" and "multiplexing" is designed in this application to achieve good performance and low latency for the overall concatenated FEC solution. Therefore, the concatenated FEC transmission solution can be applied to multiple transmission scenarios, and is particularly applicable to transmission scenarios requiring low transmission latency, such as low-latency data center interconnection scenarios. Data processing is performed via the aforementioned sender processing module 02.

FIG. 3(a) is a schematic diagram of a first type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(a), after processing data from multiple synchronous client lanes, the Physical Medium Attachment (PMA) sublayer of the transmitting-side processing module may obtain n outer-code-encoded Physical Coding Sublayer (PCS) or FEC lane data streams and perform alignment marker lock and lane data alignment to obtain n aligned lane data streams. Next, lane reordering is performed on the n lanes of data based on the alignment markers, so that the n lanes of data can be arranged in a specified sequence. The n lane data streams obtained by lane reordering are sent to a designated processor, including convolutional interleaving and muxing, for data sequence irregularization, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner-code encoded data stream, the processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

Figure 3(b) is a schematic diagram of a second type of data processing by the transmitting-side processing module according to an embodiment of the present application. As shown in Figure 3(b), in some practical application scenarios, the n aligned lane data streams obtained by lane data alignment are already arranged in a specified sequence. In this case, lane rearrangement does not need to be performed, and the n aligned lane data streams are directly sent to a designed processor, including convolutional interleaving and multiplexing, for interleaving and data sequence irregularization, and then sent to an inner code encoder for inner code encoding.

It should be understood that in some possible implementations, unlike the data processing procedures described in Figures 3(a) and 3(b), the n aligned lane data streams obtained by lane data alignment may alternatively not be convolutionally interleaved, but may be directly multiplexed and sent to the inner code encoder for inner code encoding.

Figure 3(c) is a schematic diagram of a third type of data processing by a transmitter processing module according to an embodiment of the present application. As shown in Figure 3(c), unlike the data processing procedure shown in Figure 3(a), the n lane data streams obtained by lane rearrangement are directly multiplexed without convolutional interleaving and sent to the inner code encoder for inner code encoding.

Figure 3(d) is a schematic diagram of a fourth type of data processing by a transmitter processing module according to an embodiment of the present application. As shown in Figure 3(d), unlike the data processing procedure shown in Figure 3(b), the n lane data streams obtained by lane data alignment are directly multiplexed without convolutional interleaving and sent to the inner code encoder for inner code encoding.

Figure 3(e) is a schematic diagram of lane data alignment according to an embodiment of the present application. It should be understood that the aforementioned "lane data alignment" may be lane de-skew defined in existing standards, ensuring that the data of the n lane data streams output through lane data alignment are perfectly aligned. Alternatively, the above-mentioned "lane data alignment" may simply be lane symbol alignment, ensuring that the data of the n lane data streams output through lane data alignment are aligned based on the outer code symbol. Specifically, the data may be aligned based on one outer code symbol or multiple outer code symbols. In Figure 3(e), two lane data streams are used as an example to describe the specific operation of "lane data alignment." It is assumed that the outer code is an RS code, and the length of one RS code symbol is 10 bits. Scenario (a) in Figure 3(e) shows that there is a 75-bit deviation between the two lane data streams, with AM0 and AM1 being the alignment markers for lane data stream 0 and lane data stream 1, respectively. Scenario (b) in Figure 3(e) uses lane de-skew as defined in the existing standard, resulting in no deviation between output lane data stream 0 and output lane data stream 1. Scenario (c) in Figure 3(e) performs a single RS symbol-based alignment, aligning one RS symbol in output lane data stream 0 and one RS symbol in output lane data stream 1. In this case, there is still a 70-bit deviation between the two lanes. Scenario (d) in Figure 3(e) performs a two-RS symbol-based alignment, aligning two RS symbols in output lane data stream 0 and two RS symbols in output lane data stream 1. In this case, there is still a 60-bit deviation between the two lanes.

3(f) is a schematic diagram of a fifth type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(f), after processing data from multiple synchronous client lanes, the Physical Medium Attachment (PMA) sublayer of the transmitting-side processing module may obtain n outer-code-encoded Physical Coding Sublayer (PCS) or FEC lane data streams and perform alignment marker lock and lane data alignment to obtain n aligned lane data streams. Next, lane reordering is performed on the n lanes of data based on the alignment markers, so that the n lanes of data can be arranged in a specified sequence. The n lane data streams obtained by lane rearrangement are sent to a processor designed for interleaving and randomizing the data sequence, including convolutional interleaving and block interleaving, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code-encoded data stream, the data-processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

3(g) is a schematic diagram of a sixth type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(g), after processing data from multiple synchronous client lanes, the Physical Medium Attachment (PMA) sublayer of the transmitting-side processing module may obtain n outer-code-encoded Physical Coding Sublayer (PCS) or FEC lane data streams, where the PCS lane data streams and the FEC lane data streams are collectively referred to as lane data streams, and may perform alignment marker lock and lane data alignment to obtain n aligned lane data streams. Next, lane reordering is performed on the n lanes of data based on the alignment markers, so that the n lanes of data can be arranged in a specified sequence. The n lane data streams obtained by lane rearrangement are sent to a processor designed to interleave and randomize the data sequence, including a first block interleaving, a convolutional interleaving, and a second block interleaving, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code-encoded data stream, the data-processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

Figure 3(h) is a schematic diagram of a seventh type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in Figure 3(h), after processing data from multiple synchronous client lanes, the Physical Medium Attachment (PMA) sublayer of the transmitting-side processing module may obtain n outer-code-encoded Physical Coding Sublayer (PCS) or FEC lane data streams and perform alignment marker lock and lane data alignment to obtain n aligned lane data streams. Next, lane reordering is performed on the n lanes of data based on the alignment markers, so that the n lanes of data can be arranged in a specified sequence. The n lane data streams obtained by lane reordering are sent to a processor designed for interleaving and randomizing the data sequence, including block interleaving and convolutional interleaving, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code-encoded data stream, the data-processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

3(i) is a schematic diagram of an eighth type of data processing by a transmitting-side processing module according to an embodiment of the present application. As shown in FIG. 3(i), after processing data from n synchronous client lanes, such as an AUI-n interface, the Physical Medium Attachment (PMA) sublayer of the transmitting-side processing module can obtain n outer-code-encoded lane data streams. The PMA sublayer herein only needs to perform signal recovery operations, such as clock data recovery (CDR) and PAM4 symbol demodulation, on the data from each client lane to obtain one lane data stream, and does not need to perform other complex operations, such as AM locking, lane deskew, and lane reordering. The n lane data streams are sent to a special processor, including a convolutional interleaving processor, for interleaving and data sequence irregularization, and then to an inner-code encoder for inner-code encoding. After data processing is performed on the inner-code-encoded data stream, the data-processed data stream is transmitted to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

In some practical application scenarios, RS outer code encoding means that encoding is performed using two encoders, followed by interleaving, such as two-way interleaving, so that RS symbols on lane data streams with even sequence numbers are transmitted in the format of "A B A B A B..." and RS symbols on lane data streams with odd sequence numbers are transmitted in the format of "B A B A B A...", where A and B are two RS symbols generated by different encoders. In the case of two RS symbol-based alignment, the effect of the embodiment is that the RS symbols on all lane data streams with even sequence numbers are generated by the same encoder at the same moment, and the RS symbols on all lane data streams with odd sequence numbers are generated by another encoder at the same moment; or the effect of another embodiment is that the RS symbols on all lane data streams are generated by the same encoder at the same moment. The specific manner is not limited herein.

4(a) is a schematic diagram of a first type of data processing by a receiving processing module according to an embodiment of the present application. As shown in FIG. 4(a), the receiving processing module receives a data stream from a channel transmission medium. If data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing has been performed on the data stream from the transmitting processing module, the receiving processing module first performs corresponding data inverse processing and then sends the data stream to an inner code decoder for decoding. After inner code decoding, the data stream is sent to a processor including convolutional deinterleaving and demultiplexing for processing to obtain n-lane data streams, which are then sent to a PMA sublayer. The PMA sublayer processes the data stream and sends the processed data stream to a receiving device for outer code decoding. Convolutional de-interleaving and de-muxing in the receiving processing module are the reverse operations of convolutional interleaving and multiplexing in the transmitting processing module. Convolutional de-interleaving is the reverse operation of convolutional interleaving in the transmitting processing module, and de-multiplexing is the reverse operation of multiplexing in the transmitting processing module. The convolutional interleaving and multiplexing in the transmitting processing module are described in detail below. The convolutional de-interleaving and de-multiplexing in the receiving processing module are the reverse operations of the convolutional interleaving and multiplexing in the transmitting processing module shown in Figures 3(a) and 3(b). This is well known to those skilled in the art and will not be described herein.

4(b) is a schematic diagram of a second type of data processing by a receiving processing module according to an embodiment of the present application. As shown in FIG. 4(b), the receiving processing module receives a data stream from a channel transmission medium. If data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing has been performed on the data stream from the transmitting processing module, the receiving processing module first performs corresponding data inverse processing and then sends the data stream to an inner code decoder for decoding. After inner code decoding, the data stream is sent to a processor for processing, including block deinterleaving and convolutional deinterleaving, to obtain n-lane data streams, which are then sent to a PMA sublayer. The PMA sublayer processes the data stream and sends the processed data stream to a receiving device for outer code decoding. In this specification, block deinterleaving and convolutional deinterleaving in the receiving-side processing module are the reverse operations of block interleaving and convolutional interleaving in the transmitting-side processing module shown in Figure 3(f). Convolutional deinterleaving is the reverse operation of convolutional interleaving in the transmitting-side processing module, and block deinterleaving is the reverse operation of block interleaving in the transmitting-side processing module.

4(c) is a schematic diagram of a third type of data processing by a receiving processing module according to an embodiment of the present application. As shown in FIG. 4(c), the receiving processing module receives a data stream from a channel transmission medium. If data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing has been performed on the data stream from the transmitting processing module, the receiving processing module first performs corresponding data inverse processing and then sends the data stream to an inner code decoder for decoding. After inner code decoding, the data stream is sent to a second block deinterleaver, a convolutional deinterleaver, and a first block deinterleaver for processing to obtain n-lane data streams, which are then sent to a PMA sublayer. The PMA sublayer processes the data stream and sends the processed data stream to a receiving device for outer code decoding. In this specification, the first block deinterleaving, convolutional deinterleaving, and second block deinterleaving in the receiving-side processing module are respectively the reverse operations of the first block interleaving, convolutional interleaving, and second block interleaving in the transmitting-side processing module shown in FIG. 3(g). The first block interleaving, convolutional interleaving, and second block interleaving in the transmitting-side processing module will be described in detail below. The first block deinterleaving, convolutional deinterleaving, and second block deinterleaving in the receiving-side processing module are respectively the reverse operations of the first block interleaving, convolutional interleaving, and second block interleaving in the transmitting-side processing module. This is well known to those skilled in the art and will not be described herein.

Below, we first provide several specific scenarios to which embodiments of this application can be applied. Please note that for ease of explanation, the following specific scenarios are explained using an example in which "lane data alignment" is lane deskew.

Figure 5 is a schematic diagram of 32 PCS lane data streams corresponding to a 1x800G interface used by a transmitting device. As shown in Figure 5, the transmitting device performs outer code encoding of a KP4 RS (544, 514) code on one channel of the 800GbE service data stream to be transmitted to obtain 32 PCS lane data streams. Every 68 consecutive symbols in each of PCS lane data streams 0 to 15 form a total of 16*68 = 1088 symbols, and two RS codewords are included. Two adjacent symbols in each PCS lane data stream are from different RS codewords, and two symbols in the same location in two adjacent PCS lane data streams are from different RS codewords. Similarly, every 68 consecutive symbols in each of PCS lane data streams 16 to 31 form a total of 16*68 = 1088 symbols, and two RS codewords are included. Two adjacent symbols in each PCS lane data stream are from different RS codewords, and two symbols in the same location in two adjacent PCS lane data streams are from different RS codewords. After PMA processing, the 32 PCS lane data streams are sent to the transmit processing module via the Mounting Unit Interface 800GAUI-8.

Based on the above-described schematic diagram of the data processing of the transmit processing module shown in Figure 3(a), the transmit processing module performs alignment marker lock on the lane data streams based on the known alignment markers of the PCS lanes. The known alignment markers of the 32 lanes are different (see the "Ethernet Technology Consortium 800G Specification"). The transmit processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers, lane reorder is performed on the data of the n = 32 lanes, so that the data of the n = 32 lanes can be arranged in a specified sequence. One sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as that shown in Figure 5.

Figure 6 is a schematic diagram of 32 PCS lane data streams corresponding to the 2x400G interface used by the transmitting device. As shown in Figure 6, the transmitting device performs outer code encoding of the KP4 RS (544, 514) code on the two channels of the 400GbE service data stream to be transmitted, obtaining a total of 32 PCS lane data streams, which are two channels of PCS lane data streams, with each channel containing 16 PCS lane data streams. Every 68 consecutive symbols in each of PCS lane data streams 0 to 15 or PCS lane data streams 16 to 31 form a total of 16*68 = 1088 symbols, containing two RS codewords. Two adjacent symbols in each PCS lane data stream are from different RS codewords, and two symbols in the same location in two adjacent PCS lane data streams are from different RS codewords. After PMA processing, the 32 PCS lane data streams are sent to the transmitting processing module via the 2x400GAUI-4 mounting unit interface.

Based on the above-described schematic diagram of the data processing of the transmitting-side processing module shown in FIG. 3(a), the transmitting-side processing module performs alignment marker lock on the 16-lane data stream based on the known alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31. PCS lanes 0 to 15 may be considered as PCS lanes 0 to 15 of the 0th channel of 400G, and PCS lanes 16 to 31 may be considered as PCS lanes 0 to 15 of the 1st channel of 400G. The known alignment markers of the 16 lanes in the 0th channel of 400G are the same as the known alignment markers of the 16 lanes in the 1st channel of 400G. The transmitting-side processing module then performs lane de-skew on the 32-lane data stream to obtain 32 aligned lane data streams. Then, based on the alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31, lane reordering is performed on the data in the 16 lanes, so that the data in the 16 lanes can be arranged in a specified sequence. Finally, the data in the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as that shown in Figure 6.

Figure 7 is a schematic diagram of 32 PCS lane data streams corresponding to a 4x200G interface used by a transmitting device. As shown in Figure 7, the transmitting device performs outer code encoding of the KP4 RS (544, 514) code on the four channels of the 200GbE service data stream to be transmitted to obtain a total of 32 PCS lane data streams, which are four channels of PCS lane data streams, and each channel contains eight PCS lane data streams. Every 136 consecutive symbols in each of PCS lane data streams 0 to 7, PCS lane data streams 8 to 15, PCS lane data streams 16 to 23, or PCS lane data streams 24 to 31 form a total of 8*136 = 1088 symbols, including two RS codewords. Two adjacent symbols in each PCS lane data stream are from different RS codewords, and two symbols at the same location in two adjacent PCS lane data streams are from different RS codewords. After PMA processing, the 32 PCS lane data streams are sent to the transmit processing module via the Attachment Unit Interface 4x200GAUI-2.

Based on the above-described schematic diagram of the data processing of the transmitting processing module shown in FIG. 3(a), the transmitting processing module performs alignment marker lock on the 8-lane data streams based on known alignment markers for PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 herein may be considered as PCS lanes 0 to 7 of the 200G 0th channel, 1st channel, 2nd channel, or 3rd channel, respectively. The transmitting processing module then performs lane de-skew on the 32-lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31, lane reordering is performed on the data in the eight lanes, and the data in the eight lanes can be arranged in a specified sequence. Finally, the data in the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as that shown in Figure 7.

8 is a schematic diagram of 32 FEC lane data streams corresponding to an 8×100G interface used by a transmitting device. As shown in FIG. 8, the transmitting device performs outer code encoding of KP4RS (544, 514) code on 8 channels of 100GbE service data streams to be transmitted to obtain 8 channels of FEC lane data streams , a total of 32 FEC lane data streams , each channel including 4 FEC lane data streams. In the "100G RS-FEC-Int" mode, which uses two KP4 RS (544,514) codeword-based interleaving, every 272 consecutive symbols in each of FEC lane data streams 0 to 3, FEC lane data streams 4 to 7, FEC lane data streams 8 to 11, FEC lane data streams 12 to 15, FEC lane data streams 16 to 19, FEC lane data streams 20 to 23, FEC lane data streams 24 to 27, or FEC lane data streams 28 to 31 form a total of 4*272 = 1088 symbols, containing two RS codewords. Two adjacent symbols in each FEC lane data stream are from different RS codewords, and two symbols in the same location in two adjacent FEC lane data streams are from different RS codewords. After PMA processing, the 32 FEC lane data streams are sent to the transmit processing module via the 8x100GAUI-1 Attachment Unit Interface.

FIG. 9 is another schematic diagram of 32 FEC lane data streams corresponding to the 8×100G interface used by the transmitting device. As shown in FIG. 9, unlike the scenario in FIG. 8, in this scenario, the transmitting device uses the “100G RS-FEC” mode, and every 136 symbols in each of FEC lane data streams 0 to 3, FEC lane data streams 4 to 7, FEC lane data streams 8 to 11, FEC lane data streams 12 to 15, FEC lane data streams 16 to 19, FEC lane data streams 20 to 23, FEC lane data streams 24 to 27, or FEC lane data streams 28 to 31 form a total of 4*136=544 symbols, which includes one RS codeword. After PMA processing, the 32 FEC lane data streams are sent to the transmitting processing module via the Attachment Unit Interface 8×100GAUI-1.

Based on the aforementioned schematic data processing diagram of the transmitter processing module shown in Figure 3(a), the transmitter processing module performs alignment marker lock on the four lane data stream based on known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31 can be considered as FEC lanes 0 to 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channel, respectively. The transmit-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31, lane reordering can be performed on the data in the four lanes to arrange the data in a specified sequence. Finally, the data in the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in Figures 8 and 9.

Figure 10 is a schematic flowchart of a data processing method according to an embodiment of the present application.

1001: Perform convolutional interleaving on the n lane data streams separately to obtain n first data streams.

In this embodiment, the lane data stream may be a PCS lane data stream or an FEC lane data stream. This is not specifically limited herein. All n lane data streams are data streams obtained by the first FEC encoding, i.e., the aforementioned outer code-encoded data streams, where n is an integer greater than 1. For example, the outer code encoding may be performed using an RS code, and the n outer code-encoded data streams may include multiple RS codewords. In actual applications, other encoding methods may be used to perform the outer code encoding. For ease of explanation, hereinafter, an RS codeword is used to represent a codeword generated by the outer code encoding. It should be understood that every a codeword obtained by the outer code encoding is distributed among b lane data streams, where a≦b≦n, n may be exactly divisible by b, and a is an integer greater than or equal to 1. In different application scenarios shown in FIGS. 5 to 9, the values of a and b may also be different. The application scenario shown in Figure 5 is used as an example, with n = 32, a = 2, and b = 16, in other words, every two code words are distributed across 16 lane data streams. The values of a and b in the application scenarios of Figures 6 to 9 can be estimated with reference to the accompanying drawings, and will not be described in detail again herein. Note that in this application, the code length of the outer code is measured in symbols, and a symbol may contain one or more bits. For example, the outer code used is the KP4 RS (544, 514) code, with a code length of N = 544 symbols and one symbol containing 10 bits.

The example indicates that when a = 1, no interleaving is performed on the codeword obtained by the transmitting device 01 through outer code encoding, and the codeword is directly distributed among the b lane data streams. As shown in FIG. 9, when a = 1, no interleaving is performed on the codeword having N = 544 symbols obtained by the transmitting device 01 through outer code KP4 encoding, and the codeword is directly distributed among the b = 4 lane data streams. The 544 symbols in one dashed box shown in FIG. 9 are from the same KP4 codeword, and N/b = 544/4 = 136 consecutive symbols in one lane data stream in each dashed box are from the same KP4 codeword.

In another example, when a>1, the codewords obtained by outer-code encoding by the transmitting device 01 are first interleaved and then distributed among b lane data streams. As shown in FIG. 8, when a=2, two-way symbol interleaving is first performed on two codewords with a total of a*N=2*544=1088 symbols obtained by outer-code KP4 encoding by the transmitting device 01, and then the two codewords are distributed among b=4 lane data streams. Each dashed box in FIG. 8 contains 1088 symbols from a=2 KP4 codewords, and the 2*N/b=2*544/4=272 consecutive symbols in one lane data stream within each dashed box are from a=2 KP4 codewords, with two adjacent symbols being from different KP4 codewords. As shown in FIG. 5, two-way symbol interleaving is first performed on two codewords with a total of a*N=2*544=1088 symbols, where a=2, obtained by outer-code KP4 encoding by transmitting device 01, and then the two codewords are distributed among b=16 lane data streams. Each dashed box shown in FIG. 5 contains 1088 symbols from a=2 KP4 codewords, and the 2*N/b=2*544/16=68 consecutive symbols in one lane data stream within each dashed box are from a=2 KP4 codewords, with two adjacent symbols being from different KP4 codewords.

Note that after convolutional interleaving, z consecutive symbols in each of the first data streams are from z different codewords, where z is an integer greater than 1. Specific implementations of convolutional interleaving are described below.

FIG. 11 is a schematic diagram of a structure in which convolutional interleaving is performed separately on n lane data streams according to an embodiment of the present application. As shown in FIG. 11, convolutional interleaving may be performed separately on n lane data streams via n convolutional interleavers. After convolutional interleaving is performed on each lane data stream, a first data stream, which is an irregular data sequence, may be obtained. Note that in this embodiment, each convolutional interleaver performs convolutional interleaving on the input lane data stream in a similar manner. Specifically, each convolutional interleaver includes p delay lines, and each convolutional interleaver delays the input lane data stream based on the p delay lines to obtain the first data stream. p is an integer greater than 1, and the number of storage units included in each delay line is different. The delay line with the fewest number of storage units includes 0 storage units, and the difference in the number of storage units between all two adjacent delay lines is Q. Each storage unit is configured to store d symbols, where z = p * d. The symbols in each lane data stream are input sequentially to the p delay lines based on the sequence numbers of the p delay lines, with each delay line receiving d symbols once and outputting d symbols once, such that p*d consecutive symbols in the first data stream include d symbols output from the delay lines. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, the p delay lines may include 0 storage units, Q storage units, 2Q storage units, ..., (p-1)Q storage units, respectively, with each storage unit configured to store d symbols. In this case, the p delay lines each correspond to p delay values, and the delay values include 0 symbols, Q*d symbols, 2Q*d symbols, ..., (p-1)Q*d symbols. Note that in this application, delay values are measured in symbols, and a symbol may include one or more bits. A greater number of symbols included in the delay value of the delay line indicates a longer delay (also called latency) of the data stream through the delay line. It should be understood that if the delay line does not include a storage unit, the delay of the delay line is 0 symbols, in other words, transparent transmission without delay is performed.

The specific structure of a convolutional interleaver is explained below with reference to the attached drawings.

Figure 12(a) is a schematic diagram of a first structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 12(a), the number of storage units in p delay lines is in descending order based on the sequence numbers of the p delay lines. Specifically, delay line 0 has (p-1)Q storage units, and Q storage units are sequentially reduced in each delay line, and delay line (p-1) has 0 storage units. Figure 12(b) is a schematic diagram of a second structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 12(b), the number of storage units in p delay lines is in ascending order based on the sequence numbers of the p delay lines. Specifically, delay line 0 has 0 storage units, and Q storage units are sequentially increased in each delay line, and delay line (p-1) has (p-1)Q storage units.

Note that the input switch and output switch of the convolutional interleaver are simultaneously located on the same delay line. After d symbols are input to the current delay line once and d symbols are output from the current delay line once, the switch position is updated to the next delay line, and the symbols in each lane data stream are input sequentially to the p delay lines based on the sequence numbers of the p delay lines, ensuring that p*d consecutive symbols in the first data stream contain d symbols output from each delay line. The specific data read/write operation is as follows: d symbols are read from the storage unit closest to the output port and located on the current delay line. The d symbols stored in each storage unit on the current delay line are transferred to the next storage unit. Next, d symbols are written to the storage unit closest to the input port and located on the current delay line. Then, switching to the next delay line is performed, and the above operations are repeated; the rest can be deduced by analogy. In a possible implementation, when the convolutional interleaver shown in FIG. 12(a) is used, the parameters of the convolutional interleaver satisfy d(p*Q+1)≧a*N/b, where N is the codeword length, and p*d consecutive symbols in the first data stream output by the convolutional interleaver are from codewords of p*d different outer codes, and d≦a. In another possible implementation, when the convolutional interleaver shown in FIG. 12(b) is used, the parameters of the convolutional interleaver satisfy d(p*Q-1)≧a*N/b, where N is the codeword length, and p*d consecutive symbols in the first data stream output by the convolutional interleaver are from codewords of p*d different outer codes, and d≦a.

It should be understood that the convolutional interleaving of Figure 12(a) and the convolutional interleaving of Figure 12(b) are reciprocal operations when the same parameters p, Q, and d are used. In other words, if the transmitting processing module uses the convolutional interleaving structure shown in Figure 12(a), the corresponding convolutional deinterleaving of the receiving processing module will use the structure shown in Figure 12(b). Similarly, if the transmitting processing module uses the convolutional interleaving structure shown in Figure 12(b), the corresponding convolutional deinterleaving of the receiving processing module will use the structure shown in Figure 12(a).

It should be further understood that any one of the n convolutional interleavers may use the structure shown in Figure 12(a) or Figure 12(b). In practical applications, all n convolutional interleavers may use the structure shown in Figure 12(a); all n convolutional interleavers may use the structure shown in Figure 12(b); or some convolutional interleavers may use the structure shown in Figure 12(a), and the remaining convolutional interleavers may use the structure shown in Figure 12(b).

Note that in some specific application scenarios, n = 32 is used as an example, the value of p can be 2, 3, 4, 6, or 8, and the value of d can be 1 or 2.

For ease of explanation, the following embodiments of convolutional interleaving will be described using an example in which all n convolutional interleavers use the structure shown in Figure 12(a). Naturally, this example may be simply extended to the other structures mentioned above, the specific implementation of which may be known to those skilled in the art and will not be described in detail herein.

In some possible implementations, before convolutional interleaving is separately performed on the n lane data streams to obtain n first data streams, lane reordering may further be performed on the n lane data streams, so that the n data streams are arranged in a preset sequence. As an example, 32 data streams are used. The 32 data streams may be sorted from top to bottom from 0 to 31. Of course, this example may simply be extended to sorting in another sequence, the specific implementation of which is known to those skilled in the art and will not be described in detail herein.

In some possible implementations, before convolutional interleaving is separately performed on the n lane data streams to obtain the n first data streams, lane data alignment may be further performed on the n lane data streams. The lane data alignment may be lane de-skew defined in existing standards, ensuring that the data of the n lane data streams output through lane data alignment are perfectly aligned. Alternatively, the above-mentioned "lane data alignment" may simply be lane symbol alignment, ensuring that the data of the n lane data streams output through lane data alignment are aligned based on the external code symbol. Specifically, the data may be aligned based on one external code symbol or multiple external code symbols. For a detailed description of lane data alignment, please refer to the related description of Figure 3(e). This will not be described in detail herein.

1002: Obtain one second data stream by multiplexing every K first data streams of the n first data streams to obtain a total of m second data streams.

13 is a schematic diagram of a structure in which multiplexing is performed on n first data streams according to an embodiment of the present application. As shown in FIG. 13, m multiplexers can be used to perform the multiplexing. Specifically, every K first data streams among the n first data streams are input to one multiplexer, and the multiplexer outputs one second data stream. The m multiplexers output a total of m second data streams, where m=n/K, and K is an integer greater than 1. For ease of explanation, this embodiment of the present application uses an example in which the integer n can be exactly divided by K for illustration. It should be noted that the n first data streams include G first data stream subsets, where G is an integer greater than 1, and the symbols in different first data stream subsets are from different codewords. In a possible embodiment, if K≦G, one first data stream is selected from each of any K first data stream subsets; in other words, the K first data streams input to one multiplexer are from the K first data stream subsets, respectively. In another possible embodiment, if K>G, K/G first data streams are selected from each first data stream subset; in other words, the K first data streams input to one multiplexer include the K/G first data streams in each first data stream subset. For example, if n=32, G=2, K=4, and m=8, K>G, so two first data streams need to be selected from each of the two first data stream subsets to obtain four first data streams input to the multiplexer. In another example, when n=32, G=4, K=2, and m=8, K<G, so two first data stream subsets need to be selected from the four first data stream subsets, and one first data stream needs to be selected from each of the two first data stream subsets, to obtain two first data streams input to the multiplexer.

Note that in some specific application scenarios, n = 32 is used as an example, and the value of K can be 2, 4, or 8.

It should be understood that the first data stream subset is a concept introduced solely for ease of explanation. In actual applications, the n first data streams are whole without division, and each first data stream subset can be considered as one or more data streams within the n first data streams.

Note that since z consecutive symbols in each first data stream involved in the multiplexing are from z different code words, y consecutive symbols in each second data stream obtained by multiplexing are from y different code words, where y > z. In a possible implementation, if K <= G, then y = K * z. In another possible implementation, if K > G, then y = G * z.

A specific implementation of multiplexing will be described below. For ease of explanation, the K first data streams input to the multiplexer will be referred to as multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, ..., multiplexed input data stream (K-1).

14 is a schematic diagram of a first structure of a multiplexer according to an embodiment of the present application. As shown in FIG.
denotes Δ consecutive symbols of multiplexed input data stream j, where the Δ symbols are from codewords of Δ different outer codes, where 0≦j≦K−1 and Δ is a divisor of z for K≦G; or Δ=z for K>G.
Let β denote consecutive ΔW RS symbols in multiplexed input data stream j. Note that the second data stream output by the multiplexer includes multiple second data stream symbol subsets, each including K symbol groups, each including Δ symbols. In addition, two adjacent symbol groups in each second data stream symbol subset are from different first data stream subsets. Specifically, the jth symbol group in a second data stream symbol subset is from the jth of the K multiplexed input data streams, where 0≦j≦K−1. Note that if K>G, then two adjacent multiplexed input data streams in the K multiplexed input data streams are from different first data stream subsets. Furthermore, note that if K>G, then every Gth consecutive multiplexed input data stream is from a different first data stream subset.

Note that because two adjacent symbol groups in each second data stream symbol subset are from different first data stream subsets, y consecutive symbols in the second data stream obtained by multiplexing are from y different codewords, where y > z (y = K * z or y = G * z). It should be understood that when only convolutional interleaving is performed, a long latency is required to implement the case where y consecutive symbols in the output data stream are from y different codewords. While this solution shortens the duration of convolutional interleaving, comparable performance can still be achieved by combining convolutional interleaving with multiplexing. Also, by combining convolutional interleaving with multiplexing, comparable performance can be achieved with a shorter duration of multiplexing and shorter latency.

It should be understood that the second data stream symbol subset is merely a concept introduced for ease of explanation. In actual applications, the symbols in the second data stream are undivided wholes, and each second data stream symbol subset can be considered as multiple symbols in the second data stream.

Figure 14 is used as an example.
is denoted as the 0th second data stream symbol subset,
are denoted as the first and second data stream symbol subsets, . . . ,
is denoted as the W-th second data stream symbol subset. The 0-th second data stream symbol subset is used as an example,
represents the Δ symbols in the 0th group,
represents the Δ symbols in the first group, . . . ,
represents the Δ symbols in the (K-1)th group.
is from multiplexed input data stream 0,
is from multiplexed input data stream 1, and . . .
It can be learned that Δ=z, is from the multiplexed input data stream (K−1).
Suppose z consecutive symbols in are from z different codewords, then
It should be understood that z consecutive symbols in are from z different code words, so that ... To implement the case where y consecutive symbols in the second data stream obtained by multiplexing are from y different code words, y > z,
and
are from different first data stream subsets, in other words, multiplexed input data stream 0 and multiplexed input data stream 1 are from different first data stream subsets.
and
are from different first data stream subsets; in other words, multiplexed input data stream 1 and multiplexed input data stream 2 are from different first data stream subsets, and so on. In this way, every 2*z consecutive symbols in the second data stream obtained by multiplexing are from codewords of 2*z different outer codes. Note that if K>G, every G consecutive multiplexed input data streams are from different first data stream subsets. Specifically, multiplexed input data stream 0 through multiplexed input data stream (G-1) are from different first data stream subsets, multiplexed input data stream G and multiplexed input data stream (2*G-1) are from different first data stream subsets, and so on. In this way, every G*z consecutive symbols in the second data stream obtained by multiplexing are from codewords of G*z different outer codes.

In other words, in the above manner, the multiplexer outputs data in the K input data streams to one second data stream in a polling manner every Δ symbols, in other words, sequentially outputs Δ symbols from each of multiplexed input data streams 0 to multiplexed input data stream (K−1) to generate the second data stream, and the data sequence corresponding to the second data stream is
When K≦G, the K first data streams selected from the first data stream subsets can correspond to the multiplexed input data stream 0 to the multiplexed input data stream (K−1) of the multiplexer in any sequence, where Δ is a submultiple of z, and any K*z consecutive symbols in the second data stream obtained by multiplexing and output are from code words of different outer codes. When K>G, the K first data streams selected from the first data stream subsets must correspond to the multiplexed input data stream 0 to the multiplexed input data stream (K−1) of the multiplexer according to a specific rule. The specific rule is that every G consecutive multiplexed input data streams of the multiplexer are from different first data stream subsets. In a specific manner, the multiplexed input data stream i*G to the multiplexed input data stream (i*G+G−1) are from the first data stream subset 0 to the first data stream subset (G−1), respectively, where 0≦i<K/G. In this way, every G*z consecutive symbols in the second data stream output by the multiplexer can be from codewords of different outer codes.

1003: Separately perform second FEC encoding on the m second data streams to obtain encoded data streams.

FIG. 15 is a schematic diagram of a structure in which FEC encoding is performed on m second data streams according to an embodiment of the present application. As shown in FIG. 15, second FEC encoding, i.e., the above-mentioned inner code encoding, is performed separately on the m second data streams, and the information bit length of the inner code encoding is less than or equal to y RS symbols. After data processing is performed on the inner code encoded data streams, the data processed data streams are transmitted to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, to improve the system's ability to tolerate burst errors, the inner code encoded data streams may be interleaved and then transmitted.

In an embodiment of the present application, all n lane data streams are outer-code encoded codeword streams. Convolutional interleaving is performed separately on the n data streams, and data stream multiplexing is performed on the convolutionally interleaved n data streams to obtain m second data streams, after which inner-code encoding is performed. The data interleaving and multiplexing processing solution provided in the present application can be implemented with low latency in the following cases: multiple symbols consecutively output from the m multiplexed data streams are from codewords of multiple different outer codes. The concatenated FEC solution helps reduce the latency of data interleaving while ensuring good performance. In other words, the combined solution of convolutional interleaving and data multiplexing in the present application allows the overall latency of the concatenated FEC solution to be lower, making it more applicable to application scenarios requiring low latency.

The following further describes the steps of the data processing method described in Figure 10 with reference to several specific embodiments.

Embodiment 1: The application scenario is a 1x800G interface, the information bit length of the inner code encoding is 120 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and lane deskew is used.

Based on the above-described schematic diagram of the data processing of the transmit processing module shown in Figure 3(a), the transmit processing module performs alignment marker lock on the lane data streams based on the known alignment markers of the PCS lanes. The known alignment markers of the 32 lanes are different (see the "Ethernet Technology Consortium 800G Specification"). The transmit processing module then performs lane de-skew on the 32 lane data streams to obtain 32 fully aligned lane data streams. Then, based on the alignment markers, lane reorder is performed on the data of the n = 32 lanes, so that the data of the n = 32 lanes can be arranged in a specified sequence. One sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as in Figure 5.

The n=32 lane data streams on which lane permutation is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for convolutional interleaving and multiplexing, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc.

In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, which is performed separately on the n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

Figure 16(a) is a schematic diagram of a third structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 16(a), p = 3 delay lines are included. The p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., no delay.

As shown in FIG. 16(a), C _r (.) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (6t) and C _r (6t+1) represent the two RS symbols in lane data stream r currently input to delay line 0, and C _r (6t-12Q) and C _r (6t-12Q+1) are the two RS symbols output from delay line 0; C _r (6t+2) and C _r (6t+3) represent the two RS symbols in the lane data stream subsequently input to delay line 1, and C _r (6t-6Q+2) and C _r (6t-6Q+3) are the two RS symbols output from delay line 1; C _r (6t+4) and C _r (6t+5) represent the two RS symbols in the lane data stream subsequently input to delay line 2, and C _r (6t+4) and C _r Cr(6t+5) are the two RS symbols output from delay line 2; _Cr (6t+6) and _Cr (6t+7) represent the two RS symbols in the lane data stream that are subsequently input to delay line 0, and _Cr (6t-12Q+6) and _Cr (6t-12Q+7) are the two RS symbols output from delay line 0; and so on. Referring to Figure 5, it can be seen that when 6Q+2≥68, i.e., Q≥11, the total six RS symbols output by convolutional interleaving, _Cr (6t-12Q), _Cr (6t-12Q+1), _Cr (6t-6Q+2), _Cr (6t-6Q+3), _Cr (6t+4), and _Cr (6t+5), are from six different RS codewords.

FIG. 16(b) is a schematic diagram of a fourth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 16(b), in a possible implementation, Q=11 is selected, and the specific structure of the convolutional interleaver is shown in FIG. 16(b). The interleaving latency corresponding to the convolutional interleaver is approximately 22*2*3/2=66 RS symbols. The convolutional interleaver shown in FIG. 16(b) performs convolutional interleaving separately on the 32 PCS lane data streams to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 5. It is not difficult to understand that any RS symbol in the first data streams 0 to 15 and any RS symbol in the first data streams 16 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=2 first data stream subsets, with first data streams 0 to 15 being first data stream subset 0 and first data streams 16 to 31 being first data stream subset 1. Referring to Figure 16(a), it is not difficult to see that the six output symbols _{Cr_0} (6t-12Q), Cr_0(6t-12Q+1), _{Cr_0} (6t-12Q+1), _{Cr_0} (6t-6Q+3), _{Cr_0} (6t+4), and _{Cr_0} (6t+5) belonging to any data stream _{r_0} in the first data stream subset 0, and the six output symbols _{Cr_1} (6t-12Q), Cr_1(6t-12Q+1), _{Cr_1} (6t-6Q+2), _{Cr_1} (6t-6Q+3), _{Cr_1} (6t+4), and _{Cr_1} (6t+4) belonging to _any data stream r_1 in the first data stream subset 1, a total of 12 RS symbols , are from 12 different RS codewords.

In this embodiment, possible implementations of the multiplexing shown in FIG. 13 are as follows: G = 2, K = 2, and m = 16. Sixteen second data streams are generated, and sixteen 2:1 multiplexing processing modules are included. Any first data stream selected from first data stream subset 0 and any first data stream selected from first data stream subset 1 are used as inputs to the 2:1 multiplexer.

17(a) is a schematic diagram of a second structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 17(a), the two input data streams of a 2:1 multiplexer i (0≦i≦15) are a first data stream i and a first data stream (i+16). In the figure,
denotes consecutive Δ=6 RS symbols of the multiplexed input data stream j of the 2:1 multiplexer, where the RS symbols are from six different outer code RS code words. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner every six RS symbols, i.e., the output data sequence is
Note that since K = G = 2, when Δ = 1, 2, or 3, the 12 consecutive RS symbols in the data stream output by the multiplexer can be from 12 different RS codewords.

Another possible implementation of the multiplexing shown in Figure 13 of this embodiment is as follows: G = 2, K = 4, m = 8, eight second data streams are generated, and eight 4:1 multiplexers are included. Any two first data streams selected from first data stream subset 0 and any two first data streams selected from first data stream subset 1 are used as inputs to the 4:1 multiplexers.

17(b) is a schematic diagram of a third structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 17(b), multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, and multiplexed input data stream 3 of 4:1 multiplexer i (0≦i≦7) correspond to first data stream i, first data stream (i+16), first data stream (i+8), and first data stream (i+24), respectively, that is, any two consecutive multiplexed input data streams of the multiplexer are from different first data stream subsets.
denotes Δ=6 consecutive RS symbols of the multiplexed input data stream j (0≦i≦3) of the 4:1 multiplexer, where the symbols are from six different outer code RS code words. The 4:1 multiplexer outputs the data in the four input data streams to the output data stream in a polling manner every six RS symbols, i.e., the output data sequence is
The 12 consecutive RS symbols in the output data stream are from 12 different RS codewords.

Another possible implementation of the multiplexing shown in Figure 13 of this embodiment is as follows: G = 2, K = 8, m = 4, four second data streams are generated, and four 8:1 multiplexers are included. Any four first data streams selected from first data stream subset 0 and any four first data streams selected from first data stream subset 1 are used as inputs to the 8:1 multiplexers.

17(c) is a schematic diagram of a fourth structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 17(c), the multiplexed input data streams 0 to 7 of an 8:1 multiplexer i (0≦i≦3) correspond to first data stream i, first data stream (i+16), first data stream (i+8), first data stream (i+24), first data stream (i+4), first data stream (i+20), first data stream (i+12), and first data stream (i+28), respectively, i.e., any two consecutive multiplexed input data streams of the multiplexer are from different first data stream subsets. It should be noted that multiplexed input data streams 0 through 7 of 8:1 multiplexer i (0≦i≦3) may alternatively correspond to first data stream i, first data stream (i+16), first data stream (i+4), first data stream (i+20), first data stream (i+8), first data stream (i+24), first data stream (i+12), and first data stream (i+28), respectively, i.e., any two consecutive multiplexed input data streams of the multiplexer are from different first data stream subsets.
denotes consecutive Δ=6 RS symbols of the multiplexed input data stream j (0≦j≦7) of the 8:1 multiplexer, where the symbols are from six different outer code RS code words. The 8:1 multiplexer outputs the data in the eight input data streams to the output data stream in a polling manner every six RS symbols, i.e., the output data sequence is
The 12 consecutive RS symbols in the output data stream are from 12 different RS codewords.

Inner code encoding is performed separately on 16, 8, or 4 second data streams, with the information bit length of the inner code encoding being 120 bits. Specifically, the inner code encoder adds redundancy separately to a total of 120 bits in 12 consecutive RS symbols in each second data stream to obtain a codeword data stream of the inner code. In one possible embodiment, inner code encoding is performed using Hamming (128, 120) to obtain a 128-bit codeword, with 8 bits of redundancy added to a total of 120 bits in 12 consecutive RS symbols in each second data stream. In another possible embodiment, inner code encoding is performed using BCH (136, 120), with 16 bits of redundancy added to a total of 120 bits in 12 consecutive RS symbols in each second data stream to obtain a 136-bit codeword.

After data processing is performed on the inner-code encoded data stream, the processed data stream is transmitted to a channel transmission medium. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, the inner-code encoded data stream may be interleaved to improve the system's ability to tolerate burst errors.

By using the data interleaving and encoding method of embodiment 1, the concatenated code of KP4 RS (544, 514) + Hamming (128, 120) in the method is in the presence of AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3, which is close to the optimal performance of the concatenated FEC method.

Embodiment 2: The application scenario is a 1x800G interface, the information bit length of the inner code encoding is 120 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and lane symbol alignment is used.

The main difference between embodiment 2 and embodiment 1 is that in embodiment 2, 32 aligned lane data streams are obtained by alignment based on two RS symbols.

Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs alignment marker lock on the lane data streams based on the known alignment markers of the PCS lanes. The transmitting processing module then performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. Based on the alignment markers, lane reordering is then performed on the data of the 32 lanes, allowing the data of the 32 lanes to be arranged in a specified sequence. One arrangement sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as Figure 3(a). Another arrangement sequence is for the first 16 lane data streams to contain PCS lane data streams 0 to 15, and the second 16 lanes to contain PCS lane data streams 16 to 31, among the 32 lanes output through top-to-bottom "lane reordering." In this case, it should be understood that the specific sequence of the first 16-lane data stream is not limited, and the specific sequence of the second 16-lane data stream is also not limited. That is, lane data stream i in Figure 3(a) does not necessarily correspond to PCS lane data stream i.

The 32 lane data streams on which lane rearrangement is performed are sent to a processor designed for convolutional interleaving and multiplexing for interleaving and data sequence irregularization, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission. It should be understood that the convolutional interleaving, multiplexing, and inner code encoding methods used in this embodiment all use the solution of embodiment 1.

By using the data interleaving and encoding scheme of embodiment 2, the concatenated code of KP4 RS(544,514) + Hamming(128,120) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3. The performance is comparable to that of the solution of embodiment 1, and the overall latency is lower. However, the solution of embodiment 2 has poorer resistance to system burst errors compared to the solution of embodiment 1. This solution is applicable to some scenarios that require lower latency.

Embodiment 3: The application scenario is a 1x800G interface, the information bit length of the inner code encoding is 160 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and lane deskew is used.

Based on embodiment 1, in this embodiment, an inner code with a code length of 160 bits is considered, and a newly designed convolutional interleaver is used accordingly.

In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, which is performed separately on the n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

Figure 18(a) is a schematic diagram of a fifth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 18(a), p = 4 delay lines are included. The four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

As shown in FIG. 18(a), C _r (.) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (8t) and C _r (8t+1) represent the two RS symbols in lane data stream r currently input to delay line 0, C _r (8t-24Q) and C _r (8t-24Q+1) are the two RS symbols output from delay line 0; C _r (8t+2) and C _r (8t+3) represent the two RS symbols in the lane data stream subsequently input to delay line 1, C _r (8t-16Q+2) and C _r (8t-16Q+3) are the two RS symbols output from delay line 1; C _r (8t+4) and C _r (8t+5) represent the two RS symbols in the lane data stream subsequently input to delay line 2, C _r (8t-8Q+4) and C _r (8t-8Q+5) are the two RS symbols output from delay line 2; C _r (8t+6) and C _r (8t+7) represent the two RS symbols in the lane data stream that are subsequently input to delay line 3; C _r (8t+6) and C _r (8t+7) are the two RS symbols output from delay line 3; and so on. Referring to Figure 5, it can be seen that when 8Q+2≧68, i.e., Q≧9, the total of eight RS symbols _Cr (8t-24Q), _Cr (8t-24Q+1), _Cr (8t-16Q+2), _Cr (8t-16Q+3), _Cr (8t-8Q+4), _Cr (8t-8Q+5), _Cr (8t+6), and _Cr (8t+7) output through convolutional interleaving are from eight different RS codewords.

FIG. 18(b) is a schematic diagram of a sixth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 18(b), in a possible implementation, Q=9 is selected, and the specific structure of the convolutional interleaver is shown in FIG. 18(b). The interleaving latency corresponding to the convolutional interleaver is approximately 27*2*4/2=108 RS symbols. The convolutional interleaver shown in FIG. 18(b) performs convolutional interleaving separately on the 32 PCS lane data streams to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 5. It is not difficult to understand that any RS symbol in the first data streams 0 to 15 and any RS symbol in the first data streams 16 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=2 first data stream subsets, with first data streams 0 to 15 being first data stream subset 0 and first data streams 16 to 31 being first data stream subset 1. Referring to FIG . 18(a), eight output symbols C _{r_0} (8t-24Q), C r_0 (8t-24Q+1), C _{r_0} (8t-16Q+2), C _{r_0} (8t-16Q+3), C _{r_0} (8t-8Q+4), C _{r_0} (8t-8Q+5), C _{r_0} (8t+6), and C _{r_0} (8t+7) of an arbitrary data stream _{r_0} in the first data stream subset 0, and eight output symbols C _{r_1} (8t-24Q), C _{r_1} (8t-24Q+1), C _{r_1} (8t-16Q+2), C _{r_1} (8t-16Q+3),
, C _{r — 1} (8t−8Q+5), C _{r — 1} (8t+6), and C _{r — 1} ( 8t+7), are from 16 different RS codewords.

In this embodiment, possible implementations of the multiplexing shown in Figure 13 are as follows: G = 2, K = 2, and m = 16. 16 second data streams are generated, and 16 2:1 multiplexing processing modules are included. Any first data stream selected from first data stream subset 0 and any first data stream selected from first data stream subset 1 are used as inputs to the 2:1 multiplexer. A corresponding specific implementation of the 2:1 multiplexer is shown in Figure 17(a). The two input data streams of 2:1 multiplexer i (0 ≤ i ≤ 15) are first data stream i and first data stream (i + 16). In the figure,
denotes consecutive Δ=8 RS symbols of the multiplexed input data stream j (0≦j≦1) of the 2:1 multiplexer, where the symbols are from eight different outer code RS code words. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner every eight RS symbols, i.e., the output data sequence is
,
The 16 consecutive RS symbols in the output data stream are from 16 different RS code words. Note that since K = G = 2, when Δ = 1, 2, or 4, the 16 consecutive RS symbols in the data stream output by the multiplexer can be from 16 different RS code words.

In this embodiment, another possible implementation of the multiplexing shown in FIG. 13 is as follows: G=2, K=4, and m=8. Eight second data streams are generated, and eight 4:1 multiplexers are included. Any two first data streams selected from first data stream subset 0 and any two first data streams selected from first data stream subset 1 are used as inputs to the 4:1 multiplexers. A corresponding specific implementation of the 4:1 multiplexers is shown in FIG. 17(b). Multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, and multiplexed input data stream 3 of 4:1 multiplexer i (0≦i≦7) correspond to first data stream i, first data stream (i+16), first data stream (i+8), and first data stream (i+24), respectively; that is, any two consecutive multiplexed input data of the multiplexer are from different first data symbol subsets. In the figure,
denotes Δ=8 consecutive RS symbols of the multiplexed input data stream j (0≦j≦3) of the 4:1 multiplexer, where the symbols are from 8 different outer code RS code words. The 4:1 multiplexer outputs the data in the four input data streams to the output data stream in a polling manner every 8 RS symbols, i.e., the output data sequence is
The 16 consecutive RS symbols in the output data stream are from 16 different RS codewords.

Another possible implementation of the multiplexing shown in FIG. 13 of this embodiment is as follows: G=2, K=8, m=4, four second data streams are generated, and four 8:1 multiplexers are included. Any four first data streams selected from first data stream subset 0 and any four first data streams selected from first data stream subset 1 are used as inputs to the 8:1 multiplexers. A corresponding specific implementation of the 8:1 multiplexers is shown in FIG. 17(c). The 0 to 7 multiplexed input data streams of 8:1 multiplexer i (0≦i≦3) correspond to first data stream i, first data stream (i+16), first data stream (i+4), first data stream (i+20), first data stream (i+8), first data stream (i+24), first data stream (i+12), and first data stream (i+28), respectively. In the figure,
denotes Δ=8 consecutive RS symbols of the multiplexed input data stream j (0≦j≦7) of the 8:1 multiplexer, where the symbols are from 8 different outer code RS code words. The 8:1 multiplexer outputs the data in the 8 input data streams to the output data stream in a polling manner every 8 RS symbols, i.e., the output data sequence is
where 16 consecutive RS symbols in the output data stream are from 16 different RS codewords.

Inner code encoding is performed separately on 16, 8, or 4 second data streams, with the information bit length of the inner code encoding being 160 bits. Specifically, the inner code encoder adds redundancy separately to a total of 160 bits in 16 consecutive RS symbols in the second data stream to obtain a codeword data stream of the inner code. In one possible embodiment, inner code encoding is performed using Hamming (170, 160) to obtain a 170-bit codeword, adding 10 bits of redundancy to a total of 160 bits in 16 consecutive RS symbols in each second data stream. In another possible embodiment, inner code encoding is performed using BCH (176, 160), adding 16 bits of redundancy to a total of 160 bits in 16 consecutive RS symbols in each second data stream to obtain a 176-bit codeword. After data processing is performed on the inner code-encoded data stream, the data-processed data stream is transmitted to a channel transmission medium for transmission.

By using the data interleaving and encoding scheme in this embodiment, when Hamming (170, 160) is used as the inner code, the concatenated code of KP4 RS (544, 514) + Hamming (170, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.3E-3, which is close to the optimal performance of the concatenated FEC scheme. When the inner code uses BCH (176, 160), the concatenated code of KP4 RS (544, 514) + BCH (176, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 8.3E-3, which is close to the optimal performance of the concatenated FEC scheme.

Embodiment 4: The application scenario is a 1x800G interface, the information bit length of the inner code encoding is 160 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and lane symbol alignment is used.

The main difference between embodiment 4 and embodiment 3 is that in embodiment 4, 32 aligned lane data streams are obtained by alignment based on two RS symbols.

Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs alignment marker lock on the lane data streams based on the known alignment markers of the PCS lanes. The transmitting processing module then performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. Based on the alignment markers, lane reordering is then performed on the data of the 32 lanes, allowing the data of the 32 lanes to be arranged in a specified sequence. One arrangement sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as Figure 3(a). Another arrangement sequence is for the first 16 lane data streams to contain PCS lane data streams 0 to 15, and the second 16 lanes to contain PCS lane data streams 16 to 31, among the 32 lanes output through top-to-bottom "lane reordering." In this case, it should be understood that the specific sequence of the first 16-lane data stream is not limited, and the specific sequence of the second 16-lane data stream is also not limited. That is, lane data stream i in Figure 3(a) does not necessarily correspond to PCS lane data stream i.

The 32 lane data streams on which lane rearrangement is performed are sent to a processor designed for convolutional interleaving and multiplexing for interleaving and data sequence irregularization, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission. It should be understood that the convolutional interleaving, multiplexing, and inner code encoding methods used in this embodiment all use the solution of embodiment 3.

By using the data interleaving and encoding scheme of embodiment 4, the concatenated code of KP4 RS(544,514) + Hamming(160,120) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3. The performance is comparable to that of the solution of embodiment 3, and the overall latency is lower. However, the solution of embodiment 4 has poorer resistance to system burst errors compared to the solution of embodiment 3. This solution is applicable to some scenarios requiring lower latency.

By using the data interleaving and encoding scheme of embodiment 4, when Hamming (170, 160) is used as the inner code, the concatenated code of KP4 RS (544, 514) + Hamming (170, 160) in the scheme is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.3E-3, which is close to the optimal performance of the concatenated FEC scheme. When the inner code uses BCH (176, 160), the concatenated code of KP4 RS (544, 514) + BCH (176, 160) in the scheme is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 8.3E-3, which is close to the optimal performance of the concatenated FEC scheme. It should be understood that when the same inner code scheme as the solution of embodiment 3 is used, the performance of the solution of embodiment 4 is the same as that of the solution of embodiment 3, but the solution of embodiment 4 has poor resistance to system burst errors. This solution is applicable to some scenarios that require lower latency.

Embodiment 5: The application scenario is a 2x400G interface, the information bit length of the inner code encoding is 120 or 160 bits, a 2:1, 4:1, or 8:1 multiplexer is used, and lane deskew is used.

Unlike embodiments 1 to 4, in this embodiment the host interface is considered to be a 2 x 400G interface at 100Gb/s per lane. For details of the interface, see IEEE Std 802.3ck™/D3.0.

Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(a), the transmitting processing module performs alignment marker lock on the 16 lane data streams based on the known alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31. Then, the transmitting processing module performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31, lane reorder is performed on the 16 lane data, so that the data of the 16 lanes can be arranged in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as in Figure 6.

The 32 lane data streams on which lane rearrangement is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to the channel transmission medium for transmission.

In a possible implementation, if the processor including the convolutional interleaving and multiplexing and inner code encoding used in embodiment 5 is the same as that in the solution of embodiment 1, the performance and latency of the concatenated FEC solution will be the same as that in embodiment 1.

In another possible implementation, if the processor including the convolutional interleaving and multiplexing and inner code encoding used in embodiment 5 is the same as that in the solution of embodiment 3, the performance and latency of the concatenated FEC solution will be the same as that in embodiment 3.

Embodiment 6: The application scenario is a 2x400G interface, the information bit length of the inner code encoding is 120 or 160 bits, a 2:1, 4:1, or 8:1 multiplexer is used, lane symbol alignment is used, and lane reordering is not performed.

Based on the solution of embodiment 5, embodiment 6 provides an implementation solution with lower latency.

Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting-side processing module shown in Figure 3(b), the transmitting-side processing module performs alignment marker lock on the 16 lane data streams based on the known alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31. The transmitting-side processing module then performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. The 32 aligned lane data streams are sent directly to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and data sequence irregularization, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code-encoded data streams, the processed data streams are transmitted to the channel transmission medium for transmission.

In a possible implementation, if the processor including the convolutional interleaving and multiplexing and inner code encoding used in embodiment 6 is the same as that in the solution of embodiment 2, the performance and latency of the concatenated FEC solution will be the same as that in embodiment 2.

In another possible implementation, if the processor including the convolutional interleaving and multiplexing and inner code encoding used in embodiment 6 is the same as that in the solution of embodiment 4, the performance and latency of the concatenated FEC solution will be the same as that in embodiment 4.

Embodiment 7: The application scenario is a 4x200G interface, the information bit length of the inner code encoding is 120 or 160 bits, a 4:1 or 8:1 multiplexer is used, and lane deskew is used.

In this embodiment, the host interface is considered to be a 4x200G interface at 100Gb/s per lane. For details about the interface, see IEEE Std 802.3ck™/D3.0.

Based on the above-described schematic diagram of the data processing of the transmitting processing module shown in FIG. 3(a), the transmitting processing module performs alignment marker lock on the 8-lane data streams based on known alignment markers for PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 herein may be considered as PCS lanes 0 to 7 of the 200G 0th channel, 1st channel, 2nd channel, or 3rd channel, respectively. The transmitting processing module then performs lane de-skew on the 32-lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31, lane reordering is performed on the data in the eight lanes, and the data in the eight lanes can be arranged in a specified sequence. Finally, the data in the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in Figure 7.

The 32 lane data streams on which lane rearrangement is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to the channel transmission medium for transmission.

In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, which is performed separately on the n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

Figure 19(a) is a schematic diagram of a seventh structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 19(a), p = 2 delay lines are included. The two delay lines each include Q storage units and 0 storage units, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 2Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

As shown in FIG. 19(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (4t) and C _r (4t+1) represent the two RS symbols in the lane data stream currently input to delay line 0, and Cr(4t-4Q) and Cr(4t-4Q+1) are the two RS symbols output from delay line 0; C _r (4t+2) and C _r (4t+3) represent the two RS symbols in the lane data stream subsequently input to delay line 1, and C _r (4t+2) and C _r (4t+3) are the two RS symbols output from delay line 1; C _r (4t+4) and C _r (4t+5) represent the two RS symbols in the lane data stream subsequently input to delay line 0, and Cr(4t-4Q+4) and Cr(4t-4Q+5) are the two RS symbols output from delay line 0; and so on. Referring to Figure 7, it can be seen that when 4Q+2≧136, i.e., Q≧34, a total of four consecutive RS symbols, Cr(4t−4Q), Cr(4t−4Q+1), _Cr (4t+2), and _Cr (4t+3), output through convolutional interleaving are from four different RS codewords.

19(b) is a schematic diagram of an eighth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 19(b), in a possible implementation, Q=34 is selected, and the specific structure of the convolutional interleaver is shown in FIG. 19(b). The corresponding interleaving latency is approximately 34*2*2/2=68 RS symbols. The convolutional interleaver shown in FIG. 19(b) performs convolutional interleaving separately on the 32 PCS lane data streams to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 7. It is not difficult to understand that any RS symbol in first data streams 0 to 7, any RS symbol in first data streams 8 to 15, any RS symbol in first data streams 16 to 23, and any RS symbol in first data streams 24 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=4 first data stream subsets, with first data streams 0 to 7 in first data stream subset 0, first data streams 8 to 15 in first data stream subset 1, first data streams 16 to 23 in first data stream subset 2, and first data streams 24 to 31 in first data stream subset 3.

In this embodiment, possible implementations of the multiplexing shown in FIG. 13 are as follows: G = 4, K = 4, and m = 8. Eight 4:1 multiplexers are included. Each multiplexer multiplexes four first data streams to obtain one second data stream, generating a total of eight second data streams. Any first data stream selected from first data stream subset 0, any first data stream selected from first data stream subset 1, any first data stream selected from first data stream subset 2, and any first data stream selected from first data stream subset 3 are used as inputs to the 4:1 multiplexers.

A corresponding specific implementation of a 4:1 multiplexer is shown in Figure 17(b). Multiplexed Input Data Stream 0, Multiplexed Input Data Stream 1, Multiplexed Input Data Stream 2, and Multiplexed Input Data Stream 3 of 4:1 multiplexer i (0 < i < 7) correspond to first data stream i, first data stream (i + 16), first data stream (i + 8), and first data stream (i + 24), respectively. Note that multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, and multiplexed input data stream 3 of 4:1 multiplexer i (0 < i < 7) may alternatively correspond to first data stream i, first data stream (i + 8), first data stream (i + 16), and first data stream (i + 24), respectively. In this embodiment, the multiplexed input data streams shown in Figure 17(b) are used.
denotes consecutive Δ=4 RS symbols of the multiplexed input data stream j (0≦j≦3) of the 4:1 multiplexer, where the symbols are from four different outer code RS code words. The 4:1 multiplexer outputs the data in the four input data streams to the output data stream in a polling manner every four RS symbols, i.e., the output data sequence is
The 16 consecutive RS symbols in the output data stream are from 16 different RS code words. Note that because K = G = 4, one first data stream selected from each of first data stream subsets 0 to 3 can correspond to multiplexed input data streams 0 to 3 of 4:1 multiplexer i (0 ≦ i ≦ 7) in any sequence. If Δ = 1 or 2, the 16 consecutive RS symbols in the second data stream can still be from 16 different RS code words.

In this embodiment, another possible implementation of the multiplexing shown in FIG. 13 is as follows: G = 4, K = 8, and m = 4. Four 8:1 multiplexers are included. Each multiplexer multiplexes eight first data streams to obtain one second data stream, generating a total of four second data streams. Any two first data streams selected from first data stream subset 0, any two first data streams selected from first data stream subset 1, any two first data streams selected from first data stream subset 2, and any two first data streams selected from first data stream subset 3 are used as inputs to the 8:1 multiplexers.

A corresponding specific implementation of an 8:1 multiplexer is shown in Figure 17(c). The multiplexed input data streams 0 through 7 of 8:1 multiplexer i (0 < i < 3) correspond to first data stream i, first data stream (i + 16), first data stream (i + 8), first data stream (i + 24), first data stream (i + 4), first data stream (i + 20), first data stream (i + 12), and first data stream (i + 28), respectively; i.e., any Q = 4 consecutive multiplexed input data streams of the multiplexer are from different first data stream subsets. It should be noted that multiplexed input data streams 0 through 7 of 8:1 multiplexer i (0≦i≦3) may alternatively correspond to first data stream i, first data stream (i+8), first data stream (i+16), first data stream (i+24), first data stream (i+4), first data stream (i+12), first data stream (i+20), and first data stream (i+28), respectively.
denotes consecutive Δ=4 RS symbols of the multiplexed input data stream j (0≦j≦7) of the 8:1 multiplexer, where the symbols are from four different outer code RS code words. The 8:1 multiplexer outputs the data in the eight input data streams to the output data stream in a polling manner every four RS symbols, i.e., the output data sequence is
where 16 consecutive RS symbols in the output data stream are from 16 different RS codewords.

Inner code encoding is performed separately on the aforementioned eight or four second data streams. The inner code encoding method may be the encoding method provided in embodiment 1 to obtain performance equivalent to that of embodiment 1; alternatively, the encoding method provided in embodiment 3 may be used to obtain performance equivalent to that of embodiment 3, and details will not be described herein.

Embodiment 8: The application scenario is a 4x200G interface, the information bit length of the inner code encoding is 120 bits, a 2:1 multiplexer is used, and lane deskew is used.

Based on embodiment 7, this embodiment considers the use of a 2:1 multiplexer, and a newly designed convolutional interleaver is used accordingly.

Specifically, based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in FIG. 3(a), the transmitting processing module performs alignment marker lock on the 8-lane data streams based on known alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 herein may be considered as PCS lanes 0 to 7 of the 200G 0th channel, 1st channel, 2nd channel, or 3rd channel, respectively. The transmitting processing module then performs lane de-skew on the 32-lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31, lane reordering is performed on the data in the eight lanes, and the data in the eight lanes can be arranged in a specified sequence. Finally, the data in the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in Figure 7.

The 32 lane data streams on which lane rearrangement is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to the channel transmission medium for transmission.

In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately on the n = 32 PCS lane data streams to obtain n = 32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. Figure 16(a) shows the configuration of a convolutional interleaver including p = 3 delay lines. The three delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbol, i.e., no delay.

As shown in FIG. 16(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (6t) and C _r (6t+1) represent the two RS symbols in the lane data stream currently input to delay line 0, and C _r (6t-12Q) and C _r (6t-12Q+1) are the two RS symbols output from delay line 0; C _r (6t+2) and C _r (6t+3) represent the two RS symbols in the lane data stream subsequently input to delay line 1, and C _r (6t-6Q+2) and C _r (6t-6Q+3) are the two RS symbols output from delay line 1; C _r (6t+4) and C _r (6t+5) represent the two RS symbols in the lane data stream subsequently input to delay line 2, and C _r (6t+4) and C _r Cr(6t+5) are the two RS symbols output from delay line 2; _Cr (6t+6) and _Cr (6t+7) represent the two RS symbols in the lane data stream that are subsequently input to delay line 0, and _Cr (6t-12Q+6) and _Cr (6t-12Q+7) are the two RS symbols output from delay line 0; and so on. Referring to Figure 7, it can be seen that when 6Q+2≥136, in other words, Q≥23, the total six RS symbols output by convolutional interleaving, _Cr (6t-12Q), _Cr (6t-12Q+1), _Cr (6t-6Q+2), _Cr (6t-6Q+3), _Cr (6t+4), and _Cr (6t+5), are from six different RS codewords.

20 is a schematic diagram of a ninth structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 20, in a possible implementation, Q=23 is selected, and a specific structure of the convolutional interleaver is shown in FIG. 20. The corresponding interleaving latency is approximately 46*2*3/2=138 RS symbols. The convolutional interleaver shown in FIG. 20 performs convolutional interleaving separately on the 32 PCS lane data streams to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 7. It is not difficult to understand that any RS symbol in first data streams 0 to 7, any RS symbol in first data streams 8 to 15, any RS symbol in first data streams 16 to 23, and any RS symbol in first data streams 24 to 31 are from different RS codewords. Therefore, the 32 first data streams include G=4 first data stream subsets, with first data streams 0 to 7 in first data stream subset 0, first data streams 8 to 15 in first data stream subset 1, first data streams 16 to 23 in first data stream subset 2, and first data streams 24 to 31 in first data stream subset 3.

In this embodiment, possible implementations of the multiplexing shown in FIG. 13 are as follows: G=4, K=2, and m=16. Sixteen 2:1 multiplexers are included. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. Two first data streams, selected from any two of first data stream subset 0, first data stream subset 1, first data stream subset 2, and first data stream subset 3 , are used as inputs to the 2:1 multiplexers. A corresponding specific implementation of the 2:1 multiplexer is shown in FIG. 17(a). Multiplexed input data stream 0 and multiplexed input data stream 1 of 2 :1 multiplexer i (0≦i≦15) correspond to first data stream i and first data stream (i+16), respectively. In the figure,
denotes consecutive Δ=6 RS symbols of the multiplexed input data stream j (0≦j≦1) of the 2:1 multiplexer, where the symbols are from six different outer code RS code words. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner every six RS symbols, i.e., the output data sequence is
The 12 consecutive RS symbols in the output data stream are from 12 different RS codewords. Note that because K<G, if Δ=1, 2, or 3, the 12 consecutive RS symbols in the second data stream can still be from 12 different RS codes.

Inner code encoding is performed separately for the 16 second data streams, and the inner code encoding method for the 16 second data streams can be the same as that of embodiment 1 using the encoding method provided in embodiment 1. Details will not be described in this specification.

Embodiment 9: The application scenario is a 4x200G interface, the information bit length of the inner code encoding is 160 bits, a 2:1 multiplexer is used, and lane deskew is used.

Based on embodiment 8, in this embodiment, an inner code with a code length of 160 bits is considered, and a newly designed convolutional interleaver is used accordingly.

Specifically, in this embodiment, the convolutional interleaver structure shown in Figure 18(a) is used, which includes p = 4 delay lines. The four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

As shown in FIG. 18(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (8t) and C _r (8t+1) represent the two RS symbols in the lane data stream currently input to delay line 0, and C _r (8t-24Q) and C _r (8t-24Q+1) are the two RS symbols output from delay line 0; C _r (8t+2) and C _r (8t+3) represent the two RS symbols in the lane data stream subsequently input to delay line 1, and C _r (8t-16Q+2) and C _r (8t-16Q+3) are the two RS symbols output from delay line 1; C _r (8t+4) and C _r (8t+5) represent the two RS symbols in the lane data stream subsequently input to delay line 2, and C _r (8t-8Q+4) and C _r (8t-8Q+5) are the two RS symbols output from delay line 2; _Cr (8t+6) and _Cr (8t+7) represent the two RS symbols in the lane data stream that are subsequently input to delay line 3, and _Cr (8t+6) and _Cr (8t+7) are the two RS symbols output from delay line 3; _Cr (8t+8) and _Cr (8t+9) represent the two RS symbols in the lane data stream that are subsequently input to delay line 0, and _Cr (8t-24Q+8) and _Cr (8t-24Q+9) are the two RS symbols output from delay line 0; and so on. Referring to Figure 7, it can be seen that when 8Q+2≧136, in other words, Q≧17, the total eight RS symbols output by convolutional interleaving, _Cr (8t-24Q), _Cr (8t-24Q+1), _Cr (8t-16Q+2), _Cr (8t-16Q+3), _Cr (8t-8Q+4), _Cr (8t-8Q+5), _Cr (8t+6), and _Cr (8t+7), are from eight different RS codewords.

Figure 21 is a schematic diagram of a tenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 21, in a possible implementation, Q = 17 is selected, and the specific structure of the convolutional interleaver is shown in Figure 21. The corresponding interleaving latency is approximately 51 * 2 * 4 / 2 = 204 RS symbols.

The convolutional interleaver shown in FIG. 21 performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 7. It is not difficult to see that any RS symbol in first data streams 0 to 7, any RS symbol in first data streams 8 to 15, any RS symbol in first data streams 16 to 23, and any RS symbol in first data streams 24 to 31 are from different RS codewords. Therefore, the 32 first data streams include G = 4 first data stream subsets, where first data streams 0 to 7 are first data stream subset 0, first data streams 8 to 15 are first data stream subset 1, first data streams 16 to 23 are first data stream subset 2, and first data streams 24 to 31 are first data stream subset 3.

In this embodiment, possible implementations of the multiplexing shown in FIG. 13 are as follows: G=4, K=2, and m=16. Sixteen 2:1 multiplexers are included. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. Two first data streams, selected from any two of first data stream subset 0, first data stream subset 1, first data stream subset 2, and first data stream subset 3 , are used as inputs to the 2:1 multiplexers. A corresponding specific implementation of the 2:1 multiplexer is shown in FIG. 17(a). Multiplexed input data stream 0 and multiplexed input data stream 1 of 2 :1 multiplexer i (0≦i≦15) correspond to first data stream i and first data stream (i+16), respectively. In the figure,
denotes consecutive Δ=8 RS symbols of the multiplexed input data stream j (0≦j≦1) of the 2:1 multiplexer, where the symbols are from eight different outer code RS code words. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner every eight RS symbols, i.e., the output data sequence is
The 16 consecutive RS symbols in the output data stream are from 16 different RS codewords. Note that because K<G, if Δ=1, 2, or 4, the 16 consecutive RS symbols in the second data stream can still be from 16 different RS codes.

Inner code encoding is performed separately for the 16 second data streams, and the inner code encoding method for the 16 second data streams can use the encoding method provided in embodiment 3 to obtain performance equivalent to that of embodiment 3. Details will not be described in this specification.

Embodiment 10: The application scenario is a 4x200G interface, the information bit length of the inner code encoding is 160 bits, and lane symbol alignment is used.

Based on any one of embodiments 7 to 9, this embodiment provides a solution with lower latency.

Based on the aforementioned schematic diagram of the data processing of the transmitting processing module shown in Figure 3(d), the transmitting processing module performs alignment marker lock on the eight lane data streams based on the known alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. In this specification, PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 may be considered as PCS lanes 0 to 7 of the 200G zeroth channel, first channel, second channel, or third channel, respectively. The transmitting processing module then performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. The 32 aligned lane data streams are sent directly to the designated processor, including multiplexing, for processing and then to the inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the processed data stream is sent to the channel transmission medium for transmission.

In a possible implementation, when both the multiplexing and inner code encoding schemes of this embodiment use the solution of embodiment 7, the concatenated codes in the scheme are under AWGN, and the performance is comparable to that of the solution of embodiment 7, with lower overall latency. However, the solution of this embodiment has poorer resistance to system burst errors than the solution of embodiment 7. This solution is applicable to some scenarios requiring lower latency.

In another possible implementation, when both the multiplexing and inner code encoding schemes of this embodiment use the solution of embodiment 8, the concatenated codes in the scheme are under AWGN, and the performance is comparable to that of the solution of embodiment 8, with lower overall latency. However, the solution of this embodiment has poorer resistance to system burst errors than the solution of embodiment 8. This solution is applicable to some scenarios requiring lower latency.

In yet another possible implementation, when both the multiplexing and inner code encoding schemes of this embodiment use the solution of embodiment 9, the concatenated codes in the scheme are under AWGN, and the performance is comparable to that of the solution of embodiment 9, with lower overall latency. However, the solution of this embodiment has poorer resistance to system burst errors compared to the solution of embodiment 9. This solution is applicable to some scenarios requiring lower latency.

Embodiment 11: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 120 bits or 160 bits, an 8:1 multiplexer is used, and lane deskew is used.

In this embodiment, the host interface is an 8x100G interface at 100Gb/s per lane, and it is assumed that the "100G RS-FEC-Int" mode is used. For details about the interface, see IEEE Std 802.3ck™/D3.0.

Based on the aforementioned schematic data processing diagram of the transmitter processing module shown in Figure 3(c), the transmitter processing module performs alignment marker lock on the four lane data stream based on known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31 can be considered as FEC lanes 0 to 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channel, respectively. The transmit-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Next, based on the alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31, lane reordering can be performed on the four lanes of data to arrange the four lanes of data in a specified sequence. Finally, the 32 lanes of data can be arranged in a specified sequence. One sequence is for the lane data streams to be sorted from top to bottom from 0 to 31, which is the same as that in Figure 11. The 32 lane data streams that undergo lane reordering are not convolutionally interleaved but are directly multiplexed to obtain a total of 16 second data streams, which are then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code-encoded data streams, the processed data streams are sent to a channel transmission medium for transmission.

Refer to the PCS lane data streams shown in Figure 8. It is not difficult to see that any RS symbol in lane data streams 0 through 3, any RS symbol in lane data streams 4 through 7, any RS symbol in lane data streams 8 through 11, any RS symbol in lane data streams 12 through 15, any RS symbol in lane data streams 16 through 19, any RS symbol in lane data streams 20 through 23, any RS symbol in lane data streams 24 through 27, and any RS symbol in lane data streams 28 through 31 are all from different RS codewords. Because no convolutional interleaving is performed on the lane data streams, lane data streams 0 through 31 are equivalent to the first data streams 0 through 31. Therefore, the 32 first data streams include G=8 first data stream subsets, where first data streams 0 to 3 are first data stream subset 0, first data streams 4 to 7 are first data stream subset 1, first data streams 8 to 11 are first data stream subset 2, first data streams 12 to 15 are first data stream subset 3, first data streams 16 to 19 are first data stream subset 4, first data streams 20 to 23 are first data stream subset 5, first data streams 24 to 27 are first data stream subset 6, and first data streams 28 to 31 are first data stream subset 7.

13 used in this embodiment is as follows: G=8, K=8, m=4, and multiplexing is performed on 32 lane data streams to obtain four second data streams. As eight input data streams of 8:1 multiplexer i (0≦i≦3), one data stream in first data stream subset 0, one data stream in first data stream subset 1, one data stream in first data stream subset 2, one data stream in first data stream subset 3, one data stream in first data stream subset 4, one data stream in first data stream subset 5, one data stream in first data stream subset 6, and one data stream in first data stream subset 7 are used , for a total of eight lane data streams . A specific embodiment is shown in FIG. 17(c). Multiplexer i (0≦i≦3) corresponds to multiplexed input data streams 0 through 7 of the 8:1 multiplexer using first data stream i, first data stream (i+16), first data stream (i+8), first data stream (i+24), first data stream (i+4), first data stream (i+20), first data stream (i+12), and first data stream (i+28), respectively.
denotes consecutive Δ=2 RS symbols of the multiplexed input data stream j (0≦j≦7) of the 8:1 multiplexer, where the symbols are from two different outer code RS code words. The 8:1 multiplexer outputs the data in the eight input data streams to the output data stream in a polling manner every two RS symbols, i.e., the output data sequence is
and the 16 consecutive RS symbols in the output data stream are from 16 different RS codewords. Note that, because K≦G, when Δ=1, the 16 consecutive RS symbols in the second data stream can still be from 16 different RS codes.

22 is a schematic diagram of a fifth structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 22, multiplexer i (0≦i≦3) uses first data stream i, first data stream (i+4), first data stream (i+8), first data stream (i+12), first data stream (i+16), first data stream (i+20), first data stream (i+24), and first data stream (i+28) to correspond to multiplexed input data streams 0 to 7 of the 8:1 multiplexer, respectively. In the figure,
denotes consecutive Δ=2 RS symbols of the multiplexed input data stream j (0≦j≦7) of the 8:1 multiplexer, where the symbols are from two different outer code RS code words. The 8:1 multiplexer outputs the data in the eight input data streams to the output data stream in a polling manner every two RS symbols, i.e., the output data sequence is
and the 16 consecutive RS symbols in the output data stream are from 16 different RS codewords. Note that, because K≦G, when Δ=1, the 16 consecutive RS symbols in the second data stream can still be from 16 different RS codes.

Inner code encoding is performed separately on the four second data streams. The inner code encoding method may be the encoding method provided in embodiment 1 to obtain performance equivalent to that of embodiment 1; or the encoding method provided in embodiment 3 may be used to obtain performance equivalent to that of embodiment 3, and details will not be described herein.

Embodiment 12: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 120 bits or 160 bits, a 4:1 multiplexer is used, and lane deskew is used.

Based on the solution of embodiment 11, this embodiment provides a second low-latency implementation solution when a 4:1 multiplexer is used for multiplexing.

Based on the aforementioned schematic data processing diagram of the transmitter processing module shown in Figure 3(a), the transmitter processing module performs alignment marker lock on the four lane data stream based on known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31 can be considered as FEC lanes 0 to 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channel, respectively. The transmit-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31, lane reordering can be performed on the data of the four lanes to arrange the data of the four lanes in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in Figure 11.

The 32 lane data streams on which lane rearrangement is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to the channel transmission medium for transmission.

In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately on the n = 32 PCS lane data streams to obtain n = 32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. Figure 19(a) shows the configuration of a convolutional interleaver including p = 2 delay lines. The two delay lines each include Q storage units and 0 storage units, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 2Q symbols, and the delay value of delay line 1 is 0 symbol, i.e., no delay.

As shown in FIG. 19(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (4t) and C _r (4t+1) represent the two RS symbols in the lane data stream currently input to delay line 0, and Cr(4t-4Q) and Cr(4t-4Q+1) are the two RS symbols output from delay line 0; C _r (4t+2) and C _r (4t+3) represent the two RS symbols in the lane data stream subsequently input to delay line 1, and C _r (4t+2) and C _r (4t+3) are the two RS symbols output from delay line 1; C _r (4t+4) and C _r (4t+5) represent the two RS symbols in the lane data stream subsequently input to delay line 0, and Cr(4t-4Q+4) and Cr(4t-4Q+5) are the two RS symbols output from delay line 0; and so on. Referring to Figure 8, it can be seen that when 4Q+2≧272, i.e., Q≧68, the four consecutive RS symbols Cr(4t−4Q), Cr(4t−4Q+1), Cr(4t+2), and Cr(4t+3) output through convolutional interleaving are from four different RS codewords.

Figure 23 is a schematic diagram of an eleventh structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 23, in a possible implementation, Q = 68 is selected, and the specific structure of the convolutional interleaver is shown in Figure 23. The corresponding interleaving latency is approximately 68 * 2 * 2 / 2 = 136 RS symbols.

The convolutional interleaver shown in FIG. 23 performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 8. It is not difficult to see that any RS symbol in lane data streams 0 to 3, any RS symbol in lane data streams 4 to 7, any RS symbol in lane data streams 8 to 11, any RS symbol in lane data streams 12 to 15, any RS symbol in lane data streams 16 to 19, any RS symbol in lane data streams 20 to 23, any RS symbol in lane data streams 24 to 27, and any RS symbol in lane data streams 28 to 31 are from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, where first data streams 0 to 3 are first data stream subset 0, first data streams 4 to 7 are first data stream subset 1, first data streams 8 to 11 are first data stream subset 2, first data streams 12 to 15 are first data stream subset 3, first data streams 16 to 19 are first data stream subset 4, first data streams 20 to 23 are first data stream subset 5, first data streams 24 to 27 are first data stream subset 6, and first data streams 28 to 31 are first data stream subset 7.

In this embodiment, possible implementations of the multiplexing shown in FIG. 13 are as follows: G=8, K=4, and m=8. Eight 4:1 multiplexers are included. Each multiplexer multiplexes four first data streams to obtain one second data stream, generating a total of eight second data streams. Four first data streams, selected from any four of first data stream subsets 0 to 7 , are used as inputs to the 4:1 multiplexers. A specific implementation is shown in FIG. 17(b). The multiplexed input data streams 0 to 3 of 4:1 multiplexer i (0≦i≦7) correspond to first data stream i, first data stream (i+16), first data stream (i+8), and first data stream (i+24), respectively. In the figure,
denotes consecutive Δ=4 RS symbols of the multiplexed input data stream j (0≦j≦3) of the 4:1 multiplexer, where the symbols are from four different outer code RS code words. The 4:1 multiplexer outputs the data in the four input data streams to the output data stream in a polling manner every four RS symbols, i.e., the output data sequence is
The 16 consecutive RS symbols in the output data stream are from 16 different RS codewords. Note that, because K≦G, when Δ=1 or 2, the 16 consecutive RS symbols in the second data stream can still be from 16 different RS codes.

24 is a schematic diagram of a sixth structure of a multiplexer according to an embodiment of the present application. As shown in FIG. 24, multiplexer i (0≦i≦3) uses first data stream i, first data stream (i+8), first data stream (i+16), and first data stream (i+24) to correspond to multiplexed input data streams 0 to 3 of the 4:1 multiplexer, respectively. In the figure,
denotes consecutive Δ=4 RS symbols of the multiplexed input data stream j (0≦j≦3) of the 4:1 multiplexer, where the symbols are from four different outer code RS code words. The 4:1 multiplexer outputs the data in the four input data streams to the output data stream in a polling manner every four RS symbols, i.e., the output data sequence is
The 16 consecutive RS symbols in the output data stream are from 16 different RS codewords. Note that, because K≦G, when Δ=1 or 2, the 16 consecutive RS symbols in the second data stream can still be from 16 different RS codes.

Inner code encoding is performed separately on the eight second data streams. The inner code encoding method may be the encoding method provided in embodiment 1 to obtain performance equivalent to that of embodiment 1; or the encoding method provided in embodiment 3 may be used to obtain performance equivalent to that of embodiment 3, and details will not be described herein.

Embodiment 13: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 120 bits, a 2:1 multiplexer is used, and lane deskew is used.

Based on embodiment 12, in this embodiment, a 2:1 multiplexer and an inner code with an information length of 120 bits are used for multiplexing, and a newly designed convolutional interleaver and multiplexing are correspondingly used.

In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately on the n = 32 PCS lane data streams to obtain n = 32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. Figure 16(a) shows the configuration of a convolutional interleaver including p = 3 delay lines. The three delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbol, i.e., no delay.

As shown in FIG. 16(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (6t) and C _r (6t+1) represent the two RS symbols in the lane data stream currently input to delay line 0, and C _r (6t-12Q) and C _r (6t-12Q+1) are the two RS symbols output from delay line 0; C _r (6t+2) and C _r (6t+3) represent the two RS symbols in the lane data stream subsequently input to delay line 1, and C _r (6t-6Q+2) and C _r (6t-6Q+3) are the two RS symbols output from delay line 1; C _r (6t+4) and C _r (6t+5) represent the two RS symbols in the lane data stream subsequently input to delay line 2, and C _r (6t+4) and C _r Cr(6t+5) are the two RS symbols output from delay line 2; _Cr (6t+6) and _Cr (6t+7) represent the two RS symbols in the lane data stream that are subsequently input to delay line 0, and _Cr (6t-12Q+6) and _Cr (6t-12Q+7) are the two RS symbols output from delay line 0; and so on. Referring to Figure 8, it can be seen that when 6Q+2≥272, in other words, Q≥45, the total six RS symbols output by convolutional interleaving, _Cr (6t-12Q), _Cr (6t-12Q+1), _Cr (6t-6Q+2), _Cr (6t-6Q+3), _Cr (6t+4), and _Cr (6t+5), are from six different RS codewords.

Figure 25 is a schematic diagram of a twelfth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 25, in a possible implementation, Q = 45 is selected, and the specific structure of the convolutional interleaver is shown in Figure 25. The corresponding interleaving latency is approximately 90 * 2 * 3 / 2 = 270 RS symbols.

The convolutional interleaver shown in FIG. 25 performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 8. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, where first data streams 0 to 3 are first data stream subset 0, first data streams 4 to 7 are first data stream subset 1, first data streams 8 to 11 are first data stream subset 2, first data streams 12 to 15 are first data stream subset 3, first data streams 16 to 19 are first data stream subset 4, first data streams 20 to 23 are first data stream subset 5, first data streams 24 to 27 are first data stream subset 6, and first data streams 28 to 31 are first data stream subset 7.

In this embodiment, possible implementations of the multiplexing shown in FIG. 13 are as follows: G=8, K=2, and m=16. Sixteen 2:1 multiplexers are included. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. Two first data streams, selected from any two of first data stream subsets 0 to 7 , are used as inputs to the 2:1 multiplexers. A corresponding specific implementation of the 2:1 multiplexer is shown in FIG. 17(a). Multiplexed input data stream 0 and multiplexed input data stream 1 of 2 :1 multiplexer i (0≦i≦15) correspond to first data stream i and first data stream (i+16), respectively. In the figure,
denotes consecutive Δ=6 RS symbols of the multiplexed input data stream j (0≦j≦1) of the 2:1 multiplexer, where the symbols are from six different outer code RS code words. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner every 6 RS symbols, i.e., the output data sequence is
The 12 consecutive RS symbols in the output data stream are from 12 different RS codewords. Note that since K≦G, if Δ=1, 2, or 3, the 12 consecutive RS symbols in the second data stream can still be from 12 different RS codes.

The solution for encoding the 16 second data streams output by multiplexing can use the solution of embodiment 1 and obtain performance equivalent to that of embodiment 1, and details will not be described again in this specification.

Embodiment 14: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 160 bits, a 2:1 multiplexer is used, and lane deskew is used.

Based on embodiment 12, in this embodiment, a 2:1 multiplexer and an inner code with an information length of 160 bits are used for multiplexing, and a newly designed convolutional interleaver and multiplexing are used correspondingly.

In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately on the n = 32 PCS lane data streams to obtain n = 32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure. Figure 18(a) shows the configuration of a convolutional interleaver including p = 4 delay lines. The four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, delay line 0 has a delay value of 6Q symbols, delay line 1 has a delay value of 4Q symbols, delay line 2 has a delay value of 2Q symbols, and delay line 3 has a delay value of 0 symbol, i.e., no delay.

As shown in FIG. 18(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (8t) and C _r (8t+1) represent the two RS symbols in the lane data stream currently input to delay line 0, and C _r (8t-24Q) and C _r (8t-24Q+1) are the two RS symbols output from delay line 0; C _r (8t+2) and C _r (8t+3) represent the two RS symbols in the lane data stream subsequently input to delay line 1, and C _r (8t-16Q+2) and C _r (8t-16Q+3) are the two RS symbols output from delay line 1; C _r (8t+4) and C _r (8t+5) represent the two RS symbols in the lane data stream subsequently input to delay line 2, and C _r (8t-8Q+4) and C _r (8t-8Q+5) are the two RS symbols output from delay line 2; _Cr (8t+6) and _Cr (8t+7) represent the two RS symbols in the lane data stream that are then subsequently input to delay line 3, and _Cr (8t+6) and _Cr (8t+7) are the two RS symbols output from delay line 3; _Cr (8t+8) and _Cr (8t+9) represent the two RS symbols in the lane data stream that are then subsequently input to delay line 0, and _Cr (8t-24Q+8) and _Cr (8t-24Q+9) are the two RS symbols output from delay line 0; and so on. Referring to Figure 8, it can be seen that when 8Q+2≧272, in other words, Q≧34, the total of eight RS symbols _Cr (8t-24Q), _Cr (8t-24Q+1), _Cr (8t-24Q+2), _Cr (8t-16Q+3), _Cr (8t-8Q+4), _Cr (8t-8Q+5), _Cr (8t+6), and _Cr (8t+7) output by convolutional interleaving are from eight different RS codewords.

Figure 26 is a schematic diagram of a thirteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 26, in a possible implementation, Q = 34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 26. The corresponding interleaving latency is approximately 102 * 2 * 4 / 2 = 408 RS symbols.

The convolutional interleaver shown in FIG. 26 performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS lane data streams shown in FIG. 8. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, where first data streams 0 to 3 are first data stream subset 0, first data streams 4 to 7 are first data stream subset 1, first data streams 8 to 11 are first data stream subset 2, first data streams 12 to 15 are first data stream subset 3, first data streams 16 to 19 are first data stream subset 4, first data streams 20 to 23 are first data stream subset 5, first data streams 24 to 27 are first data stream subset 6, and first data streams 28 to 31 are first data stream subset 7.

In this embodiment, possible implementations of the multiplexing shown in FIG. 13 are as follows: G=8, K=2, and m=16. Sixteen 2:1 multiplexers are included. Each multiplexer multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. Two first data streams, selected from any two of first data stream subsets 0 to 7 , are used as inputs to the 2:1 multiplexers. A corresponding specific implementation of the 2:1 multiplexer is shown in FIG. 17(a). Multiplexed input data stream 0 and multiplexed input data stream 1 of 2 :1 multiplexer i (0≦i≦15) correspond to first data stream i and first data stream (i+16), respectively. In the figure,
denotes consecutive Δ=8 RS symbols of the multiplexed input data stream j (0≦j≦1) of the 2:1 multiplexer, where the symbols are from eight different outer code RS code words. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner every eight RS symbols, i.e., the output data sequence is
The 16 consecutive RS symbols in the output data stream are from 16 different RS codewords. Note that since K≦G, if Δ=1, 2, or 4, the 16 consecutive RS symbols in the second data stream can still be from 16 different RS codes.

The method for performing inner code encoding on the 16 second data streams output by multiplexing can use the inner code encoding method of embodiment 3, and achieves performance equivalent to that of embodiment 3, and details will not be described again in this specification.

Embodiment 15: The application scenario is an 8x100G interface, and lane symbol alignment is used.

Based on any of embodiments 11 to 14, this embodiment provides a solution with lower latency.

Based on the aforementioned schematic data processing diagram of the transmitting-side processing module shown in FIG. 3(b), the transmitting-side processing module performs alignment marker lock on the four lane data streams based on known alignment markers for FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. The transmitting-side processing module then performs alignment on the 32 lane data streams based on two RS symbols to obtain 32 aligned lane data streams. Convolutional interleaving is performed separately on the 32 lane data streams to obtain 32 first data streams, and multiplexing is performed on the first data streams to obtain 4, 8, or 16 second data streams, which are then sent to the inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the processed data stream is sent to the channel transmission medium for transmission.

In this embodiment, if the processor including the convolutional interleaving, multiplexing, and inner code encoding is the same as that of the solution in embodiment 11, the concatenated code in the scheme is under AWGN, and the performance is equivalent to that of the solution in embodiment 11, but the solution in this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

In this embodiment, when the processor and inner code encoding including convolutional interleaving and multiplexing are the same as those in the solution of embodiment 12, the concatenated code in the scheme is under AWGN and the performance is equivalent to that of the solution of embodiment 12, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

In this embodiment, when the processor and inner code encoding including convolutional interleaving and multiplexing are the same as those in the solution of embodiment 13, the concatenated code in the scheme is under AWGN and the performance is equivalent to that of the solution of embodiment 13, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

In this embodiment, when the processor and inner code encoding including convolutional interleaving and multiplexing are the same as those in the solution of embodiment 14, the concatenated code in the scheme is under AWGN and the performance is equivalent to that of the solution of embodiment 14, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

Embodiment 16: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 120 bits or 160 bits, an 8:1 multiplexer is used, and lane deskew is used.

In this embodiment, the host interface is an 8x100G interface at 100Gb/s per lane, and it is assumed that "100G RS-FEC" mode is used. For details about the interface, see IEEE Std 802.3ck™/D3.0.

Based on the aforementioned schematic data processing diagram of the transmitter processing module shown in Figure 3(a), the transmitter processing module performs alignment marker lock on the four lane data stream based on known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31 can be considered as FEC lanes 0 to 3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channel, respectively. The transmit-side processing module then performs lane de-skew on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers of FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31, lane reordering can be performed on the data of the four lanes to arrange the data of the four lanes in a specified sequence. Finally, the data of the 32 lanes can be arranged in a specified sequence. One sequence is for the lane data stream to be sorted from top to bottom from 0 to 31, which is the same as in Figure 9.

The 32 lane data streams on which lane rearrangement is performed are sent to a special processor, including a convolutional interleaving and multiplexing processor, for interleaving and randomizing the data sequence, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to the channel transmission medium for transmission.

In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, which is performed separately on the n = 32 FEC lane data streams to obtain n = 32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

Figure 27(a) is a schematic diagram of a fourteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 27(a), p = 2 delay lines are included. The two delay lines each include Q storage units and 0 storage units, and each storage unit is configured to store d = 1 symbols. That is, the delay value of delay line 0 is Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

As shown in Figure 27(a), _Cr (•) represents one RS symbol in lane data stream r (0≦r≦n-1). For example, _Cr (2t) represents one RS symbol in the lane data stream currently input to delay line 0, and _Cr (2t-2Q) is one RS symbol output from delay line 0; Cr(2t+1) represents one RS symbol in the lane data stream subsequently input to delay line 1, _{and Cr(2t+1) is one RS symbol output from delay line 1; Cr ( 2t} +2) represents one RS symbol in the lane data stream subsequently input to delay line 0, and _Cr (2t-2Q+2) is one RS symbol output from delay line 0; and so on. Referring to Figure 9, it can be seen that when 2Q+1≧136, i.e., Q≧68, two consecutive RS symbols, C _r (2t−2Q) and C _r (2t+1), output through convolutional interleaving are from two different RS codewords.

Figure 27(b) is a schematic diagram of a fifteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 27(b), in a possible implementation, Q = 68 is selected, and the specific structure of the convolutional interleaver is shown in Figure 27(b). The corresponding interleaving latency is approximately 68 * 2 / 2 = 68 RS symbols.

The convolutional interleaver shown in FIG. 27(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in FIG. 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, where first data streams 0 to 3 are first data stream subset 0, first data streams 4 to 7 are first data stream subset 1, first data streams 8 to 11 are first data stream subset 2, first data streams 12 to 15 are first data stream subset 3, first data streams 16 to 19 are first data stream subset 4, first data streams 20 to 23 are first data stream subset 5, first data streams 24 to 27 are first data stream subset 6, and first data streams 28 to 31 are first data stream subset 7.

In this embodiment, the 8:1 multiplexing processing structure of embodiment 11 is used, and four second data streams can be obtained, with all 16 consecutive RS symbols in each second data stream coming from 16 different RS code words.

Inner code encoding is performed separately on the four second data streams. The inner code encoding method may be the encoding method provided in embodiment 1 to obtain performance equivalent to that of embodiment 1; or the encoding method provided in embodiment 3 may be used to obtain performance equivalent to that of embodiment 3, and details will not be described herein.

Embodiment 17: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 120 bits, a 4:1 multiplexer is used, and lane deskew is used.

Based on the solution of embodiment 16, in this embodiment, when the length of the inner code information is 120 bits and a 4:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing are used accordingly.

In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, which is performed separately on the n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

Figure 28(a) is a schematic diagram of a sixteenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 28(a), p = 3 delay lines are included. The p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 1 symbols. That is, the delay value of delay line 0 is 2Q symbols, the delay value of delay line 1 is Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

As shown in FIG. 28(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, Cr(3t) represents one RS symbol in the lane data stream currently input to delay line 0, and Cr(3t-6Q) is one RS symbol output from delay line 0; Cr(3t+1) represents one RS symbol in the lane data stream subsequently input to delay line 1, and Cr(3t-3Q+1) is one RS symbol output from delay line 1; Cr(3t+2) represents one RS symbol in the lane data stream subsequently input to delay line 2, and Cr(3t+2) is one RS symbol output from delay line 2; Cr(3t+3) represents one RS symbol in the lane data stream subsequently input to delay line 0, and Cr(3t-6Q+3) is one RS symbol output from delay line 0; and so on. Referring to Figure 9, it can be seen that when 3Q+1≧136, i.e., Q≧45, the total three RS symbols output through convolutional interleaving, Cr(3t-6Q), Cr(3t-3Q+2), and Cr(3t+2), are from three different RS codewords.

Figure 28(b) is a schematic diagram of the seventeenth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 28(b), in a possible implementation, Q = 45 is selected, and the specific structure of the convolutional interleaver is shown in Figure 28(b). The corresponding interleaving latency is approximately 90 * 3/2 = 135 RS symbols.

The convolutional interleaver shown in Figure 28(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in Figure 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, where first data streams 0 to 3 are first data stream subset 0, first data streams 4 to 7 are first data stream subset 1, first data streams 8 to 11 are first data stream subset 2, first data streams 12 to 15 are first data stream subset 3, first data streams 16 to 19 are first data stream subset 4, first data streams 20 to 23 are first data stream subset 5, first data streams 24 to 27 are first data stream subset 6, and first data streams 28 to 31 are first data stream subset 7.

In this embodiment, the multiplexing processing structure of embodiment 12 is used, and when Δ = 1 or 3, eight second data streams can be obtained, with all 12 consecutive RS symbols in each second data stream coming from 12 different RS code words.

The solution for encoding the eight second data streams output by multiplexing can use the solution of embodiment 1 and obtain performance equivalent to that of embodiment 1, and details will not be described again in this specification.

Embodiment 18: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 160 bits, a 4:1 multiplexer is used, and lane deskew is used.

Based on the solution of embodiment 16, this embodiment provides a second low-latency implementation solution in which the length of the inner code information is 160 bits and a 4:1 multiplexer is used for multiplexing, and a newly designed interleaver and multiplexing are used correspondingly.

In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, which is performed separately on the n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

Figure 29(a) is a schematic diagram of an 18th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 29(a), p = 4 delay lines are included. The p = 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 1 symbols. That is, the delay value of delay line 0 is 3Q symbols, the delay value of delay line 1 is 2Q symbols, the delay value of delay line 2 is Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

As shown in FIG. 29(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (4t) represents one RS symbol in the lane data stream currently input to delay line 0, and Cr(4t-12Q) is one RS symbol output from delay line 0; C _r (4t+1) represents one RS symbol in the lane data stream subsequently input to delay line 1, and Cr(4t-8Q+1) is one RS symbol output from delay line 1; C _r (4t+2) represents one RS symbol in the lane data stream subsequently input to delay line 2, and Cr(4t-4Q+2) is one RS symbol output from delay line 2; C _r (4t+3) represents one RS symbol in the lane data stream subsequently input to delay line 3, and _Cr (4t+3) is one _RS symbol output from delay line 3; Cr(4t-8Q+1), Cr(4t-4Q+2), and Cr(4t+3) are RS symbols in the lane data stream that are subsequently input to delay line 0, Cr(4t-12Q), Cr(4t-8Q+1), Cr(4t-4Q+2), and Cr(4t+3), respectively, and so on. Referring to FIG. 9, it can be seen that when 4Q+1≧136, i.e., Q≧34, the total of four RS symbols that are sequentially output by convolutional interleaving, _Cr (4t-12Q), _Cr (4t-8Q+1), _Cr (4t-4Q+2), and _Cr (4t+3), are from four different RS codewords.

Figure 29(b) is a schematic diagram of a 19th structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 29(b), in a possible implementation, Q = 34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 29(b). The corresponding interleaving latency is approximately 102 * 4/2 = 204 RS symbols.

The convolutional interleaver shown in Figure 29(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in Figure 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, where first data streams 0 to 3 are first data stream subset 0, first data streams 4 to 7 are first data stream subset 1, first data streams 8 to 11 are first data stream subset 2, first data streams 12 to 15 are first data stream subset 3, first data streams 16 to 19 are first data stream subset 4, first data streams 20 to 23 are first data stream subset 5, first data streams 24 to 27 are first data stream subset 6, and first data streams 28 to 31 are first data stream subset 7.

In this embodiment, the multiplexing processing structure of embodiment 13 is used, and when Δ = 1, 2, or 4, eight second data streams can be obtained, with all 16 consecutive RS symbols in each second data stream coming from 16 different RS code words.

Inner code encoding is performed separately for the eight second data streams, and the inner code encoding method for the eight second data streams can be the same as that of embodiment 3 by using the inner code encoding method provided in embodiment 3. Details will not be described in this specification.

Embodiment 19: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 120 bits, a 2:1 multiplexer is used, and lane deskew is used.

Based on the solution of embodiment 16, in this embodiment, when the length of the inner code information is 120 bits and a 4:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing are used accordingly.

In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, which is performed separately on the n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

Figure 30(a) is a schematic diagram of a twentieth structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 30(a), p = 6 delay lines are included. The p = 6 delay lines include 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 1 symbols. That is, the delay value of delay line 0 is 5Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 3Q symbols, the delay value of delay line 3 is 2Q symbols, the delay value of delay line 4 is Q symbols, and the delay value of delay line 5 is 0 symbols, i.e., no delay.

As shown in FIG. 30(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (6t) represents one RS symbol in the lane data stream currently input to delay line 0, C _r (6t-30Q) is one RS symbol output from delay line 0; C _r (6t+1) represents one RS symbol in the lane data stream subsequently input to delay line 1, C _r (6t-24Q+1) is one RS symbol output from delay line 1; C _r (6t+2) represents one RS symbol in the lane data stream subsequently input to delay line 2, C _r (6t-18Q+2) is one RS symbol output from delay line 2; C _r (6t+3) represents one RS symbol in the lane data stream subsequently input to delay line 3, C _r (6t-12Q+3 ₎ is one RS symbol output from delay line 3; (6t+4) represents one RS symbol in the lane data stream that is subsequently input to delay line 4, and C _r (6t-6Q+4) is one RS symbol output from delay line 4; C _r (6t+5) represents one RS symbol in the lane data stream that is subsequently input to delay line 5, and C _r (6t+5) is one RS symbol output from delay line 5; C _r (6t+6) represents one RS symbol in the lane data stream that is subsequently input to delay line 0, and C _r (6t-30Q+6) is one RS symbol output from delay line 0; and so on. Referring to Figure 9, it can be seen that when 6Q+1≧136, i.e., Q≧23, the total of six RS symbols C _r (6t−30Q), C _r (6t−24Q+1), and C _r (6t−18Q+2) output consecutively by convolutional interleaving are from six different RS codewords.

Figure 30(b) is a schematic diagram of the 21st structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 30(b), in a possible implementation, Q = 23 is selected, and the specific structure of the convolutional interleaver is shown in Figure 30(b). The corresponding interleaving latency is approximately 23 * 5 * 6 / 2 = 345 RS symbols.

The convolutional interleaver shown in Figure 30(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in Figure 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, where first data streams 0 to 3 are first data stream subset 0, first data streams 4 to 7 are first data stream subset 1, first data streams 8 to 11 are first data stream subset 2, first data streams 12 to 15 are first data stream subset 3, first data streams 16 to 19 are first data stream subset 4, first data streams 20 to 23 are first data stream subset 5, first data streams 24 to 27 are first data stream subset 6, and first data streams 28 to 31 are first data stream subset 7.

In this embodiment, the multiplexing processing structure of embodiment 13 is used, and when Δ = 1, 2, 3, or 6, 16 second data streams can be obtained, with all 12 consecutive RS symbols in each second data stream coming from 12 different RS code words.

Inner code encoding is performed separately for the 16 second data streams, and the encoding method for the 16 second data streams can achieve performance equivalent to that of embodiment 1 by using the inner code encoding method provided in embodiment 1. Details will not be described in this specification.

Embodiment 20: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 160 bits, a 2:1 multiplexer is used, and lane deskew is used.

Based on the solution of embodiment 16, in this embodiment, when the length of the inner code information is 160 bits and a 2:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing are used accordingly.

In this embodiment, the structure shown in FIG. 11 is used for convolutional interleaving, which is performed separately on the n=32 PCS lane data streams to obtain n=32 first data streams. Convolutional interleaver 0, convolutional interleaver 1, convolutional interleaver 2, ..., convolutional interleaver 31 use the same interleaving structure.

Figure 31(a) is a schematic diagram of a 22nd structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 31(a), p = 8 delay lines are included. The p = 8 delay lines include 7Q storage units, 6Q storage units, 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 1 symbols. That is, the delay value of delay line 0 is 7Q symbols, the delay value of delay line 1 is 6Q symbols, the delay value of delay line 2 is 5Q symbols, the delay value of delay line 3 is 4Q symbols, the delay value of delay line 4 is 3Q symbols, the delay value of delay line 5 is 2Q symbols, the delay value of delay line 6 is Q symbols, and the delay value of delay line 7 is 0 symbols, i.e., no delay.

As shown in FIG. 31(a), C _r (·) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (8t) represents one RS symbol in the lane data stream currently input to delay line 0, and C _r (8t-56Q) is one RS symbol output from delay line 0; C _r (8t+1) represents one RS symbol in the lane data stream subsequently input to delay line 1, and C _r (8t-48Q+1) is one RS symbol output from delay line 1; C _r (8t+2) represents one RS symbol in the lane data stream subsequently input to delay line 2, and C _r (8t-40Q+2) is one RS symbol output from delay line 2; C _r (8t+3) represents one RS symbol in the lane data stream subsequently input to delay line 3, and C _r (8t-32Q+3) is one RS symbol output from delay line ₃ ; C r (8t+4) represents one RS symbol in the lane data stream that is subsequently input to delay line 4, and C _r (8t−24Q+4) is one RS symbol output from delay line 4; C _r (8t+5) represents one RS symbol in the lane data stream that is subsequently input to delay line 5, and C _r (8t−16Q+5) is one RS symbol output from delay line 5; C _r (8t+6) represents one RS symbol in the lane data stream that is subsequently input to delay line 6, and C _r (8t−8Q+6) is one RS symbol output from delay line 6; C _r (8t+7) represents one RS symbol in the lane data stream that is subsequently input to delay line 7, and C _r (8t+7) is one RS symbol output from delay line ₇ ; Cr(8t-56Q+8) represents one RS symbol in the lane data stream that is subsequently input to delay line 0, _Cr (8t-56Q+8) is one RS symbol output from delay line 0, and so on. Referring to Figure 9, it can be seen that when 8Q+1≥136, i.e., Q≥17, the total of eight RS symbols _Cr (8t-56Q), _Cr (8t-48Q+1), _Cr (8t-40Q+2), _Cr (8t-32Q+3), _Cr (8t-24Q+4), _Cr (8t-16Q+5), _Cr (8t-8Q+6), and _Cr (8t+7) that are sequentially output via convolutional interleaving are from eight different RS codewords.

Figure 31(b) is a schematic diagram of the 23rd structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 31(b), in a possible implementation, Q = 17 is selected, and the specific structure of the convolutional interleaver is shown in Figure 31(b). The corresponding interleaving latency is approximately 17 * 7 * 8 / 2 = 476 RS symbols.

The convolutional interleaver shown in Figure 31(b) performs convolutional interleaving on the 32 FEC lane data streams separately to obtain 32 first data streams. See the FEC lane data streams shown in Figure 9. It is not difficult to see that any RS symbol in first data streams 0 to 3, any RS symbol in first data streams 4 to 7, any RS symbol in first data streams 8 to 11, any RS symbol in first data streams 12 to 15, any RS symbol in first data streams 16 to 19, any RS symbol in first data streams 20 to 23, any RS symbol in first data streams 24 to 27, and any RS symbol in first data streams 28 to 31 are from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, where first data streams 0 to 3 are first data stream subset 0, first data streams 4 to 7 are first data stream subset 1, first data streams 8 to 11 are first data stream subset 2, first data streams 12 to 15 are first data stream subset 3, first data streams 16 to 19 are first data stream subset 4, first data streams 20 to 23 are first data stream subset 5, first data streams 24 to 27 are first data stream subset 6, and first data streams 28 to 31 are first data stream subset 7.

In this embodiment, the multiplexing processing structure of embodiment 13 is used, and when Δ = 1, 2, 3, or 8, 16 second data streams can be obtained, with all 16 consecutive RS symbols in each second data stream coming from 16 different RS code words.

Inner code encoding is performed separately for the 16 second data streams, and the inner code encoding method for the 16 second data streams can be the same as that of embodiment 3 by using the inner code encoding method provided in embodiment 3. Details will not be described in this specification.

Embodiment 21: The application scenario is an 8x100G interface, the information bit length of the inner code encoding is 120 bits or 160 bits, and lane symbol alignment is used.

Based on the solution in any of embodiments 16 to 20, this embodiment provides a solution with lower latency.

Based on the aforementioned schematic data processing diagram of the transmitter processing module shown in FIG. 3(d), the transmitter processing module performs alignment marker lock on the four lane data streams based on known alignment markers for FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. The transmitter processing module then performs one symbol-based alignment on the 32 lane data streams to obtain 32 aligned lane data streams. Convolutional interleaving is performed separately on the 32 lane data streams to obtain 32 first data streams, and multiplexing is performed on the first data streams to obtain 4, 8, or 16 second data streams, which are then sent to the inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the processed data stream is sent to the channel transmission medium for transmission.

It should be understood that both the multiplexing and inner code encoding schemes used in this embodiment use the solutions provided in any one of embodiments 16 to 20.

In this embodiment, when the processor including multiplexing and inner code encoding are the same as those in the solution of embodiment 16, the concatenated code in the scheme is under AWGN and the performance is equivalent to that of the solution of embodiment 16, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

In this embodiment, when the processor including multiplexing and inner code encoding are the same as those in the solution of embodiment 17, the concatenated code in the scheme is under AWGN and the performance is equivalent to that of the solution of embodiment 17, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

In this embodiment, when the processor including multiplexing and inner code encoding are the same as those in the solution of embodiment 18, the concatenated code in the scheme is under AWGN and the performance is equivalent to that of the solution of embodiment 18, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

In this embodiment, when the processor including multiplexing and inner code encoding are the same as those in the solution of embodiment 19, the concatenated code in the scheme is under AWGN and the performance is equivalent to that of the solution of embodiment 19, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

In this embodiment, when the processor including multiplexing and inner code encoding are the same as those in the solution of embodiment 20, the concatenated code in the scheme is under AWGN and the performance is equivalent to that of the solution of embodiment 20, but the solution of this embodiment is poor at tolerating system burst errors. This solution is applicable to some scenarios that require lower latency.

Please note that in some possible implementations, the multiplexing described in the previous embodiments may also be replaced by block interleaving for implementation purposes. Below, a description is provided with reference to specific embodiments.

Figure 32(a) is a schematic diagram of a structure in which block interleaving is performed on n first data streams according to an embodiment of the present application. As shown in Figure 32(a), block interleaving may be performed via m parallel block interleaving modules. Specifically, each block interleaver generates one second data stream after performing block interleaving on K input first data streams, resulting in a total of m second data streams. The manner of selecting the K first data streams to be input to each block interleaver is consistent with the manner of selecting the K input multiplexed data streams to be input to the multiplexer in the previous embodiment, and details will not be described again herein.

Figure 32(b) is a schematic diagram of the structure of a block interleaver according to an embodiment of the present application. As shown in Figure 32(b), consecutive ΔRS symbols in a first data stream i _k are a symbol subset and are represented by S _k (.), where 0≦k≦K−1. Therefore, S _k (0), S _k (1), ..., S _k (W) represent W consecutive symbol subsets output from the first data stream i _k . Consecutive ΔRS symbols in a second data stream are a symbol subset and are represented by S(.). W symbol subsets are obtained from each of the K input first data streams to form a first symbol matrix having K rows and W columns. Each element of the first symbol matrix is a symbol subset, and S _k (w) corresponds to an element in k rows and w columns of the first symbol matrix, where 0≦k≦K−1 and 0≦w≦W−1. The second symbol matrix with 1 row and C columns is obtained by performing block interleaving on the first symbol matrix with K rows and W columns, where C = K*W. Each element of the second symbol matrix is also a symbol subset, where S(c) represents the element of column c of the second symbol matrix, where 0≦c≦C. The mapping between block interleaving S(c) and _Sk (w) can be expressed as: c = K*w+k. The second symbol matrices S(0), S(0),..., S(K*W-1) obtained by block interleaving correspond sequentially to the information bits of the Q inner codes, and the Q inner codes are obtained by inner code encoding. If the length of the inner code is D symbols, then K*W*Δ = Q*D.

Please note that the concept of symbol subsets is merely introduced for ease of explanation. In actual applications, both the first data stream and the second data stream are whole and not divided. Each symbol subset may be considered as one or more symbols in the first data stream or the second data stream. In addition, in actual applications, the first symbol matrix and the second symbol matrix may not necessarily be presented in matrix form. For example, the first symbol matrix may be presented as a first symbol set, which includes K*W symbol subsets corresponding to K rows and W columns of elements in the first symbol matrix, respectively. The second symbol matrix may be presented as a second symbol set, which includes C symbol subsets corresponding to 1 row and C columns of elements in the second symbol matrix, respectively.

In the example, based on the convolutional interleaver provided in embodiment 1, a specific implementation corresponding to block interleaving is as follows: G = 2, K = 2, and m = 16. The input first data stream _i0 and the input first data stream _i1 of block interleaver i correspond to first data stream i and first data stream (i + 16), respectively. The structure of the block interleaver shown in Figure 32(b) is used as an example, and the parameters of the block interleaver may be Δ = 6, W = 1, Q = 1, or Δ = 3, W = 2, Q = 1. The second symbol matrix is mapped to one piece of information data of an inner code with an information bit length of 120 bits, and the inner code encoding method of embodiment 1 can be used to achieve equivalent performance.

In another example, based on the convolutional interleaver provided in embodiment 1, another specific implementation corresponding to block interleaving is as follows: G = 2, K = 4, and m = 16. The first data stream i0 input to the first data stream _i3 of block interleaver i corresponds to first data stream _i , first data stream (i+16), first data stream (i+8), and first data stream (i+24), respectively. The structure of the block interleaver shown in Figure 32(b) is used as an example, and the parameters of the block interleaver may be Δ = 6, W = 1, and Q = 2. The second symbol matrix is mapped to two pieces of information data of an inner code with an information length of 120 bits, and the inner code encoding scheme of embodiment 1 can be used to achieve equivalent performance.

In yet another example, based on the convolutional interleaver provided in embodiment 1, another specific implementation corresponding to block interleaving is as follows: G = 2, K = 8, and m = 16. The first data stream i0 input to the first data stream _i7 of block interleaver i corresponds to first data stream _i , first data stream (i+16), first data stream (i+8), first data stream (i+24), first data stream (i+4), first data stream (i+20), first data stream (i+12), and first data stream (i+28), respectively. The structure of the block interleaver shown in Figure 32(b) is used as an example, and the parameters of the block interleaver may be Δ = 6, W = 1, and Q = 4. The second symbol matrix is mapped to four pieces of information data of an inner code having an information bit length of 120 bits, and the inner code encoding method of embodiment 1 can be used to achieve equivalent performance.

It should be understood that in other embodiments, the implementation of the corresponding block interleaving may alternatively be estimated based on convolutional interleaving and inner code encoding schemes, and will not be listed one by one in this specification.

The above describes the data processing method provided in the embodiment of this application. Below, we describe the data processing device provided in the embodiment of this application.

33 is a schematic diagram of the structure of a data processing apparatus according to an embodiment of the present application. As shown in FIG. 33, the data processing apparatus includes a convolutional interleaver 101 and a multiplexer 102. The convolutional interleaver 101 is configured to perform the operation of separately performing convolutional interleaving on n lane data streams to obtain n first data streams in the aforementioned data processing method. The multiplexer 102 is configured to perform the operation of multiplexing every K first data streams among the n first data streams to obtain one second data stream in total to obtain m second data streams in the aforementioned data processing method. For details, please refer to the related descriptions of the convolutional interleaving operation and multiplexing operation in the aforementioned data processing method. The details will not be described again in this specification.

It should be understood that the devices provided in this application may alternatively be implemented in other ways. For example, the unit divisions of the devices described above are merely logical functional divisions, and other divisions may be used in actual implementations. For example, multiple units or components may be combined or integrated into another system. In addition, functional units in the embodiments of this application may be integrated into a single processing unit, or may be separate physical units, or two or more functional units may be integrated into a single processing unit. Integrated units may be implemented in the form of hardware or software functional units.

Please note that in addition to the data processing method described in the above embodiment, the present application also provides another data processing method, which will be described in detail below.

In this embodiment, n lane data streams are first interleaved to obtain m target data streams. Then, a second FEC encoding is performed separately on the m target data streams to obtain encoded data streams. The manner in which the second FEC encoding is performed separately on the m target data streams is similar to the manner described in step 1003 of the embodiment shown in FIG. 10, and the details will not be described again herein.

In this embodiment, the lane data stream may be a PCS lane data stream or an FEC lane data stream. This is not specifically limited herein. All n lane data streams are data streams obtained by the first FEC encoding, i.e., the aforementioned outer code-encoded data streams, where n is an integer greater than 1 and a multiple of 4. For example, an RS code may be used in the outer code encoding, and the n outer code-encoded data streams may include multiple RS codewords. In actual applications, other encoding methods may be used to perform the outer code encoding. For ease of explanation, hereinafter, an RS codeword is used to represent a codeword generated by the outer code encoding. It should be understood that every a codeword obtained by the outer code encoding is distributed among b lane data streams, where a≦b≦n, n may be exactly divisible by b, and a is an integer greater than or equal to 1. In different application scenarios shown in FIGS. 5 to 9, the values of a and b may also be different. The application scenario shown in Figure 5 is used as an example, with n = 32, a = 2, and b = 16; in other words, every second codeword is distributed across 16 lane data streams. The values of a and b in the application scenarios of Figures 6 to 9 can be estimated with reference to the accompanying drawings and will not be described in detail again herein. Therefore, the maximum value of b is 16, and the minimum value of b is 4. Note that in this application, the code length of the outer code is measured in symbols, and a symbol may contain one or more bits. For example, the outer code used is the KP4 RS (544, 514) code, with a code length of N = 544 symbols and one symbol containing 10 bits.

It should be understood that the F consecutive symbols in each target data stream are from F different code words, where F>a. The F consecutive symbols in each target data stream are from at least K1 different lane data streams, and the F consecutive symbols in each target data stream are from up to K2 symbols in the n aligned symbols of the n lane data streams, where K1 and K2 are submultiples of n, and K2 is a submultiple of K1. The n aligned symbols of the n lane data streams refer to n symbols at the same position in all lane data streams. Different application scenarios shown in Figures 5 to 9 are used as examples, in which the n symbols in each column of the n lane data streams are aligned. In other words, the n aligned symbols of the n lane data streams may be n symbols in one column of the n lane data streams. Up to K3 symbols in the F consecutive symbols in each target data stream are from the same lane data stream.
It should be further understood that represents an integer obtained by rounding up the quotient of F/K1, any two of the K3 symbols are separated by at least K4 symbols on the same lane data stream, and K4≧a*N*K2/n, where N is the length of the codeword. In this embodiment, the maximum value of b is 16 and the minimum value of b is 4. Thus, in some possible implementations, K1=n/4 and K2=n/16.

In some possible implementations, lane reordering may further be performed on the n lane data streams so that the n data streams are arranged in a preset sequence before being interleaved to obtain the m target data streams. 32 data streams are used as an example. The 32 data streams may be sorted from 0 to 31 from top to bottom. Of course, this example may simply be extended to sorting in another sequence, the specific implementation of which is known to those skilled in the art and will not be described in detail herein.

In some possible implementations, lane data alignment may be further performed on the n lane data streams before the n lane data streams are interleaved to obtain the m target data streams. The lane data alignment may be lane de-skew defined in existing standards, ensuring that the data of the n lane data streams output through lane data alignment are perfectly aligned. Alternatively, the above-mentioned "lane data alignment" may simply be lane symbol alignment, ensuring that the data of the n lane data streams output through lane data alignment are aligned based on the outer code symbol. Specifically, the data may be aligned based on one outer code symbol or multiple outer code symbols. For a detailed description of lane data alignment, please refer to the related description of Figure 3(e). This will not be described in detail herein.

Please note that the interleaving in this embodiment can have multiple specific implementations, which are described separately below.

Figure 34 is a schematic flowchart of interleaving according to an embodiment of the present application.

3401: Perform convolutional interleaving on the n lane data streams separately to obtain n first data streams.

In this embodiment, z consecutive symbols in each first data stream obtained by convolutional interleaving are from at least e different code words, where z is an integer greater than 1, a≦e≦F, and e*k2≧F. Up to k1/k2 symbols in the z consecutive symbols in each first data stream are from the same code word.

Note that the implementation of convolutional interleaving in this embodiment is similar to the convolutional interleaving style described in the embodiment shown in FIG. 10, and details will not be described again herein. In a possible implementation, when the convolutional interleaver shown in FIG. 12(a) is used, the parameters of the convolutional interleaver satisfy d(p*Q+1)≧K4, so that z=p*d consecutive symbols in the first data stream output by the convolutional interleaver are from codewords of at least e different outer codes, where N is the codeword length of the outer code encoding. In another possible implementation, when the convolutional interleaver shown in FIG. 12(b) is used, the parameters of the convolutional interleaver satisfy d(p*Q-1)≧K4, so that z=p*d consecutive symbols in the first data stream output by the convolutional interleaver are from codewords of at least e different outer codes, where N is the codeword length of the outer code encoding.

3402: Obtain S target data streams by performing block interleaving on every K1 first data streams of the n first data streams, so as to obtain m target data streams in total.

Figure 35 is a schematic diagram of a structure in which block interleaving is performed on n first data streams according to an embodiment of the present application. As shown in Figure 35, T block interleavers may be used to perform block interleaving. Specifically, every K1 first data streams of the n first data streams are input to one block interleaver, which outputs S target data streams. The T block interleavers output a total of m target data streams, where m = S * T, T = n/K1, and S ≥ k1/k2. Note that the n first data streams include K1 first data stream groups, one first data stream from each first data stream group is selected to form the K1 first data streams involved in block interleaving, and the symbols of any two first data streams in the same first data stream group are from the same codeword.

It should be understood that the first data stream group is a concept introduced simply for ease of explanation. In actual applications, the n first data streams are whole without division, and each first data stream group can be considered as one or more data streams within the n first data streams.

Specific implementations of block interleaving are described below.

FIG. 36 is a schematic diagram of an implementation of block interleaving according to an embodiment of the present application. As shown in FIG. 36, one implementation of a block interleaver is used as an example for illustration. Each of the K first data streams involved in block interleaving includes B symbols. In other words, the K first data streams include a first symbol matrix, which includes K rows and B columns of symbols. B = R*p*d, where R is an integer greater than or equal to 1, and the B symbols in each row of the first symbol matrix are B consecutive symbols output from p delay lines of a convolutional interleaver in which R polling is performed. Each of the S target data streams obtained by block interleaving includes F symbols. In other words, the S target data streams include a second symbol matrix, which includes S rows and F columns of symbols. K*B = S*F, where F is the length of the inner code information data. It should be understood that the symbols in the first symbol matrix are from at least F different codewords, and up to R*K1/K2 symbols in the first symbol matrix are from the same codeword, and F symbols from different codewords are selected from the first symbol matrix and mapped to one row of the second symbol matrix. That is, F consecutive symbols in each target data stream are from F different codewords.

In a possible embodiment, the F symbols in each row of the second symbol matrix are at least
column, and each
At most K2 symbols are selected in the column,
represents the integer obtained by rounding up the quotient of F/K2. The F symbols in each row of the second symbol matrix are at least equal to the F symbols in each row of the first symbol matrix.
symbols,
represents the integer obtained by truncating the quotient of F/K1, and F symbols in each row of the second symbol matrix are at most F in each row of the first symbol matrix.
symbols,
represents the integer obtained by rounding up the quotient of F/K1.

In another possible implementation, in each row of the second symbol matrix, symbols from odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix, and in each row of the second symbol matrix, symbols from even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix.

In yet another possible implementation, the symbols in each row of the second symbol matrix output from delay lines having the same delay value are from different rows of the first symbol matrix. Up to K3 symbols in each row of the second symbol matrix are from the same row of the first symbol matrix, and any two of the K3 symbols are output from two delay lines whose delay difference is greater than or equal to 2*Q*d.

Note that in practical applications, the first symbol matrix and the second symbol matrix may not alternatively be presented in matrix form. For example, the first symbol matrix may be presented as a first symbol set, which includes K*B symbol subsets corresponding to the K rows and B columns of symbols in the first symbol matrix. The second symbol matrix may be presented as a second symbol set, which includes S*F symbol subsets corresponding to the S rows and F columns of symbols in the second symbol matrix.

In the present invention, a data interleaving and encoding method, including convolutional interleaving, block interleaving, and encoding, is designed for the concatenated FEC transmission solution, so that the same interleaving solution can be used for all access services, and the entire concatenated FEC solution has good performance and low latency. Therefore, the concatenated FEC transmission solution can be applied to multiple transmission scenarios, and is particularly applicable to transmission scenarios that require low transmission latency, such as low-latency data center interconnection scenarios.

The steps of the interleaving method shown in FIG. 34 will be further described below with reference to several specific embodiments. It should be understood that the inner code parallelism in each of the following embodiments is the number of target data streams. For example, an inner code parallelism of 16 indicates that the number of target data streams is 16. It should also be understood that a target symbol subset in the following embodiments represents F consecutive symbols in the target data stream.

Embodiment 1: Uniform interleaving is used for all services, the information bit length of the inner code encoding is 120 bits, and the inner code parallelism is 16.

This embodiment is service-independent and provides a specific data interleaving and encoding scheme for OIF LR scenarios. Based on the type of access service, the transmitting-side processing module performs alignment marker lock on lane data streams based on the known alignment markers of the PCS or FEC lanes of each service. The known alignment markers of the 32 lanes are different and associated with the access service. The transmitting-side processing module then performs deskew on multiple PCS or FEC lanes in each service. After deskew, all multiple PCS/FEC lanes within the same service are AM aligned, and lane data streams between services only need to meet RS symbol alignment, i.e., the difference between AMs is an integer number of RS symbols.

Figure 37 is a schematic diagram of a lane-aligned data stream format for a 2x400GbE host interface. For example, if the access service is a 2x400GbE service, 32 deskewed lane data streams are shown in Figure 37. AM alignment is performed between the 16 PCS lanes of each 400GbE service, and the difference between the AMs of the two services is an integer number of RS symbols. Then, based on the alignment marker, lane reordering is performed on the data in the n=32 lanes, so that the data in the n=32 lanes can be arranged in a specified sequence. For example, if the access service is a 1x800GbE service, 32 lane data streams are shown in Figure 5. If the access service is a 2x400GbE service, 32 lane data streams are shown in Figure 6. If the access service is a 4x200GbE service, 32 lane data streams are shown in Figure 7. When the access service is an 8*100GbE service and is in "100G RS-FEC-Int" mode, a 32-lane data stream is shown in Figure 8. When the access service is an 8*100GbE service and is in "100G RS-FEC" mode, a 32-lane data stream is shown in Figure 9.

The n = 32 lane data streams on which lane permutation is performed are sent to a convolutional interleaving module and a block interleaving module for corresponding processing, and then sent to an inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc.

In this embodiment, convolutional interleaving is performed separately on the n = 32 PCS lane data streams to obtain n = 32 first data streams. Convolutional Interleave 0, Convolutional Interleave 1, Convolutional Interleave 2, ..., Convolutional Interleave 31 use the same interleaving structure. Figure 16(a) shows the configuration of a convolutional interleaver including p = 3 delay lines. The p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbol, i.e., no delay.

As shown in FIG. 16(a), C _r (.) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (6t) and C _r (6t+1) represent two RS symbols in the lane data stream currently input to delay line 0, and C _r (6t-12Q) and C _r (6t-12Q+1) are the two RS symbols output from delay line 0; C _r (6t+2) and C _r (6t+3) represent two RS symbols in the lane data stream that will later input to delay line 1, and C _r (6t-6Q+2) and C _r (6t-6Q+3) are the two RS symbols output from delay line 1; C _r (6t+4) and C _r (6t+5) represent two RS symbols in the lane data stream that will subsequently input to delay line 2, and C _r (6t+4) and C _r (6t+5) are the two RS symbols output from delay line 2; C _r (6t+6) and C _r (6t+7) represent the two RS symbols in the lane data stream that are subsequently input to delay line 0, and C _r (6t−12Q+6) and C _r (6t−12Q+7) are the two RS symbols output from delay line 0; and so on. If the access service is a 1*800GbE service or a 2*400GbE service,
is satisfied, i.e., 6Q+2≧2*544/16, i.e., Q≧11, and a total of six RS symbols _Cr (6t-12Q), _Cr (6t-12Q+1), _Cr (6t-6Q+2), _Cr (6t-6Q+3), _Cr (6t+4), and _Cr (6t+5) output by convolutional interleaving are from six different RS codewords. Then, the data of the two first data stream subsets are aggregated by using block interleaving, so that 12 consecutive RS symbols in the target data stream can be from 12 different RS codewords. Similarly, for another access service, with subsequent block interleaving, when Q≧11, 12 consecutive RS symbols in the target data stream can be from 12 different RS codewords.

In a possible implementation, Q = 11 is selected, and the specific structure of the convolutional interleaver is shown in Figure 16(b). The interleave latency corresponding to the convolutional interleaver is approximately 22 * 2 * 3 / 2 = 66 RS symbols.

The convolutional interleaver shown in Figure 16(b) performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS/FEC lane data streams shown in Figures 5 to 9. It is not difficult to see that the first data streams include at most G _max = 8 first data stream subsets and at least G _min = 2 first data stream subsets. In order to use the same interleaving solution for all services and reduce the convolutional interleaving delay, the first data streams are divided into K1 = G _max = 8 first data stream groups, where any two data streams in each first data stream group are from the same RS codeword, and the corresponding groups are specifically divided as follows: first data streams 0 to 3 are first data stream group 0, first data streams 4 to 7 are first data stream group 1, first data streams 8 to 11 are first data stream group 2, first data streams 12 to 15 are first data stream group 3, first data streams 16 to 19 are first data stream group 4, first data streams 20 to 23 are first data stream group 5, first data streams 24 to 27 are first data stream group 6, and first data streams 28 to 31 are first data stream group 7. Therefore, in this embodiment, the block interleave shown in Figure 35 is used, and the corresponding parameters are K = K1 = 8 and T = 32/K1 = 4, and eight first data streams , which are arbitrary first data streams selected from each first data stream group, are used as the eight input data streams of block interleave i (0 < i < 4).

Figure 38 is a schematic diagram of an embodiment of block interleaving. As shown in Figure 38, the eight input data streams of block interleave i (0≦i<4) are first data stream i, first data stream (i+4), first data stream (i+8), first data stream (i+12), first data stream (i+16), first data stream (i+20), first data stream (i+24), and first data stream (i+28), respectively. B = 6 consecutive RS symbols are obtained from each input data stream to form a first symbol matrix with 8 rows and 6 columns, and the 6 RS symbols in each row are the 6 RS symbols output from delay line 0, delay line 1, and delay line 2, respectively, of the convolutional interleaver shown in Figure 16(b) in which R = 1 polling is performed. See Figures 5 to 9. It is not difficult to learn that the first symbol matrix is from at least 12 different RS codewords, and at most four RS symbols belong to the same RS codeword. Furthermore, in the first symbol matrix, rows 0 through 3 are from at least six different RS codewords, and rows 4 through 7 are from at least six different RS codewords, with no two from the same RS codeword. Furthermore, the RS codeword distribution in all odd-numbered columns or all even-numbered columns of the first symbol matrix may be consistent. Furthermore, in the first symbol matrix, the distribution of RS codewords in columns 0 through 3 may be consistent, and the distribution of RS codewords in columns 2 through 5 may be consistent. Thus, two RS symbols may be selected from each column of the first symbol matrix, with one RS symbol from any row from rows 0 through 3 and the other RS symbol from any row from rows 4 through 7. A total of 12 RS symbols are mapped to one row of the second symbol matrix to obtain a second symbol matrix with 4 rows and 12 columns. The 12 RS symbols in the tth (0≦t<4) row of the second symbol matrix are 12 consecutive RS symbols in the target data stream (i*4+t) output through block interleave i. Therefore, one row of the second symbol matrix is defined as a target symbol subset. For ease of explanation, S(i _x , j _y ), i _x ∈ [0, 7], j _y ∈ [0, 5] is defined as the symbol representing the i _xth row and j _yth column of the first symbol matrix. To allow the 12 RS symbols in the target symbol subset to be from 12 different RS codewords, the six RS symbols selected from rows 0 to 3 of the first symbol matrix or the six RS symbols selected from rows 4 to 7 of the first symbol matrix correspond to S( _i0,0 ), S(i1,1), S( _i2,2 ), S( _i3,3 ), S( _i4,4 ), and S( _i5,5 ) of the first symbol matrix, where _i0 , _i1 , _i2 , and i3 are unequal, _i2 , _i3 , _i4 , and _i5 are unequal, _i0 , _i2 , _{and i4} are unequal, _i1 , _i3 , and _i5 are unequal, and _i0 , _i1 , _i2 , _i3 , _i4 , and _i5 are unequal _. ∈[0, 3] or _i0 , _i1 , _i2 , _i3 , _i4 , and _i5 ∈ [4, 7], which is equivalent to the case where all two symbols in the target symbol subset are from the same column of the first symbol matrix, with one symbol located in any row from 0 to 3 of the first symbol matrix and the other symbol located in any row from 4 to 7 of the first symbol matrix. Furthermore, within the target symbol subset, six symbols from odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix, and six symbols from even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix. Furthermore, in the target symbol subset, at least one symbol is from the same row of the first symbol matrix, and at most two symbols are from the same row of the first symbol matrix, and two symbols from the same row are output from two different delay lines due to convolutional interleaving, and the delay difference corresponding to the two delay lines is greater than or equal to 2*d*Q=44 symbols. According to this rule, there are many specific mappings from the first symbol matrix to the second symbol matrix. Tables 1 to 4 provide some specific mapping relationships. The number x in the yth row and zth column of each table indicates that the RS symbol in the yth row and zth column of the second symbol matrix is from the xth RS symbol of the first symbol matrix, where 0≦y<4, 0≦z<12, and 0≦x<48. The xth RS symbol of the first symbol matrix is from the (x%8)th row and (
) denotes the column symbol. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, switching between any columns after switching between any rows, or switching between any columns before switching between any rows in Tables 1 to 4 is performed. x%8 denotes the remainder obtained when x is divided by 8,
It should be understood that represents the quotient obtained when x is divided by 8. In the following embodiments, the same representation manner will not be described again.

Based on the relationship between the first symbol matrix and the first data stream, and the relationship between the first data stream and the lane data stream, it is not difficult to learn that the 12 symbols of each target symbol subset are from K1=8 lane data streams, and the 8 lane data streams can be represented as lane data stream j ₀ , lane data stream j ₁ , lane data stream j ₂ , lane data stream j ₃ , lane data stream j ₄ , lane data stream j ₅ , lane data stream j ₆ and lane data stream j ₇ ,
, x∈[0, 7], and
represents j _x /4 rounded down to the nearest integer. Furthermore, one symbol is obtained from each of the four lane data streams, and two RS symbols are obtained from each of the remaining four lane data streams. Furthermore, when two RS symbols are obtained from a lane data stream, the spacing between two RS symbols in the corresponding lane data stream is greater than or equal to a*N*K2/n, or in other words, greater than or equal to 2*544*2/32 = 68 RS symbols. Furthermore, the maximum two RS symbols are from two aligned symbols in two different lane data streams.

Block interleaving generates 16 target data streams, and inner code encoding is performed on each target symbol subset within the 16 target data streams, with the information bit length of the inner code encoding being 120 bits. Specifically, to obtain 16 encoded data streams, an inner code encoder separately encodes a total of 120 bits of each target symbol subset within the target data stream and adds redundancy. In one possible implementation, inner code encoding is performed using Hamming (128, 120) to obtain a 128-bit codeword, with 8 bits of redundancy added to the total 120 bits within 12 consecutive RS symbols within each target data stream. In another possible implementation, inner code encoding is performed using BCH (136, 120), with 16 bits of redundancy added to the total 120 bits within 12 consecutive RS symbols within each target data stream to obtain a 136-bit codeword.

After data processing is performed on the inner-code encoded data stream, the processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, the inner-code encoded data stream may be interleaved to improve the system's ability to tolerate burst errors.

By using the data interleaving and encoding scheme of this embodiment, the concatenated KP4 RS (544, 514) + Hamming (128, 120) code in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3, which is close to the optimal performance of the concatenated FEC scheme.

Embodiment 2: Uniform interleaving is used for all services, the information bit length of the inner code encoding is 120 bits, and the inner code parallelism is 32.

The convolutional interleaver shown in Figure 16(b) performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS/FEC lane data streams shown in Figures 5 to 9. It is not difficult to see that the first data streams include at most G _max = 8 first data stream subsets and at least G _min = 2 first data stream subsets. In order to use the same interleaving solution for all services and reduce the convolutional interleaving delay, the first data streams are divided into K1 = G _max = 8 first data stream groups, where any two data streams in each first data stream group are from the same RS codeword, and the corresponding groups are specifically divided as follows: first data streams 0 to 3 are first data stream group 0, first data streams 4 to 7 are first data stream group 1, first data streams 8 to 11 are first data stream group 2, first data streams 12 to 15 are first data stream group 3, first data streams 16 to 19 are first data stream group 4, first data streams 20 to 23 are first data stream group 5, first data streams 24 to 27 are first data stream group 6, and first data streams 28 to 31 are first data stream group 7. Therefore, in this embodiment, the block interleave shown in Figure 35 is used, and the corresponding parameters are K = K1 = 8 and T = 32/K1 = 4, and eight first data streams , which are arbitrary first data streams selected from each first data stream group, are used as the eight input data streams of block interleave i (0 < i < 4).

Figure 39 is a schematic diagram of another embodiment of block interleaving. As shown in Figure 39, the eight input data streams of block interleave i (0≦i<4) are first data stream i, first data stream (i+4), first data stream (i+8), first data stream (i+12), first data stream (i+16), first data stream (i+20), first data stream (i+24), and first data stream (i+28), respectively. Twelve consecutive RS symbols are obtained from each input data stream to form a first symbol matrix with 8 rows and 12 columns, and the 12 RS symbols in each row are the 12 RS symbols consecutively output from delay line 0, delay line 1, and delay line 2, respectively, of the convolutional interleaver shown in Figure 16(b) in which R = 2 polling is performed. 5 to 9, it is not difficult to learn that the first symbol matrix is from at least 12 different RS codewords, and a maximum of R*K1/K2=8 RS symbols belong to the same RS codeword. Furthermore, in the first symbol matrix, rows 0 to 3 are from at least six different RS codewords, and rows 4 to 7 are from at least six different RS codewords, with no two being from the same RS codeword. Furthermore, the RS codeword distributions in all odd-numbered columns or all even-numbered columns of the first symbol matrix may be consistent. Furthermore, in the first symbol matrix, all RS codeword distributions in columns 0 to 3 may be consistent, all RS codeword distributions in columns 2 to 5 may be consistent, all RS codeword distributions in columns 6 to 9 may be consistent, and all RS codeword distributions in columns 8 to 11 may be consistent. Furthermore, the RS codeword distribution in the jth, (j+1), (j+6), and (j+7) columns (j∈{0, 2, 4}) of the first symbol matrix may be consistent. Therefore, to obtain a second symbol matrix with 8 rows and 12 columns, a total of 12 RS symbols, one symbol from each column of the first symbol matrix, may be selected and mapped to one row of the second symbol matrix. The 12 RS symbols in the tth (0≦t<8)th row of the second symbol matrix are 12 consecutive RS symbols in the target data stream (i*8+t) output through block interleaving i. Therefore, one row of the second symbol matrix is defined as the target symbol subset. For ease of explanation, S( _ix , _jy ), _ix∈ [0, 7], _jy∈ [0, 11], are defined as the symbol representing the _ith row and _jyth column of the first symbol matrix. To allow the 12 RS symbols in the target symbol subset to be from 12 different RS codewords, the 12 RS symbols correspond to S( _i0,0 ), S( _i1,1 ), S(i2,2), ..., S( _i10,10 ), and S _{(i11,11 )} in the first symbol matrix. _i0 , _i1 , _i2 , and _i3 are unequal to one another, _i2 , _i3 , _i4 , and _i5 are unequal to one another, _i6 , _i7 , _i8 , and _i9 are unequal to one another, _i8 , _i9 , _i10 , and _i11 are unequal to one another, _i0 , _i1 , _i6 , and _i7 are unequal to one another, _i2 , _i3 , _i8 , and _i9 are unequal to one another, _i4 , _i5 , _i11 , and _i12 are unequal to one another, _i0 , _i2 , _i4 , _i6 , _i8 , and _i10 are unequal to one another, and _i1 , _i3 , _i5 , _i7 , _i9 , i The symbols _i0 , i1, _i2 , _i3 , _i4 , i5, _i6 , _i7 , _i8 , _i9 , _i10 , and _i11 are unequal to each other, with i0, i1, i2, _i3 , _{i4, i5} , i6, i7, i8, i9, i10, and _i11 ∈ [0, 7]. This is equivalent to each symbol in the target symbol subset being from the same column in the first symbol matrix. Furthermore, six symbols in the target symbol subset from odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix, and six symbols in the target symbol subset from even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix. Furthermore, symbols in the target symbol subset from the first symbol matrix output from delay lines with the same delay value are located in different rows of the first symbol matrix. Furthermore, in the target symbol subset, at least one symbol is from the same row of the first symbol matrix, and at most two symbols are from the same row of the first symbol matrix, and two symbols from the same row are output from two different delay lines due to convolutional interleaving, and the delay difference corresponding to the two delay lines is greater than or equal to 2*d*Q=44 symbols. According to this rule, there are many specific mappings from the first symbol matrix to the second symbol matrix. The following Tables 5 to 8 provide some specific mapping relationships. The number x in the yth row and zth column of each table indicates that the RS symbol in the yth row and zth column of the second symbol matrix is from the xth RS symbol of the first symbol matrix, where 0≦y<8, 0≦z<12, and 0≦x<96; and the xth RS symbol of the first symbol matrix is from the (x%8)th row and (
) denotes the column symbol. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, switching between any columns after switching between any rows, or switching between any columns before switching between any rows is performed.

According to the RS codeword distribution rule of the first symbol matrix, another mapping manner from the first symbol matrix to the target symbol subset is as follows: a total of six columns are selected, which are arbitrary columns from the (2*j)th column and the (2*j+1)th column (j∈[0,5]) of the first symbol matrix, and then two RS symbols from each of the selected six columns , which are a total of 12 RS symbols , are selected to be mapped to the target symbol subset. The correspondingly selected 12 RSs correspond to S(i0, j0), S( _i1 , _j0 ), S( _i2 , _j1 ), S( _i3 , _j1 ), S( _i4 , _j2 ), S( _i5 , _j2 ), S( _i6 , _j3 ), S( _i7 , _j3 ), S( _i8 , _j4 ), S( _i9 , _j4 ), S _{(i10 , j5} ), and S( _i11 , _j5 ) in the _first symbol matrix. _i0 , _i1 , _i2 , _i3 are unequal to each other, _i2 , _i3 , _i4 , _i5 are unequal to each other, _i6 , _i7 , _i8 , _i9 are unequal to each other, _i8 , _i9 , _i10 , _i11 are unequal to each other, _i0 , _i1 , _i6 , _i7 are unequal to each other, _i2 , _i3 , _i8 , _i9 are unequal to each other, and _i4 , _i5 , _i10 , _i11 are unequal to each other. _i0 , _i1 , _i2 , _i3 , _i4 , i5, _i6 , _i7 , _i8 , _i9 , _i10 , i11, _i12 , _i13 , _i14 , and _i15 ∈ [0, 7]. _j0 ∈ [0, 1], _j1 ∈ [2 _, 3], _j2 ∈ [4, 5], _j3 ∈ [ ₆ , 7], _j4 ∈ [8, 9], _j5 ∈ [10, 11], _j6 ∈ [12, 13], _j7 ∈ [14, 15]. This is equivalent to the case where every two symbols in the target symbol subset are from the same column of the first symbol matrix, with one symbol located in any row from 0 to 3 of the first symbol matrix and the other symbol located in any row from 4 to 7 of the first symbol matrix. Furthermore, six symbols from odd-numbered columns of the first symbol matrix in the target symbol subset are located in different rows of the first symbol matrix, and six symbols from even-numbered columns of the first symbol matrix in the target symbol subset are located in different rows of the first symbol matrix. Furthermore, symbols in the target symbol subset from the first symbol matrix output from delay lines with the same delay value are located in different rows of the first symbol matrix. Furthermore, in the target symbol subset, at most two symbols are from the same row of the first symbol matrix, and two symbols from the same row are output from two different delay lines for convolutional interleaving, and the delay difference corresponding to the two delay lines is greater than or equal to 2*d*Q=44 symbols. According to this rule, there are many specific mappings from the first symbol matrix to the second symbol matrix. Tables 9 to 12 provide some specific mapping relationships. The number x in the yth row and zth column of each table indicates that the RS symbol in the yth row and zth column of the second symbol matrix is from the xth RS symbol of the first symbol matrix, where 0≦y<8, 0≦z<12, and 0≦x<96; the xth RS symbol of the first symbol matrix is from the (x%8)th row and (
) denotes the column symbol. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, switching between any columns after switching between any rows, or switching between any columns before switching between any rows is performed.

Based on the relationship between the first symbol matrix and the first data stream, and the relationship between the first data stream and the lane data stream, it is not difficult to learn that the 12 symbols of each target symbol subset are from K1=8 lane data streams, and the 8 lane data streams can be represented as lane data stream j ₀ , lane data stream j ₁ , lane data stream j ₂ , lane data stream j ₃ , lane data stream j ₄ , lane data stream j ₅ , lane data stream j ₆ and lane data stream j ₇ ,
, x∈[0, 7], and
represents j _x /4 rounded down to the nearest integer. Furthermore, one symbol is obtained from each of the four lane data streams, and two RS symbols are obtained from each of the remaining four lane data streams. Furthermore, when two RS symbols are obtained from a lane data stream, the spacing between two RS symbols in the corresponding lane data stream is greater than or equal to a*N*K2/n, or in other words, greater than or equal to 2*544*2/32 = 68 RS symbols. Furthermore, the maximum two RS symbols are from two aligned RS symbols in two different lane data streams.

32 target data streams are generated by block interleaving, and inner code encoding is performed on each target symbol subset within the 32 target data streams, with the information bit length of the inner code encoding being 120 bits. Specifically, to obtain 32 encoded data streams, the inner code encoder separately encodes a total of 120 bits of each target symbol subset within the target data stream and adds redundancy. In one possible implementation, inner code encoding is performed using Hamming (128, 120) to obtain a 128-bit codeword, with 8 bits of redundancy added to the total 120 bits within 12 consecutive RS symbols within each target data stream. In another possible implementation, inner code encoding is performed using BCH (136, 120), with 16 bits of redundancy added to the total 120 bits within 12 consecutive RS symbols within each target data stream to obtain a 136-bit codeword.

After data processing is performed on the inner-code encoded data stream, the processed data stream is sent to a channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, the inner-code encoded data stream may be interleaved to improve the system's ability to tolerate burst errors.

By using the data interleaving and encoding scheme of this embodiment, the concatenated KP4 RS (544, 514) + Hamming (128, 120) code in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3, which is close to the optimal performance of the concatenated FEC scheme.

Embodiment 3: Uniform interleaving is used for all services, the information bit length of the inner code encoding is 160 bits, and the inner code parallelism is 16.

In this embodiment, the structure shown in Figure 11 is used for convolutional interleaving, which is performed separately on the n = 32 PCS lane data streams to obtain n = 32 first data streams. Convolutional Interleave 0, Convolutional Interleave 1, Convolutional Interleave 2, ..., Convolutional Interleave 31 use the same interleaving structure. Figure 18(a) shows the configuration of a convolutional interleaver including p = 4 delay lines. The four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, delay line 0 has a delay value of 6Q symbols, delay line 1 has a delay value of 4Q symbols, delay line 2 has a delay value of 2Q symbols, and delay line 3 has a delay value of 0 symbol, i.e., no delay.

As shown in FIG. 18(a), C _r ( ) represents one RS symbol in lane data stream r (0≦r≦n−1). For example, C _r (8t) and C _r (8t+1) represent the two RS symbols in the lane data stream currently input to delay line 0, C _r (8t-24Q) and C _r (8t-24Q+1) are the two RS symbols output from delay line 0; C _r (8t+2) and C _r (8t+3) represent the two RS symbols in the lane data stream subsequently input to delay line 1, C _r (8t-16Q+2) and C _r (8t-16Q+3) are the two RS symbols output from delay line 1; C _r (8t+4) and C _r (8t+5) represent the two RS symbols in the lane data stream subsequently input to delay line 2, C _r (8t-8Q+4) and C _r (8t-8Q+5) are the two RS symbols output from delay line 2; C _r (8t+6) and C _r (8t+7) represent the two RS symbols in the lane data stream that are subsequently input to delay line 3, C _r (8t+6) and C _r (8t+7) are the two RS symbols output from delay line 3; and so on. 5 and 6, when 8Q+2≧68, i.e., Q≧9, a total of eight RS symbols _Cr (8t−24Q), Cr(8t−24Q+1), _Cr (8t−16Q+2), _Cr (8t−16Q+3), _Cr (8t−8Q+4), _Cr (8t−8Q+5), _Cr (8t+6), and _Cr (8t+7) output through _{convolutional} interleaving are from eight different RS codewords. Then, the data of the two first data stream subsets are aggregated by using block interleaving, so that 16 consecutive RS symbols in the target data stream can be from 16 different RS codewords. Similarly, for a different access service, for subsequent block interleaving, when Q≧9, 16 consecutive RS symbols in the target data stream can be from 16 different RS codewords.

In a possible implementation, Q = 9 is selected, and the specific structure of the convolutional interleaver is shown in Figure 18(b). The interleaving latency corresponding to the convolutional interleaver is approximately 27 * 2 * 4 / 2 = 108 RS symbols.

The convolutional interleaver shown in Figure 18(b) performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS/FEC lane data streams shown in Figures 5 to 9. It is not difficult to see that the first data streams include at most G _max = 8 first data stream subsets and at least G _min = 2 first data stream subsets. In order to use the same interleaving solution for all services and reduce the convolutional interleaving delay, the first data streams are divided into K1 = G _max = 8 first data stream groups, where any two data streams in each first data stream group are from the same RS codeword, and the corresponding groups are specifically divided as follows: first data streams 0 to 3 are first data stream group 0, first data streams 4 to 7 are first data stream group 1, first data streams 8 to 11 are first data stream group 2, first data streams 12 to 15 are first data stream group 3, first data streams 16 to 19 are first data stream group 4, first data streams 20 to 23 are first data stream group 5, first data streams 24 to 27 are first data stream group 6, and first data streams 28 to 31 are first data stream group 7. Therefore, in this embodiment, the block interleave shown in Figure 35 is used, and the corresponding parameters are K = K1 = 8 and T = 32/K1 = 4, and eight first data streams , which are arbitrary first data streams selected from each first data stream group, are used as the eight input data streams of block interleave i (0 < i < 4).

Figure 40 is a schematic diagram of another embodiment of block interleaving. As shown in Figure 40, the eight input data streams of block interleave i (0≦i<4) are first data stream i, first data stream (i+4), first data stream (i+8), first data stream (i+12), first data stream (i+16), first data stream (i+20), first data stream (i+24), and first data stream (i+28), respectively. Eight consecutive RS symbols are obtained from each input data stream to form a first symbol matrix with 8 rows and 8 columns, where the eight RS symbols in each row are the eight RS symbols output from delay line 0, delay line 1, delay line 2, and delay line 3, respectively, of the convolutional interleaver shown in Figure 18(b), in which R=1 polling is performed. Referring to Figures 5 to 9, it is not difficult to learn that the first symbol matrix is from 16 different RS codewords, and all four RS symbols belong to the same codeword. Furthermore, in the first symbol matrix, rows 0 through 3 are from eight different RS codewords, and rows 4 through 7 are from eight different RS codewords, with no two from the same RS codeword. Furthermore, the RS codeword distribution in all odd-numbered columns or all even-numbered columns of the first symbol matrix may be consistent. Furthermore, in the first symbol matrix, the RS codeword distribution in columns 0 through 3 may be consistent, the RS codeword distribution in columns 2 through 5 may be consistent, or the RS codeword distribution in columns 4 through 7 may be consistent. Thus, two RS symbols may be selected from each column of the first symbol matrix. One RS symbol may be from any of rows 0 through 3, and the other RS symbol may be from any of rows 4 through 7. A total of 16 RS symbols are mapped to one row of the second symbol matrix to obtain a second symbol matrix with 4 rows and 16 columns. The 16 RS symbols in the tth (0≦t<4) row of the second symbol matrix are 16 consecutive RS symbols in the target data stream (i*4+t) output through block interleave i. Therefore, one row of the second symbol matrix is defined as a target symbol subset. For ease of explanation, S(i _x , j _y ), i _x ∈ [0, 7], j _y ∈ [0, 7] are defined as the symbol representing the i _xth row and j _yth column of the first symbol matrix. To allow the 16 RS symbols in the target symbol subset to be from 16 different RS codewords, the eight RS symbols selected in rows 0 through 3 of the first symbol matrix or the eight RS symbols selected in rows 4 through 7 of the first symbol matrix correspond to S( _i0,0 ), S(i1,1), S( _i2,2 ), S(i3,3), S(i4,4), S( _i5,5 ), S( _i6,6 ), _and S( _i7,7 ) of the first symbol matrix, where _i0 , _i1 , _i2 , and _i3 are unequal, i2, _i3 , _i4 , and _i5 are unequal, _i4 , _i5 , _{i6 ,} and _i7 are unequal _{, i0 , i2} , _i4 , _{and i6} are unequal, and _i1 , i _i0 , i1, _i2 , _i3 , i4, i5, i6, and _i7 are not equal, _{and i0} , _i1 , _i2 , i3, _i4 , _i5 , i6, and _i7 ∈ [0, 3], or _i0 , _i1 , _i2 , _i3 , _i4 , _i5 , _i6 , and _i7 ∈ [4, 7]. This is equivalent to the case where every two symbols in the target symbol subset are from the same column of the first symbol matrix, with one symbol located in any row from 0 to 3 of the first symbol matrix and the other symbol located in any row from 4 to 7 of the first symbol matrix. Furthermore, within the target symbol subset, eight symbols from odd-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix, and eight symbols from even-numbered columns of the first symbol matrix are located in different rows of the first symbol matrix. Furthermore, in the target symbol subset, every two symbols are from the same row of the first symbol matrix, and two symbols from the same row are output from two different delay lines due to convolutional interleaving, and the delay difference corresponding to the two delay lines is greater than or equal to 2*d*Q=44 symbols. According to this rule, there are many specific mappings from the first symbol matrix to the second symbol matrix. Tables 13 to 16 below provide some specific mapping relationships. The number x in the yth row and zth column of each table indicates that the RS symbol in the yth row and zth column of the second symbol matrix is from the xth RS symbol in the first symbol matrix, where 0≦y<4, 0≦z<16, and 0≦x<64. The xth RS symbol in the first symbol matrix is from the (x%8)th row and (
) denotes column symbols. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, switching between any columns after switching between any rows, or switching between any columns before switching between any rows in the table is performed.

Based on the relationship between the first symbol matrix and the first data stream, and the relationship between the first data stream and the lane data stream, it is not difficult to learn that the 16 symbols of each target symbol subset are from K1=8 lane data streams, and the 8 lane data streams can be represented as lane data stream _j0 , lane data stream _j1 , lane data stream _j2 , lane data stream _j3 , lane data stream _j4 , lane data stream _j5 , lane data stream _j6 and lane data stream _j7 ,
, x∈[0, 7], and
represents j _x /4 rounded down to the nearest integer. Furthermore, if two symbols are obtained from each lane data stream, the spacing between two RS symbols in the corresponding lane data stream is greater than or equal to a*N*K2/n, or in other words, greater than or equal to 2*544*2/32 = 68 RS symbols. Furthermore, the maximum two RS symbols are from two aligned RS symbols in two different lane data streams.

Sixteen target data streams are generated by block interleaving, and inner code encoding is performed on each target symbol subset within the 16 target data streams, with the information bit length of the inner code encoding being 160 bits. Specifically, to obtain 16 encoded data streams, an inner code encoder separately encodes a total of 160 bits of each target symbol subset within the target data stream and adds redundancy. In one possible embodiment, inner code encoding is performed using Hamming (170, 160) to obtain a 170-bit codeword, adding 10 bits of redundancy to the total 160 bits within 16 consecutive RS symbols within each target data stream. In another possible embodiment, inner code encoding is performed using BCH (176, 160), adding 16 bits of redundancy to the total 160 bits within 16 consecutive RS symbols within each target data stream to obtain a 176-bit codeword. After data processing is performed on the inner-code encoded data streams, the processed data streams are transmitted to a channel transmission medium for transmission.

After data processing is performed on the inner-code encoded data stream, the processed data stream is sent to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, the inner-code encoded data stream may be interleaved to improve the system's ability to tolerate burst errors.

By using the data interleaving and encoding scheme in this embodiment, when Hamming (170, 160) is used as the inner code, the concatenated code of KP4 RS (544, 514) + Hamming (170, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.3E-3, which is close to the optimal performance of the concatenated FEC scheme. When the inner code uses BCH (176, 160), the concatenated code of KP4 RS (544, 514) + BCH (176, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 8.3E-3, which is close to the optimal performance of the concatenated FEC scheme.

Embodiment 4: Uniform interleaving is used for all services, the information bit length of the inner code encoding is 160 bits, and the inner code parallelism is 32.

The convolutional interleaver shown in Figure 18(b) performs convolutional interleaving on the 32 PCS lane data streams separately to obtain 32 first data streams. See the PCS/FEC lane data streams shown in Figures 5 to 9. It is not difficult to see that the first data streams include at most G _max = 8 first data stream subsets and at least G _min = 2 first data stream subsets. In order to use the same interleaving solution for all services and reduce the convolutional interleaving delay, the first data streams are divided into K1 = G _max = 8 first data stream groups, where any two data streams in each first data stream group are from the same RS codeword, and the corresponding groups are specifically divided as follows: first data streams 0 to 3 are first data stream group 0, first data streams 4 to 7 are first data stream group 1, first data streams 8 to 11 are first data stream group 2, first data streams 12 to 15 are first data stream group 3, first data streams 16 to 19 are first data stream group 4, first data streams 20 to 23 are first data stream group 5, first data streams 24 to 27 are first data stream group 6, and first data streams 28 to 31 are first data stream group 7. Therefore, in this embodiment, the block interleave shown in Figure 35 is used, and the corresponding parameters are K = K1 = 8 and T = 32/K1 = 4, and eight first data streams , which are arbitrary first data streams selected from each first data stream group, are used as eight input data streams of block interleave i (0 < i < 4).

Figure 41 is a schematic diagram of another embodiment of block interleaving. As shown in Figure 41, the eight input data streams of block interleave i (0≦i<4) are first data stream i, first data stream (i+4), first data stream (i+8), first data stream (i+12), first data stream (i+16), first data stream (i+20), first data stream (i+24), and first data stream (i+28), respectively. 16 consecutive RS symbols are obtained from each input data stream to form a first symbol matrix with 8 rows and 16 columns, and the 16 RS symbols in each row are the 16 RS symbols consecutively output from delay line 0, delay line 1, delay line 2, and delay line 3, respectively, of the convolutional interleaver shown in Figure 18(b) in which R=2 polling is performed. 5 to 9, it is not difficult to learn that the first symbol matrix is from 16 different RS codewords, and all eight RS symbols belong to the same RS codeword. Furthermore, in the first symbol matrix, rows 0 to 3 are from at least eight different RS codewords, and rows 4 to 7 are from at least eight different RS codewords, with no two being from the same RS codeword. Furthermore, the RS codeword distributions in all odd-numbered columns or all even-numbered columns of the first symbol matrix may be consistent. Furthermore, in the first symbol matrix, the RS codeword distributions in columns 0 to 3 may be consistent, the RS codeword distributions in columns 2 to 5 may be consistent, the RS codeword distributions in columns 4 to 7 may be consistent, the RS codeword distributions in columns 8 to 11 may be consistent, the RS codeword distributions in columns 10 to 13 may be consistent, and the RS codeword distributions in columns 12 to 15 may be consistent. Furthermore, the RS codeword distribution in the jth, (j+1), (j+8), and (j+9)th columns (j∈{0, 2, 4, 6}) of the first symbol matrix may be consistent. Therefore, to obtain a second symbol matrix with 8 rows and 16 columns, a total of 16 RS symbols, one symbol from each column of the first symbol matrix, may be selected and mapped to one row of the second symbol matrix. The 16 RS symbols in the tth (0≦t<8)th row of the second symbol matrix are 16 consecutive RS symbols in the target data stream (i*8+t) output through block interleaving i. Therefore, one row of the second symbol matrix is defined as the target symbol subset. For ease of explanation, S( _ix , _jy ), _ix∈ [0, 7], _jy∈ [0, 15], are defined as the symbol representing the i- _th row and j- _th column of the first symbol matrix. To allow the 16 RS symbols in the target symbol subset to be from 16 different RS codewords, the 16 RS symbols correspond to S( _i0,0 ), S( _i1,1 ), S(i2,2), ..., S( _i14,14 ), and S _{(i15,15 )} in the first symbol matrix. _i0 , _i1 , _i2 , and _i3 are unequal to one another, _i2 , _i3 , _i4 , and _i5 are unequal to one another, _i4 , _i5 , _i6 , and _i7 are unequal to one another, _i8 , _i9 , _i10 , and _i11 are unequal to one another, _i10 , _i11 , _i12 , and _i13 are unequal to one another, _i12 , _i13 , _i14 , and _i15 are unequal to one another, _i0 , _i1 , _i8 , and _i9 are unequal to one another, _i2 , _i3 , _i10 , and _i11 are unequal to one another, _i4 , _i5 , _i12 , and _i13 are unequal to one another, _i6 , i _i0 , i2, _i4 , i6, i8, _i10 , i12, and _i14 are unequal to each other, _i1 , _i3 , _i5 , _i7 , _i9 , _i11 , _i13 , and _i15 are unequal to each other, and _i0 , _{i1 , i2} , _i3 , _i4 , _{i5 , i6} , i7, _i8 , _i9 , _i10 , _i11 , _i12 , _i13 , _i14 , and _i15 ∈ _[ 0, _{7 ]} . This _is equivalent to each symbol in the target symbol subset being from the _same column in _the first symbol matrix. Furthermore, eight symbols from odd-numbered columns of the first symbol matrix in the target symbol subset are located in different rows of the first symbol matrix, and eight symbols from even-numbered columns of the first symbol matrix in the target symbol subset are located in different rows of the first symbol matrix. Furthermore, symbols in the target symbol subset from the first symbol matrix output from delay lines with the same delay value are located in different rows of the first symbol matrix. Furthermore, in the target symbol subset, every two symbols are from the same row of the first symbol matrix, and two symbols from the same row are output from two different delay lines due to convolutional interleaving, and the delay difference corresponding to the two delay lines is greater than or equal to 2*d*Q=44 symbols. According to this rule, there are many specific mappings from the first symbol matrix to the second symbol matrix. Tables 17 to 20 below provide some specific mapping relationships. The number x in the yth row and zth column of each table indicates that the RS symbol in the yth row and zth column of the second symbol matrix is from the xth RS symbol in the first symbol matrix, where 0≦y<8, 0≦z<16, and 0≦x<128. The xth RS symbol in the first symbol matrix is from the (x%8)th row and (
) indicates the column symbol. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, interleaving between any columns after switching between any rows, or switching between any columns before switching between any rows in the table is performed.

According to the RS codeword distribution rule of the first symbol matrix, another mapping manner from the first symbol matrix to the target symbol subset is that any columns from the 2*j and 2*j+1 columns (j∈[0,7]) of the first symbol matrix are selected, totaling eight columns , and then two RS symbols from each of the selected eight columns , totaling 16 RS symbols, are selected to be mapped to the target symbol subset. The correspondingly selected 16 RSs correspond to S(i0, j0), S( _i1 , _j0 ), S( _i2 , _j1 ), S( _i3 , _j1 ), S( _i4 , _j2 ), S( _i5 , _j2 ), S( _i6 , _j3 ), S( _i7 , _j3 ), S(i8, j4), S( _i9 , _j4 ), S( _i10 , _j5 ), S( _i11 , _j5 ), S( _i12 , _j6 ), S _{( i13} , _j6 ), S( _i14 , _j7 ), and S( _i15 , _j7 ) in _{the first symbol} matrix. _i0 , _i1 , _i2 , _i3 are unequal to one another, _i2 , _i3 , _i4 , _i5 are unequal to one another, _i4 , _i5 , _i6 , _i7 are unequal to one another, _i8 , _i9 , _i10 , _i11 are unequal to one another, _i10 , _i11 , _i12 , _i13 are unequal to one another, _i12 , _i13 , _i14 , _i15 are unequal to one another, _i0 , _i1 , _i8 , _i9 are unequal to one another, _i2 , _i3 , _i10 , _i11 are unequal to one another, _i4 , _i5 , _i12 , _i13 are unequal to one another, _i6 , _i7 , _i14 , _i15 are unequal to each other. _i0 , _i1 , _i2 , i3, _i4 , _i5 , _i6 , i7, _i8 , _i9 , _i10 , _i11 , _i12 , _i13 , _i14 , and _i15 ∈ [0, 7]. _j0 ∈ [ ₀ , ₁ ], _j1 ∈ [2, 3], j2 ∈ [4, 5], _j3 ∈ [6, 7], _j4 ∈ [8 _, 9], _j5 ∈ [10, 11], _j6 ∈ [12, 13], _j7 ∈ [14, 15]. This is equivalent to the case where every two symbols in the target symbol subset are from the same column of the first symbol matrix, with one symbol located in any row from 0 to 3 of the first symbol matrix and the other symbol located in any row from 4 to 7 of the first symbol matrix. Furthermore, eight symbols from odd-numbered columns of the first symbol matrix in the target symbol subset are located in different rows of the first symbol matrix, and eight symbols from even-numbered columns of the first symbol matrix in the target symbol subset are located in different rows of the first symbol matrix. Furthermore, symbols in the target symbol subset from the first symbol matrix output from delay lines with the same delay value are located in different rows of the first symbol matrix. Furthermore, in the target symbol subset, every two symbols are from the same row of the first symbol matrix, and two symbols from the same row are output from two different delay lines due to convolutional interleaving, and the delay difference corresponding to the two delay lines is greater than or equal to 2*d*Q=44 symbols. According to this rule, there are many specific mappings from the first symbol matrix to the second symbol matrix. Tables 21 to 24 provide some specific mapping relationships. The number x in the yth row and zth column of each table indicates that the RS symbol in the yth row and zth column of the second symbol matrix is from the xth RS symbol of the first symbol matrix, where 0≦y<8, 0≦z<16, and 0≦x<128. The xth RS symbol of the first symbol matrix is from the (x%8)th row and (
) indicates the column symbol. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, interleaving between any columns after switching between any rows, or switching between any columns before switching between any rows in the table is performed.

Based on the relationship between the first symbol matrix and the first data stream, and the relationship between the first data stream and the lane data stream, it is not difficult to learn that the 16 symbols of each target symbol subset are from K1=8 lane data streams, and the 8 lane data streams can be represented as lane data stream _j0 , lane data stream _j1 , lane data stream _j2 , lane data stream _j3 , lane data stream _j4 , lane data stream _j5 , lane data stream _j6 and lane data stream _j7 ,
, x∈[0, 7], and
represents j _x /4 rounded down to the nearest integer. Furthermore, if two symbols are obtained from each lane data stream, the spacing between two RS symbols in the corresponding lane data stream is greater than or equal to a*N*K2/n, or in other words, greater than or equal to 2*544*2/32 = 68 RS symbols. Furthermore, the maximum two RS symbols are from two aligned RS symbols in two different lane data streams.

Thirty-two target data streams are generated by block interleaving, and inner code encoding is performed on each target symbol subset within the 32 target data streams, with the information bit length of the inner code encoding being 160 bits. Specifically, to obtain 32 encoded data streams, an inner code encoder separately encodes a total of 160 bits of each target symbol subset within the target data stream and adds redundancy. In one possible embodiment, inner code encoding is performed using Hamming (170, 160) to obtain a 170-bit codeword, adding 10 bits of redundancy to the total 160 bits within 16 consecutive RS symbols within each target data stream. In another possible embodiment, inner code encoding is performed using BCH (176, 160), adding 16 bits of redundancy to the total 160 bits within 16 consecutive RS symbols within each target data stream to obtain a 176-bit codeword. After data processing is performed on the inner-code encoded data streams, the processed data streams are transmitted to a channel transmission medium for transmission.

After data processing is performed on the inner-code encoded data stream, the processed data stream is sent to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, the inner-code encoded data stream may be interleaved to improve the system's ability to tolerate burst errors.

By using the data interleaving and encoding scheme in this embodiment, when Hamming (170, 160) is used as the inner code, the concatenated code of KP4 RS (544, 514) + Hamming (170, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.3E-3, which is close to the optimal performance of the concatenated FEC scheme. When the inner code uses BCH (176, 160), the concatenated code of KP4 RS (544, 514) + BCH (176, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 8.3E-3, which is close to the optimal performance of the concatenated FEC scheme.

Figure 42 is another schematic flowchart of interleaving according to an embodiment of the present application.

4201: Perform first block interleaving on the n lane data streams to obtain T first data streams.

In this embodiment, C consecutive symbols in each first data stream after the first block interleaving are from at least E different code words, where T = n/K1, C is a multiple of a, and E >= K2 * a. Specific implementations of the first block interleaving are described below.

Figure 43 is a schematic diagram of an implementation of performing first block interleaving according to an embodiment of the present application. As shown in Figure 43, the n lane data streams involved in the first block interleaving include a third symbol matrix, where the third symbol matrix includes symbols in n rows and A columns, where the A symbols in different rows of the third symbol matrix are from different lane data streams, and A is a multiple of a. The T first data streams obtained by the first block interleaving include a fourth symbol matrix, where the fourth symbol matrix includes symbols in T rows and C columns, where the C symbols in different rows of the fourth symbol matrix are from different first data streams, and T is a submultiple of n, where n*A=T*C. Specifically, every T consecutive symbols in one column of the third symbol matrix is a symbol submatrix, and the T symbols in each column of the fourth symbol matrix have a one-to-one correspondence with each symbol submatrix in the third symbol matrix.

In one possible embodiment, the symbol submatrices of the third symbol matrix are arranged in a first sequence, and the first through nth rows of each column of the third symbol matrix include the first through (n/T)th symbol submatrices arranged in the first sequence. Two adjacent columns of the third symbol matrix include the (n/T)th symbol submatrix in the preceding column and the first symbol submatrix in the succeeding column, which are two consecutive symbol submatrices arranged in the first sequence. The T symbols in the first column of the fourth symbol matrix are from the first symbol submatrix of the third symbol matrix arranged in the first sequence, and the remaining T symbols in the Cth column of the fourth symbol matrix can be deduced by analogy until they are from the last symbol submatrix of the third symbol matrix arranged in the first sequence. That is, the mapping of all column symbol submatrices of the third symbol matrix to the fourth symbol matrix is performed sequentially from top to bottom and left to right for each column, i.e., the mapping is performed first from top to bottom and then from left to right.

In another possible embodiment, the symbol submatrices of the third symbol matrix are arranged in a second sequence, and the first column through the Ath row of every T rows of the third symbol matrix contain the first through Ath symbol submatrices arranged in the second sequence. The Ath symbol submatrix of the first Tth row and the first symbol submatrix of the second Tth row of two consecutive Tth rows of the third symbol matrix are two consecutive symbol submatrices arranged in the second sequence. The Tth symbols in the first column of the fourth symbol matrix are from the first symbol submatrix of the third symbol matrix arranged in the second sequence, and the remaining T symbols in the Cth column of the fourth symbol matrix can be deduced by analogy until the last symbol submatrix, which is the third symbol matrix arranged in the second sequence. That is, the mapping of the symbol submatrices of a total of n/T rows of the third symbol matrix to the fourth symbol matrix is performed sequentially from left to right and top to bottom of the same row, i.e., the mapping is performed first from left to right and then from top to bottom.

Note that in practical applications, the third symbol matrix and the fourth symbol matrix may not necessarily be presented in matrix form. For example, the third symbol matrix may be presented as a third symbol set, which includes n*A symbol subsets corresponding to the symbols in n rows and A columns of the third symbol matrix. The fourth symbol matrix may be presented as a fourth symbol set, which includes T*C symbol subsets corresponding to the symbols in T rows and C columns of the fourth symbol matrix.

4202: Perform convolutional interleaving on the T first data streams to obtain T second data streams.

In this embodiment, the H consecutive symbols in each of the second data streams are from at least F different codewords, where F≧E, and at most K1/K2 symbols of the H consecutive symbols in each of the second data streams are from the same codeword.

Note that the implementation of convolutional interleaving in this embodiment is similar to the convolutional interleaving described in the embodiment shown in FIG. 10, and the details will not be described again herein. The difference is that each storage unit in the embodiment shown in FIG. 10 is configured to store d symbols, while each storage unit in this embodiment is configured to store C symbols. In a possible implementation, when the convolutional interleaver shown in FIG. 12(a) is used, the parameters of the convolutional interleaver satisfy C(p*Q+1)≧a*N*K1/(n/k2), so that H=p*C consecutive symbols in the first data stream output by the convolutional interleaver are from codewords of at least F different outer codes, where N is the codeword length of the outer code encoding. In another possible implementation, when the convolutional interleaver shown in FIG. 12(b) is used, the parameters of the convolutional interleaver satisfy C(p*Q-1)≧a*N*K1/(n/k2), such that H=p*C consecutive symbols in the first data stream output by the convolutional interleaver are from codewords of at least F different outer codes, where N is the codeword length of the outer code encoding.

4203: Perform second block interleaving on each of the T second data streams to obtain S target data streams, for a total of m target data streams.

In this embodiment, m = T * S, and S ≥ k1/K2. A specific implementation of the second block interleaving will be described below. Figure 44(a) is a schematic diagram of an implementation of performing the second block interleaving according to an embodiment of the present application. As shown in Figure 44(a), each second block interleaver performs block interleaving on the input second data stream to obtain S target data streams, thereby generating a total of m = T * S target data streams.

FIG. 44(b) is a schematic diagram of a specific implementation of performing second block interleaving according to an embodiment of the present application. As shown in FIG. 44(b), each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output from p delay lines, and the symbols in each symbol set are from at least F different codewords. Each target data stream includes F symbols, where R*p*C=S*F, where R is a greater than or equal integer. That is, the second block interleaving is performed on the R symbol sets output from the p delay lines of the convolutional interleaver that has been polled R times to obtain S target data streams. It should be understood that one block interleaving operation is performed to obtain only F consecutive symbols in the target data stream, and the target data stream is obtained by consecutive block interleaving. The F consecutive symbols in the target data stream are represented as target symbol subsets. All F consecutive symbols in the target data stream are at least
are from different symbol subsets,
each of the different symbol subsets having at most K2*a symbols;
represents the integer obtained by rounding up the quotient of F/(K2 * a). The maximum of all F consecutive symbols in each target data stream is
symbols are from the same symbol set,
It should further be appreciated that represents the integer obtained by rounding up the quotient of F/R.

In a possible embodiment, all F consecutive symbols in the target data stream include a first symbol group from a first symbol subset and a second symbol group from a second symbol subset, where the first symbol subset and the second symbol subset belong to the same symbol set. The first symbol subset and the second symbol subset are output from two adjacent delay lines, respectively, and the symbols in the first symbol subset and the symbols in the second symbol subset are sequentially arranged separately, with the ranking of the first symbol group in the first symbol subset being different from the ranking of the second symbol group in the second symbol subset. That is, the first symbol group and the second symbol group have different positions within their respective symbol subsets.

In another possible implementation, all F consecutive symbols in the target data stream include a third symbol group from the third symbol subset and a fourth symbol group from the fourth symbol subset, the third symbol subset and the fourth symbol subset belonging to different symbol sets, the third symbol subset and the fourth symbol subset being output from the same delay line, the symbols in the third symbol subset and the symbols in the fourth symbol subset being sequentially arranged separately, and the ranking of the third symbol group in the third symbol subset being different from the ranking of the fourth symbol group in the fourth symbol subset, i.e., the third symbol group and the fourth symbol group having different positions within their respective symbol subsets.

In the present invention, a data interleaving and encoding method is designed for the concatenated FEC transmission solution, including first block interleaving, convolutional interleaving, second block interleaving, and encoding, so that the same interleaving solution can be used for all access services, and the entire concatenated FEC solution has good performance and low latency. Therefore, the concatenated FEC transmission solution can be applied to multiple transmission scenarios and is particularly applicable to transmission scenarios that require low transmission latency, such as low-latency data center interconnection scenarios.

The steps of the interleaving method shown in FIG. 42 will be further described below with reference to several specific embodiments. It should be understood that the inner code parallelism in each of the following embodiments is the number of target data streams. For example, an inner code parallelism of 16 indicates that the number of target data streams is 16. It should also be understood that a target symbol subset in the following embodiments represents F consecutive symbols in the target data stream.

Embodiment 1: The information bit length of the inner code encoding is 120 bits, and the inner code parallelism is 16.

Based on the type of access service, the transmitting-side processing module performs alignment marker lock on the lane data streams by using the known alignment markers of the PCS or FEC lanes of each service. The known alignment markers of the 32 lanes are different and associated with the access service. The transmitting-side processing module then performs deskew on multiple PCS or FEC lanes in each service. After deskew, all multiple PCS/FEC lanes within the same service are AM aligned, and lane data streams between services only need to satisfy RS symbol alignment, i.e., the difference between AMs is an integer number of RS symbols. For example, if the access service is a 2*400GbE service, Figure 37 shows 32 deskewed lane data streams. AM alignment is performed between the 16 PCS lanes in each 400GbE service, and the difference between AMs of the two services is an integer number of RS symbols. Then, based on the alignment marker, lane reordering is performed on the data in the n=32 lanes, so that the data in the n=32 lanes can be arranged in a specified sequence. For example, when the access service is a 1*800GbE service, 32 lane data streams are shown in FIG. 5. When the access service is a 2*400GbE service, 32 lane data streams are shown in FIG. 6. When the access service is a 4*200GbE service, 32 lane data streams are shown in FIG. 7. When the access service is an 8*100GbE service in "100G RS-FEC-Int" mode, 32 lane data streams are shown in FIG. 8. When the access service is an 8*100GbE service in "100G RS-FEC" mode, 32 lane data streams are shown in FIG. 9.

The n=32 lane data streams on which lane permutation is performed are sent to the designated first block interleaving module, convolutional interleaving module, and second block interleaving module for corresponding processing, and then sent to the inner code encoder for inner code encoding. After data processing is performed on the inner code encoded data stream, the data processed data stream is sent to the channel transmission medium for transmission. The data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc.

In this embodiment, the n lane data streams are divided into G lane data stream subsets according to the RS distribution rule within the lane data stream, and any two lane data stream subsets are from different RS codewords. Thus, the number of lane data stream subsets included in a lane data stream varies depending on the access service. See the PCS/FEC lane data stream formats shown in Figures 5 to 9. For example, if the access service is a 1*800 Gb service or a 2*400 Gb service, the 32 lane data streams include G = 2 lane data stream subsets. Specifically, lane data streams 0 to 15 are lane stream subsets, and lane data streams 16 to 31 are lane stream subsets. For example, if the access service is a 4*200 GbE service, the 32 lane data streams include G = 4 lane data stream subsets. For example, if the access service is a 1*800GbE service and the 32 lane data streams include G=8 lane data stream subsets, then the 32 lane data streams include at most G _max =n/4=8 lane data stream subsets and at least G _min =n/16=2 lane data stream subsets. To enable the first block interleaving to be unaffected by the access service and to minimize the overall interleaving latency, the first interleaving module corresponds to parameters K1=G _max =8 and T=n/K1=4.

Figure 45(a) is a schematic diagram of a first block interleaving implementation. As shown in Figure 45(a), A = 2 consecutive symbols are selected from each lane data stream to form a third symbol matrix with 32 rows and 2 columns, and block interleaving is performed to obtain a fourth symbol matrix with T = 4 rows and C = 16 columns. The C = 16 symbols in the t-th row of the fourth symbol matrix are 16 consecutive symbols of the first data stream t, where 0 < t < 3. The symbol in the ith row and j-th column of the fourth symbol matrix is from the x-th row and y-th column of the third symbol matrix, where x = j * 4% 32 + i and
(0 ≤ i < 4 and 0 ≤ j < 16) is satisfied,
represents rounding down j*4/32 to the nearest integer. One row of the fourth symbol matrix is defined as one symbol subset. Referring to the PCS/FEC lane data stream format shown in Figures 5 to 9, the symbols in each symbol subset are from K1 = 8 different lane data streams, and the 8 lane data streams are named lane data stream _j0 , lane data stream _j1 , lane data stream _j2 , lane data stream _j3 , lane data stream _j4 , lane data stream _j5 , lane data stream _j6 , lane data stream _j7 ,
, x∈[0,7].
represents the rounding down of j _x /4 to the nearest integer, and each symbol subset is from at least K2*a=4 different RS codewords and at most K1*a=16 different RS codewords, where K2=G _min .

The four first data streams obtained through the first block interleaving module are sent to a convolutional interleaving module to obtain four second data streams. The convolutional interleaving module includes four convolutional interleavers: Convolutional Interleaver 0, Convolutional Interleaver 1, Convolutional Interleaver 2, and Convolutional Interleaver 3. The four convolutional interleavers use the same interleaving structure, and each convolutional interleaver interleaves one first data stream to obtain one second data stream.

Figure 45(b) is a schematic diagram of an embodiment of convolutional interleaving. As shown in Figure 45(b), p = 3 delay lines are included. The p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit has d = C = 16 symbols, or in other words, is used to store one symbol subset in the first data stream. That is, delay line 0 has a delay value of 32Q symbols, delay line 1 has a delay value of 16Q symbols, and delay line 1 has a delay value of 0 symbols, i.e., no delay.

As shown in Figure 45(b), _Sr () represents a symbol subset in the first data stream r (0 < r < T-1), which includes C = 16 symbols. For example, _Sr (3t) represents the symbol subset currently input to delay line 0 from the first data stream r, and _Sr (3t-6Q) is the symbol subset output from delay line 0; _Sr (3t+1) represents the symbol subset currently input to delay line 1 from the first data stream r, and _Sr (3t-3Q+1) is the symbol subset output from delay line 1; _Sr (3t+2) represents the symbol subset currently input to delay line 2 from the first data stream r, and _Sr (3t+2) is the symbol subset output from delay line 2; _Sr (3t+3) represents the symbol subset currently input to delay line 0 from the first data stream r, and _Sr (3t-6Q+4) is the symbol subset output from delay line 0; and so on. Referring to Figures 5 and 6, if the access service is a 1*800GbE service or a 2*400GbE service and C(p*Q+1)≧a*N*K1/b=544, i.e., Q≧11, it can be learned that the three symbol subsets _Sr (3t-6Q), _Sr (3t-3Q+1), and _Sr (3t+2) output consecutively by convolutional interleaving contain 12 different RS code words. 7 and 9, when the access service is a 4*200Gb service or an 8*100Gb service, is in "100G RS-FEC" mode, and C(p*2*Q+2)≧a*N*K1/b=1088, i.e., Q≧11, it can be learned that the three symbol subsets _Sr (3t-6Q), _Sr (3t-3Q+1), and _Sr (3t+2) successively output by convolutional interleaving contain 16 different RS codewords. Referring to FIG. 8, when the access service is an 8*100GbE service, is in "100G RS-FEC-int" mode, and Q≧0, it can be learned that the three symbol subsets _Sr (3t-6Q), _Sr (3t-3Q+1), and _Sr (3t+2) successively output by convolutional interleaving contain 16 different RS codewords. Therefore, when Q>11, it can be ensured that for all access services, the three symbol subsets _Sr (3t-6Q), _Sr (3t-3Q+1), and _Sr (3t+2) successively output by convolutional interleaving contain at least 12 different RS code words.

Figure 45(c) is a schematic diagram of another embodiment of convolutional interleaving. As shown in Figure 45(c), in a possible embodiment, Q = 11 is selected, and the corresponding interleaving latency is approximately 22 * 16 * 3/2 = 528 RS symbols.

The convolutional interleaver shown in Figure 45(c) performs convolutional interleaving separately on the four fourth data streams to obtain four second data streams. Three symbol subsets Sr(3t-6Q), Sr(3t-3Q+1), and _Sr (3t+2) of the second data streams output from delay _line 0, delay line 1, and delay _line 2 of the convolutional interleaver, respectively, are defined as symbol sets, and the symbol sets include a total of 48 RS symbols. The 16 symbols in each symbol subset are sequentially represented as symbol 0 to symbol 15. Referring to the distribution of RS codewords on the PCS/FEC lanes of various services, the first block interleaving, and the convolutional interleaving in Figures 5 to 9, it is not difficult to see that each symbol subset is from at least four different RS codewords; and the RS codeword corresponding to symbols 0 to 3 may be different from the RS codeword corresponding to symbols 4 to 7 in the same symbol subset, the RS codeword corresponding to symbols 8 to 11 may be different from the RS codeword corresponding to symbols 12 to 15 in the same symbol subset, and the RS codeword corresponding to symbols 0 to 7 may be the same as the RS codeword corresponding to symbols 8 to 15 in the same symbol subset. Furthermore, a symbol set is from at least 12 different RS codewords, and a maximum of K1/K2 = 4 symbols in a symbol set belong to the same RS codeword. Furthermore, the distribution of RS codewords corresponding to symbols 0 to 7 in any two symbol subsets may be consistent, and the distribution of RS codewords corresponding to symbols 8 to 15 in any two symbol subsets may be consistent.

Four second block interleavers are used to separately interleave the four second data streams to obtain m = S * T = 16 target data streams. Figure 45(d) is a schematic diagram of an embodiment of the second block interleaver. As shown in Figure 45(d), in second block interleaver i (0 ≤ i < 4), one symbol set is obtained from second data stream i, and four RS symbols from each symbol subset , a total of 12 RS symbols, are selected and mapped to one target symbol subset to obtain a total of S = 4 target symbol subsets. The 12 symbols in each target symbol subset are from 12 different RS codewords, and the four target symbol subsets are 12 consecutive RS symbols from target data stream i * S to target data stream (i * S + 3) output by block interleaver i, respectively. For ease of explanation, R(x,y) is defined as symbol y in symbol subset x, where x∈[0,2] and y∈[0,15]. For symbols R( _x1 , _y1 ) and R( _x2 , _y2 ), respectively, from any two symbol subsets, _x1 ≠ _x2 . If _y1 ≠ _y2 , this indicates that the two symbols are located at different locations in the symbol subsets. To allow the 12 RS symbols in the target symbol subset to be from 12 different RS codewords, the 12 RS symbols correspond to R(0,i0), R(0, _i1 ), R(0, _i2 ), R(0, _i3 ), R(1, _i4 ), R(1, _i5 ), R(1, _i6 ), R(1, _i7 ), R(2, _i8 ), R(2, _i9 ), R(2, _i10 ), and R(2, _i11 ) in the symbol set, satisfying the following cases: _i0 , _i4 , and _{i8 are} different from each other, _i1 , _i5 , and _i9 are different from each other, _i2 , _i6 , and _i10 are different from each other, _i3 , _i7 , and _i11 are different from each other, and _i0 , _i2 , i8, _i4 , and i _i0 , _i4 , and i8 ∈ [0, _3] , _i1 , _i5 , and _i9 ∈ [4, ₇ ], _i2 , _i6 , and _i10 ∈ [ ₈ , ₁₁ ], _{and i3} , _i7 , and _i11 ∈ [ _{12 , 15} ]. This is equivalent to _{the case where} the 12 RS symbols in the target symbol subset are symbols in different positions in _three symbol subsets, and every fourth _RS symbol is from _the same symbol subset. Furthermore, four symbols in the target symbol subset from the same symbol subset are any one of symbols 0 to 3 in the symbol subset, any one of symbols 4 to 7 in the symbol subset, any one of symbols 8 to 11 in the symbol subset, and any one of symbols 12 to 15 in the symbol subset, respectively. Furthermore, eight RS symbols output from two delay lines in the target symbol subset with a delay difference of Q*C=176 are located at different locations in the corresponding symbol subset. Furthermore, up to two RS symbols in the target symbol subset are from the same lane data stream and are mapped to two different symbol subsets by the first block interleaving. The corresponding two symbol subsets are output from two different delay lines of the convolutional interleaver, and the delay difference corresponding to the two delay lines is greater than or equal to 2*Q*C=352 RS symbols.

According to this rule, there are multiple specific mappings from symbol sets to target symbol subsets. Tables 1 to 4 provide some specific mapping relationships. The number x in the y-th row and z-th column of each of Tables 1 to 4 indicates the location of the z-th RS symbol in target data stream y in the symbol subset.
where 0≦y<4, 0≦z<12, and 0≦x<48. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, switching between any columns after switching between any rows, or switching between any columns before switching between any rows is performed.

Based on the mapping relationship between each symbol subset and the lane data stream and the latency relationship between each symbol subset within a symbol set, it is not difficult to learn that the relationship between the target symbol subset and the lane data stream is as follows: the data of the target symbol subset comes from K1 = 8 different lane data streams, and the 8 lane data streams can be represented as lane data stream _j0 , lane data stream _j1 , lane data stream _j2 , lane data stream _j3 , lane data stream _j4 , lane data stream _j5 , lane data stream _j6 , and lane data stream _j7 .
, x∈[0, 7], and
represents j _x /4 rounded down to the nearest integer. Furthermore, one RS symbol is selected from four lane data streams, and two RS symbols are selected from the remaining four lane data streams. Furthermore, when two RS symbols are selected from a lane data stream, the spacing distance between the two RS symbols in the corresponding lane data stream is greater than a*N*K2/n, or in other words, greater than or equal to 2*544*2/32 = 68 RS symbols. Furthermore, the maximum two RS symbols are from two aligned RS symbols in two different lane data streams.

The 16 target data streams obtained by block interleaving are sent separately to an inner code encoder. Each target symbol subset is used as one piece of information data for inner code encoding. To obtain the 16 encoded data streams, the inner code encoder generates redundant data. In one possible embodiment, inner code encoding is performed using Hamming (128, 120) to obtain 128-bit code words, with 8 bits of redundancy added to the 120 bits of the 12 RS symbols in each target symbol subset in the target data stream. In another possible embodiment, inner code encoding is performed using BCH (136, 120) to obtain 136-bit code words, with 16 bits of redundancy added to the 120 bits of the 12 RS symbols in each target symbol subset in the target data stream.

After data processing is performed on the inner-code encoded data stream, the processed data stream is sent to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, the inner-code encoded data stream may be interleaved to improve the system's ability to tolerate burst errors.

By using the data interleaving and encoding scheme of this embodiment, the concatenated KP4 RS (544, 514) + Hamming (128, 120) code in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3, which is close to the optimal performance of the concatenated FEC scheme.

Embodiment 2: The information bit length of the inner code encoding is 160 bits, and the inner code parallelism is 16.

In this embodiment, a first block interleaving is performed on n lane data streams by using the first block interleaving solution of embodiment 1 to obtain T=4 first data streams, and then four convolutional interleavers separately perform convolutional interleaving on the four first data streams to obtain four second data streams. Convolutional Interleave 0, Convolutional Interleave 1, Convolutional Interleave 2, and Convolutional Interleave 3 use the same interleaving structure.

Figure 46(a) is a schematic diagram of another embodiment of convolutional interleaving. As shown in Figure 46(a), p = 4 delay lines are included. The four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively. Each storage unit has d = C = 16 symbols, or in other words, is used to store one symbol subset in the first data stream. That is, delay line 0 has a delay value of 48Q symbols, delay line 1 has a delay value of 32Q symbols, delay line 2 has a delay value of 16Q symbols, and delay line 3 has a delay value of 0 symbols, i.e., no delay.

As shown in FIG. 46(a), S _r ( ) represents one symbol subset in the first data stream r (0≦r≦T−1). For example, _Sr (4t) represents the symbol subset currently input to delay line 0 from the first data stream r, and _Sr (4t-12Q) is the symbol subset output from delay line 0; _Sr (4t+1) represents the symbol subset currently input to delay line 1 from the first data stream r, and _Sr (4t-8Q+1) is the symbol subset output from delay line 1; _Sr (4t+2) represents the symbol subset currently input to delay line 2 from the first data stream r, and _Sr (4t-4Q+2) is the symbol subset output from delay line 2; _Sr (4t+3) represents the symbol subset currently input to delay line 3 from the first data stream r, and _Sr (4t+3 ₎ is the symbol subset output from delay line 3; where Sr(4t+4) represents the symbol subset currently input to delay line 0 from the first data stream r, _Sr (4t-12Q+4) is the symbol subset output from delay line 0, etc. Referring to Figures 5 and 6, when the access service is a 1*800 GbE service or a 2*400 GbE service and C(p*Q+1)≥544, i.e., Q≥9, it can be learned that the four symbol subsets _Sr (4t-12Q), _Sr (4t-8Q+1), _Sr (4t-4Q+2), and _Sr (4t+3) successively output by convolutional interleaving contain 16 different RS code words. Referring to Figures 7 and 9, when the access service is a 4*200Gb service or an 8*100Gb service, is in "100G RS-FEC" mode, and C(p*2*Q+2)≧1088, i.e., Q≧9, it can be learned that the four symbol subsets _Sr (4t-12Q), _Sr (4t-8Q+1), _Sr (4t-4Q+2), and _Sr (4t+3) output consecutively by convolutional interleaving contain 16 different RS code words. 8, it can be learned that when the access service is an 8*100 GbE service, is in "100G RS-FEC-int" mode, and Q≧0, the four symbol subsets _Sr (4t−12Q), _Sr (4t−8Q+1), _Sr (4t−4Q+2), and _Sr (4t+3) successively output by convolutional interleaving contain 16 different RS codewords. Therefore, when Q≧9, it can be guaranteed that for all access services, the four symbol subsets _Sr (4t−12Q), _Sr (4t−8Q+1), _Sr (4t−4Q+2), and _Sr (4t+3) successively output by convolutional interleaving contain 16 different RS codewords.

Figure 46(b) is a schematic diagram of another embodiment of convolutional interleaving. As shown in Figure 46(b), in a possible embodiment, Q = 9 is selected, and the corresponding interleaving latency is approximately 27 * 16 * 3/2 = 648 RS symbols.

The four convolutional interleavers shown in Figure 46(b) are used to separately perform convolutional interleaving on the four fourth data streams to obtain four second data streams. Four symbol subsets Sr(4t-12Q), _Sr (4t-8Q+1), Sr(4t-4Q+2), and _Sr (4t+3) of the second data stream output from Delay Line 0, Delay _Line 1, Delay Line 2, and Delay _Line 3 of the convolutional interleaver, respectively, are defined as symbol sets, and the symbol sets include a total of 64 RS symbols. The 16 symbols in each symbol subset are sequentially designated as Symbol 0 to Symbol 15. Referring to the distribution of RS codewords on the PCS/FEC lanes of various services, the first block interleaving, and the convolutional interleaving in Figures 5 to 9, it is not difficult to see that each symbol subset is from at least four different RS codewords; and the RS codeword corresponding to symbols 0 to 3 may be different from the RS codeword corresponding to symbols 4 to 7 in the same symbol subset, the RS codeword corresponding to symbols 8 to 11 may be different from the RS codeword corresponding to symbols 12 to 15 in the same symbol subset, and the RS codeword corresponding to symbols 0 to 7 may be the same as the RS codeword corresponding to symbols 8 to 15 in the same symbol subset. Furthermore, a symbol set is from 16 different RS codewords, and a maximum of K1/K2 = 4 symbols in a symbol set belong to the same RS codeword. Furthermore, the distribution of RS codewords corresponding to symbols 0 to 7 in any two symbol subsets may be consistent, and the distribution of RS codewords corresponding to symbols 8 to 15 in any two symbol subsets may be consistent. Four second block interleavers are used to separately interleave the four second data streams to obtain m = S * T = 16 target data streams. Figure 46(c) is a schematic diagram of another embodiment of the second block interleaver. As shown in Figure 46(c), in second block interleaver i (0 ≤ i < 4), one symbol set is obtained from second data stream i, and four RS symbols from each symbol subset , a total of 16 RS symbols, are selected and mapped to one target symbol subset to obtain a total of S = 4 target symbol subsets. The 16 symbols in each target symbol subset are from 16 different RS codewords, and the four target symbol subsets are 16 consecutive RS symbols from target data stream i * S to target data stream (i * S + 3) output by block interleaver i, respectively. For ease of explanation, R(x,y) is defined as the symbol y in the symbol subset x, where x∈[0,3] and y∈[0,15]. To allow the 16 RS symbols in the target symbol subset to be from 16 different RS codewords, the 16 RS symbols correspond to R(0,i0), R(0, _i1 ), R(0, _i2 ), R(0, _i3 ), R(1, _i4 ), R(1, _i5 ), R(1, _i6 ), R(1, _i7 ), R(2, _i8 ), R(2, _i9 ), R(2, _i10 ), R(2, _i11 ), R(3, _i12 ), R(3, _i13 ), R(3, _i14 ), and R( ₃ , _i15 ) in the symbol set, satisfying the following cases: _i0 , _i4 , _i8 , and _i12 are different from each other, _i1 , _i5 , _i9 , and _i13 are different from each other, _{and i2} , i ₆ , _i10 , and _i14 are different from each other, _i3 , _i7 , _i11 , and _i15 are different from each other, _i0 , _i2 %8, _i4 , and _i6 %8 are different from each other, _i4 , _i6 %8, _i8 , and _i12 %8 are different from each other, _i8 , _i12 %8, _i14 , and _i16 %8 are different from each other, _i1 , _i3 %8, _i5 , _i7 %8 are different from each other, _i5 , _i7 %8, _i9 , and _i11 %8 are different from each other, _i9 , _i11 %8, _i13 , and _i15 %8 are different from each other, _i0 , _i4 , and _i8 , and _i12 ∈[0, 3], _i1 , _i5 , _i9 , and _i13 ∈[4, 7], _i2 , _i6 , _i10 , and _i14 ∈[8, 11], and _i3 , _i7 , _i11 , and _i15 ∈[12, 15]. This is equivalent to the case where the 16 RS symbols in the target symbol subset are symbols in different positions in the four symbol subsets, and every fourth RS symbol is from the same symbol subset. Furthermore, the four symbols in the target symbol subset from the same symbol subset are any one of symbols 0 to 3 in the symbol subset, any one of symbols 4 to 7 in the symbol subset, any one of symbols 8 to 11 in the symbol subset, and any one of symbols 12 to 15 in the symbol subset, respectively. Furthermore, eight RS symbols in the target symbol subset from the symbol subsets output from the two delay lines with a delay difference of Q*C=144 are located at different locations in the corresponding symbol subset. Furthermore, up to two RS symbols in the target symbol subset are from the same lane data stream and are mapped to two different symbol subsets by the first block interleaving. The two corresponding symbol subsets are output from two different delay lines of the convolutional interleaver, and the delay difference corresponding to the two delay lines is greater than or equal to 2*Q*C=288 RS symbols.

According to this rule, there are multiple specific mappings from symbol sets to target symbol subsets. Tables 13 to 16 provide some specific mapping relationships. The number x in the y-th row and z-th column of each table indicates that the z-th RS symbol in target symbol subset y is
where 0≦y<4, 0≦z<16, and 0≦x<64. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, switching between any columns after switching between any rows, or switching between any columns before switching between any rows is performed.

According to the mapping relationship between each symbol subset and the lane data stream and the latency relationship between each symbol subset within a symbol set, it is not difficult to learn that the relationship between the data of the target symbol subset and the lane data stream is as follows: the data of the target symbol subset comes from K1=8 different lane data streams, and the 8 lane data streams can be represented as lane data stream _j0 , lane data stream _j1 , lane data stream _j2 , lane data stream _j3 , lane data stream _j4 , lane data stream _j5 , lane data stream _j6 , and lane data stream _j7 .
, x∈[0, 7], and
represents j _x /4 rounded down to the nearest integer. Furthermore, when two RS symbols are selected from each lane data stream, the spacing distance between two RS symbols in the corresponding lane data stream is greater than or equal to a*N*K2/n, or in other words, greater than or equal to 2*544*2/32 = 68 RS symbols. Furthermore, the maximum two RS symbols are from two aligned RS symbols in two different lane data streams.

The 16 target data streams obtained by block interleaving are separately sent to an inner code encoder. Each target symbol subset is used as one piece of information data for inner code encoding. To obtain the 16 encoded data streams, the inner code encoder generates redundant data. In one possible embodiment, inner code encoding is performed using Hamming (170, 160) to obtain a 170-bit codeword, with 10 bits of redundancy added to the 160 bits of the 16 RS symbols in each target symbol subset. In another possible embodiment, inner code encoding is performed using BCH (176, 160) to obtain a 176-bit codeword, with 16 bits of redundancy added to the 160 bits of the 16 RS symbols in each target symbol subset. After data processing is performed on the inner code encoded data streams, the processed data streams are transmitted to a channel transmission medium for transmission.

By using the data interleaving and encoding scheme in this embodiment, when Hamming (170, 160) is used as the inner code, the concatenated code of KP4 RS (544, 514) + Hamming (170, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.3E-3, which is close to the optimal performance of the concatenated FEC scheme. When the inner code uses BCH (176, 160), the concatenated code of KP4 RS (544, 514) + BCH (176, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 8.3E-3, which is close to the optimal performance of the concatenated FEC scheme.

Embodiment 3: The information bit length of the inner code encoding is 120 bits, and the inner code parallelism is 32.

In this embodiment, a first block interleaving is performed on the n lane data streams by using the first block interleaving solution of Embodiment 1 to obtain T=4 first data streams, and then a convolutional interleaver shown in FIG. 45(c) separately performs convolutional interleaving on the four first data streams to obtain four second data streams. Three symbol subsets Sr(3t-6Q), Sr(3t-3Q+1), and _Sr (3t+2) in the second data streams, which are output from delay _line 0, delay line 1, and delay line 2 of the convolutional _interleaver , respectively, are defined as symbol sets. Q=2 consecutive symbol sets are selected from each second data stream and marked as symbol set 0 and symbol set 1. The symbol sets include a total of six symbol subsets: symbol subset 0, symbol subset 1, symbol subset 2, symbol subset 3, symbol subset 4, and symbol subset 5. In the second block interleaver i (0≦i<4), block interleaving is performed on two consecutive symbol sets in the second data stream i to obtain eight target symbol subsets, each containing 12 RS symbols, where the eight target symbol subsets are 12 consecutive RS symbols from target data stream i*S to target data stream (i*S+7) output by block interleaver i, respectively, and each RS symbol in a target symbol subset is from a different RS codeword. 5 through 9 , it is not difficult to see that each symbol subset is from at least four different RS codewords; and that the RS codeword corresponding to symbols 0 through 3 may be different from the RS codeword corresponding to symbols 4 through 7 in the same symbol subset, that the RS codeword corresponding to symbols 8 through 11 may be different from the RS codeword corresponding to symbols 12 through 15 in the same symbol subset, and that the RS codeword corresponding to symbols 0 through 7 may be the same as the RS codeword corresponding to symbols 8 through 15 in the same symbol subset. Furthermore, the distribution of RS codewords corresponding to symbols 0 through 7 in any two symbol subsets may be consistent, and the distribution of RS codewords corresponding to symbols 8 through 15 in any two symbol subsets may be consistent. Furthermore, each symbol set is from at least 12 different RS codewords, a maximum of four symbols in a symbol set belong to the same RS codeword, and the RS codeword distribution in symbol set 0 is consistent with the RS codeword distribution in symbol set 1.

Figure 47 is a schematic diagram of another embodiment of the second block interleaving. As shown in Figure 47, a total of 12 RS symbols, two RS symbols from each symbol subset, are selected and mapped to one target symbol subset to obtain a total of eight target symbol subsets. For ease of explanation, R(x, y) is defined as symbol y in symbol subset x (x ∈ [0, 5] and y ∈ [0, 15]). To allow the 12 RS symbols in the target symbol subset to be from 12 different RS codewords, the 12 RS symbols correspond to R(0, _{i0), R(0, i1} ), R(1, _i2 ), R(1, _i3 ), R(2, _i4 ), and R(2, _i5 ), and R(3, _i6 ), R(3, _i7 ), R(4, _i8 ), R(4, _i9 ), R(5, _i10 ), and R(5, _i11 ) in the two symbol sets, satisfying the following cases: _i0 , _i1 , _i2 , _i3 , _i4 , _i5 , _i6 , _i7 , _i8 , _i9 , _i10 , _{and i11} are different from each other, and _i0 %8, _i1 %8, _i2 %8, and i _{i 3} %8 are different from each other, i ₂ %8, i ₃ %8, i ₄ %8, and i ₅ %8 are different from each other, i ₆ %8, i ₇ %8, i ₈ %8, and i ₉ %8 are different from each other, i ₈ %8, i ₉ %8, i ₁₀ %8, and i ₁₁ %8 are different from each other, i ₀ %8, i ₁ %8, i ₆ %8, and i ₇ %8 are different from each other, i ₂ %8, i ₃ %8, i ₈ %8, and i ₉ %8 are different from each other, i ₄ %8, i ₅ %8, i ₁₀ %8, and i ₁₁ %8 are different from each other, i ₀ , i ₁ , i ₂ , i ₃ , i ₄ , i ₅ , i ₆ , i ₇ , i where _i8 , _i9 , _i10 , and _i11 ∈ [0, 15]. This is equivalent to the case where the 12 RS symbols in the target symbol subset are symbols at different positions in the six symbol subsets, and every two RS symbols are from the same symbol subset. Furthermore, the four RS symbols output from the two delay lines with a delay difference of Q*C = 176 from the symbol subset in the target symbol subset are located at different positions in the corresponding symbol subset. Furthermore, the four RS symbols output from the same delay line of the convolutional interleaver from the two symbol subsets in the target symbol subset are located at different positions in the corresponding symbol subset. Furthermore, up to two RS symbols in the target symbol subset are from the same lane data stream and are mapped to two different symbol subsets by the first block interleaving. The two corresponding symbol subsets are output from two different delay lines of the convolutional interleaver, and the delay difference corresponding to the two delay lines is greater than or equal to 2*Q*C=352 RS symbols. According to this rule, there are several specific mappings in which two symbol sets are interleaved into eight target symbol subsets. Tables 5 to 12 provide some specific mapping relationships. The number x in the yth row and zth column of each table indicates that the zth RS symbol of target symbol subset y is interleaved into the symbol subset.
where 0≦y<8, 0≦z<12, and 0≦x<96. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, interleaving between any columns after switching between any rows, or switching between any columns before switching between any rows in the table is performed.

Based on the mapping relationship between each symbol subset and the lane data stream and the latency relationship between each symbol subset within a symbol set, it is not difficult to learn that the relationship between the target symbol subset and the lane data stream is as follows: the data of the target symbol subset comes from K1 = 8 different lane data streams, and the 8 lane data streams can be represented as lane data stream _j0 , lane data stream _j1 , lane data stream _j2 , lane data stream _j3 , lane data stream _j4 , lane data stream _j5 , lane data stream _j6 , and lane data stream _j7 .
, x∈[0, 7], and
represents j _x /4 rounded down to the nearest integer. Also, one RS symbol is selected from four lane data streams, and two RS symbols are selected from the remaining four lane data streams. Furthermore, when two RS symbols are selected from a lane data stream, the spacing distance between the two RS symbols in the corresponding lane data stream is greater than or equal to 2 * 544 * 2 / 32 = 68 RS symbols. Furthermore, the maximum two RS symbols are from two aligned RS symbols in two different lane data streams.

The 32 target symbol subsets obtained by block interleaving are sent separately to the inner code encoder. Each target symbol subset is used as one piece of information data for inner code encoding. To obtain 32 encoded data streams, the inner code encoder generates redundant data. In one possible implementation, inner code encoding is performed using Hamming (128, 120) to obtain a 128-bit codeword, with 8 bits of redundancy added to the 120 bits of the 12 RS symbols in the target symbol subset. In another possible implementation, inner code encoding is performed using BCH (136, 120) to obtain a 136-bit codeword, with 16 bits of redundancy added to the 120 bits of the 12 RS symbols in the target symbol subset.

After data processing is performed on the inner-code encoded data stream, the processed data stream is sent to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, the inner-code encoded data stream may be interleaved to improve the system's ability to tolerate burst errors.

Embodiment 4: The information bit length of the inner code encoding is 160 bits, and the inner code parallelism is 32.

Using the first block interleaving solution of embodiment 1, a first block interleaving is performed on the n lane data streams to obtain T=4 first data streams, and the convolutional interleaver shown in FIG. 46(b) separately performs convolutional interleaving on the four fourth data streams to obtain four second data streams. Four symbol subsets Sr(4t-12Q), Sr(4t-8Q+1), _Sr (4t-4Q+2), and _Sr (4t+3) of the second data stream output from Delay Line 0, Delay Line 1, Delay _Line 2, and Delay _Line 3 of the convolutional interleaver, respectively, are defined as symbol sets, and the symbol sets include a total of 64 RS symbols. In the second block interleave i (0≦i<4), block interleaving is performed on two consecutive symbol sets in the second data stream i to obtain eight target symbol subsets. Each target symbol subset includes 16 RS symbols, and the eight target symbol subsets are 16 consecutive RS symbols from target data stream i*S to target data stream (i*S+7) output by block interleaver i, respectively, and each RS symbol in a target symbol subset is from a different RS codeword. Referring to the distribution of RS codewords on the PCS/FEC lanes of various services, the first block interleaving, and the convolutional interleaving in Figures 5 to 9, it is not difficult to see that each symbol subset is from at least four different RS codewords; and the RS codeword corresponding to symbols 0 to 3 may be different from the RS codeword corresponding to symbols 4 to 7 in the same symbol subset, the RS codeword corresponding to symbols 8 to 11 may be different from the RS codeword corresponding to symbols 12 to 15 in the same symbol subset, and the RS codeword corresponding to symbols 0 to 7 may be the same as the RS codeword corresponding to symbols 8 to 15 in the same symbol subset. Furthermore, the distribution of RS codewords corresponding to symbols 0 through 7 within any two symbol subsets may be consistent, and the distribution of RS codewords corresponding to symbols 8 through 15 within any two symbol subsets may be consistent. Furthermore, each symbol set is from at least 12 different RS codewords, and a maximum of four symbols within a symbol set belong to the same RS codeword, and the distribution of RS codewords within symbol set 0 is consistent with the distribution of RS codewords within symbol set 1.

Figure 48 is a schematic diagram of another embodiment of the second block interleaving. As shown in Figure 48, a total of 16 RS symbols, two RS symbols from each symbol subset, are selected and mapped to one target symbol subset to obtain a total of eight target symbol subsets. For ease of explanation, R(x, y) is defined as symbol y in symbol subset x, where x ∈ [0, 7] and y ∈ [0, 15]. To allow the 16 RS symbols in the target symbol subset to be from 16 different RS codewords, the 16 RS symbols correspond to R(0, _i0 ), R(0,i1), R(1, _i2 ), R(1, _i3 ), R(2, _i4 ), R(2, _i5 ), R(3,i6), R(3, _i7 ), R(4, _i8 ), R(4, _i9 ), and R(5, _i10 ), and R( _{5 , i11} ), R(6, _i12 ), R(6, _i13 ), R(7, _i14 ), and R(7, _i15 ) in the two symbol sets, satisfying the following cases: _i0 , _i1 , _i2 , _i3 , i4, _i5 , _i6 , _i7 , _i8 , _{i9 .} , _i10 , _i11 , _i12 , _i13 , _i14 , and _i15 are different from each other, _i0 %8, _i1 %8, _i2 %8, and _i3 %8 are different from each other, _i2 %8, _i3 %8, _i4 %8, and _i5 %8 are different from each other, _i4 %8, _i5 %8, _i6 %8, and _i7 %8 are different from each other, _i8 %8, _i9 %8, _i10 %8, and _i11 %8 are different from each other, _i10 %8, _i11 %8, _i12 %8, and _i13 %8 are different from each other, _i12 %8, _i13 %8, _i14 %8, and _i15 %8 are different from each other, _i0 %8, _i1 %8, _i8 %8, and _i9 %8 are distinct from each other, _i2 %8, _i3 %8, _i10 %8, and _i11 %8 are distinct from each other, _i4 %8, _i5 %8, _i12 %8, and _i13 %8 are distinct from each other, _i6 %8, _i7 %8, _i14 %8, and _i15 %8 are distinct from each other, and _i0 , _i1 , _i2 , _i3 , _i4 , _i5 , _i6 , i7 , _{i8 , i9 , i10} , _i11 , _i12 , _i13 , _i14 , and _i15 ∈ [0, 15]. This is equivalent to the case where the 16 RS symbols in the target symbol subset are symbols located at different positions in the eight symbol subsets, and every two RS symbols are from the same symbol subset. Furthermore, four RS symbols output from two delay lines with a delay difference of Q*C=144 from a symbol subset in the target symbol subset are located at different positions in the corresponding symbol subset. Furthermore, four RS symbols output from the same delay line of the convolutional interleaver from two symbol subsets in the target symbol subset are located at different positions in the corresponding symbol subset. Furthermore, up to two RS symbols in the target symbol subset are from the same lane data stream and are mapped to two different symbol subsets by the first block interleaving. Two corresponding symbol subsets are output from two different delay lines of the convolutional interleaver, and the delay difference corresponding to the two delay lines is greater than or equal to 2*Q*C=288 RS symbols. According to this rule, there are multiple specific mappings in which two symbol sets are interleaved into eight target symbol subsets. Tables 17 to 24 provide some specific mapping relationships. The number x in the yth row and zth column of each table indicates the number of symbols in the zth RS symbol of target symbol subset y that is included in the symbol subset.
where 0≦y<8, 0≦z<16, and 0≦x<128. Note that the above mapping is still a valid mapping when any row interleaving, any column interleaving, any column interleaving after any row interleaving, or any column interleaving before any row interleaving is performed.

According to the mapping relationship between each symbol subset and the lane data stream and the latency relationship between each symbol subset within a symbol set, it is not difficult to learn that the relationship between the target symbol subset and the lane data stream is as follows: the data of the target symbol subset comes from K1=8 different lane data streams, and the 8 lane data streams can be represented as lane data stream _j0 , lane data stream _j1 , lane data stream _j2 , lane data stream _j3 , lane data stream _j4 , lane data stream _j5 , lane data stream _j6 , and lane data stream _j7 .
, x∈[0, 7], and
represents j _x /4 rounded down to the nearest integer. Furthermore, when two RS symbols are selected from each lane data stream, the spacing distance between two RS symbols in the corresponding lane data stream is greater than or equal to a*N*K2/n, or in other words, greater than or equal to 2*544*2/32 = 68 RS symbols. Furthermore, the maximum two RS symbols are from two aligned RS symbols in two different lane data streams.

The 32 target symbol subsets obtained by block interleaving are sent to 32 inner code encoders, respectively. Each target symbol subset is used as information data for one of the inner code encodings. The inner code encoders generate redundant data to obtain 32 encoded data streams. In one possible embodiment, inner code encoding is performed using Hamming (170, 160) to obtain a 170-bit codeword, with 10 bits of redundancy added to the 160 bits of the 16 RS symbols in the target symbol subset. In another possible embodiment, inner code encoding is performed using BCH (176, 160) to obtain a 176-bit codeword, with 16 bits of redundancy added to the 160 bits of the 16 RS symbols in the target symbol subset. After data processing is performed on the inner code encoded data stream, the processed data stream is transmitted to the channel transmission medium for transmission.

By using the data interleaving and encoding scheme in this embodiment, when Hamming (170, 160) is used as the inner code, the concatenated code of KP4RS (544, 514) + Hamming (170, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.3E-3, which is close to the optimal performance of the concatenated FEC scheme. When the inner code uses BCH (176, 160), the concatenated code of KP4 RS (544, 514) + BCH (176, 160) in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 8.3E-3, which is close to the optimal performance of the concatenated FEC scheme.

Embodiment 5: The information bit length of the inner code encoding is 120 bits, and the inner code parallelism is 16.

It should be understood that in embodiments 1 to 4, if the mapping relationship between the third symbol matrix and the fourth symbol matrix in the first block interleave is changed, the RS codeword symbol distribution rule within the symbol subset will be changed, and thus the relationship between the symbol set and the target symbol subset in the second block interleave will be affected. Embodiment 5 provides a specific implementation of a new first block interleave solution and a corresponding second block interleave.

Figure 49 is a schematic diagram of another embodiment of the first block interleaving. As shown in Figure 49, the symbol in the ith row and jth column of the fourth symbol matrix is from the xth row and yth column of the third symbol matrix, where x = (j%2) * 4 + i and
(0 ≤ i < 4 and 0 ≤ j < 16) is satisfied,
teeth,
represents rounding down to the nearest integer. One row of the fourth symbol matrix is defined as one symbol subset, and the four symbol subsets obtained by interleaving are 16 consecutive RS symbols on the T=4 first data streams output by the first block interleaving. Referring to the PCS/FEC lane data stream formats shown in Figures 5 to 9, it can be learned that the symbols in each symbol subset are from eight different lane data streams, and the eight lane data streams can be represented as lane data stream _j0 , lane data stream _j1 , lane data stream _j2 , lane data stream _j3 , lane data stream _j4 , lane data stream _j5 , lane data stream _j6 , and lane data stream _j7 .
, x∈[0, 7], and
represents j _x / 4 rounded down to the nearest integer. The symbols in each symbol subset are from at least four different RS codewords.

Four first data streams are obtained by the first block processing shown in FIG. 49, and then four second data streams are obtained by convolutional interleaving shown in FIG. 45(c). Three symbol subsets _Sr (3t-6Q), Sr(3t-3Q+1), and _Sr (3t+2) in the second data streams output from delay line 0, delay line 1, and _delay line 2 of the convolutional interleaver, respectively, are defined as symbol sets, and the symbol sets include a total of 48 RS symbols. Referring to the distribution of RS codewords on the PCS/FEC lanes of various services in FIGS. 5 to 9, the first block interleaving, and the convolutional interleaving, it can be seen that each symbol subset is from at least four different RS codewords; and the RS codewords corresponding to symbols 0 to 7 are different from the RS codewords corresponding to symbols 8 to 15 in the same symbol subset. Furthermore, the distribution of RS codewords corresponding to symbols 0 through 7 within any two symbol subsets may be consistent, and the distribution of RS codewords corresponding to symbols 8 through 15 within any two symbol subsets may be consistent. Furthermore, the symbol sets are from at least 12 different RS codewords, and a maximum of four symbols in a symbol set belong to the same RS codeword.

Therefore, the block interleaving structure shown in Figure 45(d) can be used to obtain one symbol set from the second data stream, and a total of 12 RS symbols, four RS symbols from each symbol subset, are selected and mapped to one target symbol subset to obtain a total of four target symbol subsets. The four target symbol subsets are 12 consecutive RS symbols within the four target symbol subsets output by the block interleaver, respectively. This is equivalent to each block interleaver outputting S = 4 target symbol subsets. For ease of explanation, R(x, y) is defined as symbol y in symbol subset x, where x ∈ [0, 2] and y ∈ [0, 15]. To allow the 12 RS symbols in the target symbol subset to be from 12 different RS codewords, the 12 RS symbols correspond to R(0,i0), R(0, _i1 ), R(0, _i2 ), R(0, _i3 ), R(1, _i4 ), R(1, _i5 ), R(1, _i6 ), R(1, _i7 ), R(2, _i8 ), R(2, _i9 ), R(2, _i10 ), and R(2, _i11 ) in the symbol set, satisfying the following cases: _i0 , _i1 , _i4 , _i5 , _i8 , _{and i9} are different from each other; _i2 , _i3 , _i6 , _i7 , _i10 , and _i11 are different from each other; and _i0 , _i1 , _i4 , _i5 , _i8 are different from each other. , and _i9 ∈ [0, 7], and _i2 , _i3 , _i6 , _i7 , _i10 , and _i11 ∈ [8, 15]. This is equivalent to the case where the 12 RS symbols in the target symbol subset are symbols in different positions within three symbol subsets; every fourth symbol is from the same symbol subset, two of which are from symbol 0 to symbol 7 in the same symbol subset, and the other two are from symbol 8 to symbol 15 in the same symbol subset. Furthermore, the eight RS symbols output from the two delay lines with a delay difference of Q*d = 176 in the target symbol subset are located in different positions in the corresponding symbol subset. Furthermore, a maximum of two RS symbols in the target symbol subset are from the same lane data stream and are mapped to two different symbol subsets by the first block interleaving. The two corresponding symbol subsets are output from two different delay lines of the two convolutional interleavers, and the delay difference corresponding to the two delay lines is greater than or equal to 136 RS symbols. According to this rule, there are multiple specific mappings from symbol sets to target symbol subsets. Tables 25 to 28 provide some specific mapping relationships. The number x in the y-th row and z-th column of Tables 25 to 28 indicates that the z-th RS symbol in target symbol subset y is included in symbol subset y.
represents that x% in are from the 16th RS symbol, and 0≦y<4, 0≦z<12, and 0≦x<48. Note that the above mapping is still a valid mapping when switching between any rows, switching between any columns, switching between any columns after switching between any rows, or switching between any columns before switching between any rows is performed.

Based on the mapping relationship between each symbol subset and the lane data stream and the latency relationship between each symbol subset within a symbol set, it is not difficult to learn that the relationship between the target symbol subset and the lane data stream is as follows: the data of the target symbol subset comes from K1 = 8 different lane data streams, and the 8 lane data streams can be represented as lane data stream _j0 , lane data stream _j1 , lane data stream _j2 , lane data stream _j3 , lane data stream _j4 , lane data stream _j5 , lane data stream _j6 , and lane data stream _j7 .
, x∈[0, 7], and
represents j _x /4 rounded down to the nearest integer. Also, one RS symbol is selected from four lane data streams, and two RS symbols are selected from the remaining four lane data streams. Furthermore, when two RS symbols are selected from a lane data stream, the spacing distance between the two RS symbols in the corresponding lane data stream is greater than a*N*K2/n, or in other words, greater than or equal to 2*544*2/32 = 68 RS symbols. Furthermore, the maximum two RS symbols are from two aligned RS symbols in two different lane data streams.

The 16 target data streams obtained by block interleaving are sent separately to an inner code encoder. Each target symbol subset is used as one piece of information data for inner code encoding. To obtain the 16 encoded data streams, the inner code encoder generates redundant data. In one possible embodiment, inner code encoding is performed using Hamming (128, 120) to obtain 128-bit code words, with 8 bits of redundancy added to the 120 bits of the 12 RS symbols in each target symbol subset in the target data stream. In another possible embodiment, inner code encoding is performed using BCH (136, 120) to obtain 136-bit code words, with 16 bits of redundancy added to the 120 bits of the 12 RS symbols in each target symbol subset in the target data stream.

After data processing is performed on the inner-code encoded data stream, the processed data stream is sent to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, polarization distribution, DSP framing, etc. For example, the inner-code encoded data stream may be interleaved to improve the system's ability to tolerate burst errors.

By using the data interleaving and encoding scheme of this embodiment, the concatenated KP4 RS (544, 514) + Hamming (128, 120) code in the scheme is in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.5E-3, which is close to the optimal performance of the concatenated FEC scheme.

50(a) is a schematic diagram of another structure of a data processing device according to an embodiment of the present application. As shown in FIG. 50(a), the data processing device includes an interleaving module 301 and an encoder 302. The interleaving module 301 is configured to perform an operation of performing interleaving on n lane data streams to obtain m target data streams in the aforementioned data processing method. The encoder 302 is configured to perform an operation of performing second FEC encoding separately on the m target data streams to obtain encoded data streams in the aforementioned data processing method. Specifically, the interleaving module 301 includes a convolutional interleaver 3011 and a block interleaver 3012. The convolutional interleaver 3011 is configured to perform step 3401 of the embodiment shown in FIG. 34, and the block interleaver 3012 is configured to perform step 3402 of the embodiment shown in FIG. 34.

Figure 50(b) is a schematic diagram of another structure of a data processing device according to an embodiment of the present application. As shown in Figure 50(b), the data processing device includes an interleaving module 401 and an encoder 402. The interleaving module 401 is configured to perform an operation of performing interleaving on n lane data streams to obtain m target data streams in the aforementioned data processing method. The encoder 402 is configured to perform an operation of performing second FEC encoding separately on the m target data streams to obtain encoded data streams in the aforementioned data processing method. Specifically, the interleaving module 401 includes a first block interleaver 4011, a convolutional interleaver 4012, and a second block interleaver 4013. The first block interleaver 4011 is configured to perform step 4201 in the embodiment shown in FIG. 42, the convolutional interleaver 4012 is configured to perform step 4202 in the embodiment shown in FIG. 42, and the second block interleaver 4013 is configured to perform step 4203 in the embodiment shown in FIG. 42.

It should be understood that the devices provided in this application may alternatively be implemented in other ways. For example, the unit divisions of the devices described above are merely logical functional divisions, and other divisions may be used in actual implementations. For example, multiple units or components may be combined or integrated into another system. In addition, functional units in the embodiments of this application may be integrated into a single processing unit, or may be separate physical units, or two or more functional units may be integrated into a single processing unit. Integrated units may be implemented in the form of hardware or software functional units.

Please note that in addition to the data processing method described in the above embodiment, the present application also provides another data processing method, which will be described in detail below.

Figure 51 is a schematic flowchart of a data processing method according to an embodiment of the present application.

5101: Perform block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams, so as to obtain a total of m first data streams.

In this embodiment, the lane data stream may be a PCS lane data stream or an FEC lane data stream. This is not specifically limited herein. All n lane data streams are data streams obtained by the first FEC encoding, i.e., the aforementioned outer code-encoded data streams, where n is an integer greater than 1. For example, an RS code may be used in the outer code encoding, and the n outer code-encoded data streams may include multiple RS codewords. In actual applications, other encoding methods may be used to perform the outer code encoding. For ease of explanation, hereinafter, an RS codeword is used to represent a codeword generated by the outer code encoding. It should be understood that every a codeword obtained by the outer code encoding is distributed among b lane data streams, where a≦b≦n, n may be exactly divisible by b, and a is an integer greater than or equal to 1. In different application scenarios shown in FIGS. 5 to 9, the values of a and b may also be different. The application scenario shown in Figure 5 is used as an example, where n = 32, a = 2, and b = 16; in other words, every second codeword is distributed across 16 lane data streams. The values of a and b in the application scenarios of Figures 6 to 9 can be estimated with reference to the accompanying drawings, and will not be described in detail again herein. Note that in this application, the code length of the outer code is measured in symbols, and a symbol may contain one or more bits. For example, the outer code used is the KP4 RS (544, 514) code, with a code length of N = 544 symbols and one symbol containing 10 bits.

Specifically, the n lane data streams can be divided into q groups, each group containing t lane data streams, where q is an integer greater than or equal to 1, and n can be divided exactly by q. Correspondingly, the m first data streams obtained by block interleaving can also be divided into q groups, each group containing s first data streams. That is, n = q * t and m = q * s. After block interleaving is performed on the t lane data streams in each group, a corresponding group of s first data streams is obtained.

Figure 52 is a schematic diagram of a structure in which block interleaving is performed on n lane data streams according to an embodiment of the present application. As shown in Figure 52, in the example, q block interleavers perform block interleaving on n lane data streams, and interleaver i obtains first data stream [(i+1)*s-1] from first data stream i*s by block interleaving on lane data stream i*t to lane data stream [(i+1)*t-1], where 0≦i<q.

Every a consecutive symbol in each lane data stream is from a different codeword, and all L1 consecutive symbols in each lane data stream are from at least different codewords, where L1 = N*a/b, and N represents the codeword length obtained by performing outer code encoding. In this case, t lane data streams in any group are used as an example. First, consecutive symbols are selected from each lane data stream to obtain a total of t*a symbols, and then any Δ bits are selected from each t*a symbols to obtain a total of D = Δ*t*a bits. The D bits are mapped to D consecutive bits in any first data stream obtained by block interleaving. Δ = M/s, where M represents the number of bits contained in one symbol. For ease of explanation, M = 10 is used as an example for explanation below.

Note that all d consecutive symbols in each first data stream obtained from block interleaving are from v different codewords, and all L2 consecutive symbols in each first data stream are from at least v different codewords, where v can be exactly divided by a, and d = D/M and L2 = t/s * L1.

In a possible embodiment, when the transmitting device 01 transmits 1*800GE services, in accordance with the "Ethernet Technology Consortium 800G Specification" defined by the Ethernet Technology Consortium, the RS-FEC of the transmitting device 01 uses a KP4 RS (544, 514) code, referred to as the outer code, and multiple RSs are assigned to 32 virtual PCS lanes. Specifically, as shown in FIG. 5, all 68 consecutive symbols in each of PCS lane data streams 0 to 15 or PCS lane data streams 16 to 31 form a total of 16*68 = 1088 symbols, including two RS codewords. a = 2 adjacent symbols in each PCS lane data stream are from different RS codewords, two symbols in the same position in two adjacent PCS lane data streams are from different RS codewords, and all L1 = 68 consecutive symbols are from at least a = 2 different RS codewords. The 32 PCS lane data streams are multiplexed and then transmitted to the transmitting processing module via the lane attached unit interface (AUI). Note that the 1088 symbols of the two RS codewords are distributed across the 16 lane data streams, with 68 of the 1088 symbols being 68 consecutive symbols within one lane data stream. If the L1 = 68 consecutive symbols within one lane data stream are, for example, from the two dashed boxes in Figure 5, then the 68 symbols are from three or four different RS codewords. For simplicity, the following description will simply express the above case as: all consecutive L1 symbols within each lane data stream are from different codewords.

Based on the data processing schematic diagram of the transmit processing module shown in Figure 3(h), the PMA unit of the transmit processing module recovers the 32 PCS lane data streams by performing demultiplexing on the lane attachment unit interface (AUI). Then, alignment marker lock is performed on the lane data streams using the known alignment markers of the PCS lanes. The known alignment markers of the 32 lanes are different (see the Ethernet Technology Consortium 800G Specification). Next, lane reordering is performed on the n = 32 PCS lane data streams based on the alignment markers, so that the data of the n = 32 PCS lanes can be arranged in a specified sequence. Specifically, a total of 16 lane data streams, 2*i (0 ≤ i < 16) , are from the same RS codeword, and a total of 16 lane data streams (lane data stream (2*i + 1) (0 ≤ i < 16)) are from the same RS codeword.

In another possible embodiment, when the transmitting device 01 transmits a 1*800GE service, based on the schematic diagram of data processing of the transmitting-side processing module shown in FIG. 3(h), the PMA unit of the transmitting-side processing module performs demultiplexing on the data received via the lane attachment unit interface AUI to recover 32 PCS lane data streams. Then, alignment marker lock is performed on the lane data streams by using the known alignment markers of the PCS lanes. The known alignment markers of the 32 lanes are different (see the "Ethernet Technology Consortium 800G Specification"). The transmitting-side processing module then performs lane reordering on the data of the n=32 lanes based on the alignment markers, so that the n=32 lane data streams can be arranged in a specified sequence. In a specific arrangement, a total of 16 lane data streams, lane data streams 0 to 15, are derived from the same RS codeword, and a total of 16 lane data streams, lane data streams 16 to 31, are derived from the same RS codeword. Note that the above phrase " a total of 16 lane data streams, lane data streams 0 to 15, are derived from the same RS codeword" can be understood with reference to Figure 5. More specifically, 34 symbols in each of lane data streams 0 to 15 , a total of 544 symbols, are derived from the same RS codeword; and 68 consecutive symbols in each of lane data streams 0 to 15 , a total of 1088 symbols, are derived from two RS codewords. Similarly, 34 symbols in each of lane data streams 16 to 31 , a total of 544 symbols, are derived from the same RS codeword; and 68 consecutive symbols in each of lane data streams 16 to 31 , a total of 1088 symbols, are derived from the other two RS codewords. For simplicity of explanation, this application will simply express the above case as follows: out of the 32 lane data streams, lane data stream 0 to lane data stream 15 , a total of 16 lane data streams are from the same codeword; out of the 32 lane data streams, lane data stream 16 to lane data stream 31 , a total of 16 lane data streams are from the same codeword; and lane data stream 0 to lane data stream 15 and lane data stream 16 to lane data stream 31 are from different codewords.

Below, we describe several specific implementations of block interleaving.

Embodiment 1: where n=32 is used as an example, 16 lane data streams in odd-numbered lanes of the 32 lane data streams are from the same codeword, and 16 lane data streams in even-numbered lanes of the 32 lane data streams are from the same codeword, and the data streams in odd-numbered lanes and the data streams in even-numbered lanes are from different codewords, i.e., stream 2*i , a total of 16 lane data streams are from the same codeword, and stream (2*i+1) , a total of 16 lane data streams are from the same codeword, and 0≦i<16.

Figure 53 is a schematic diagram of an application scenario of block interleaving according to an embodiment of the present application. One block interleaver shown in Figure 53 is used to perform block interleaving on two lane data streams to obtain one first data stream. A total of 16 block interleavers shown in Figure 53 need to be used for block interleaving. Specifically, block interleaver i performs block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain one first data stream, and a total of m=16 first data streams are obtained, where 0≦i<16. The specific mapping manner in block interleaving is as follows: a total of four symbols, a=2 symbols from each of lane data stream 2*i and lane data stream (2*i+1) , are selected and then mapped to D=40 consecutive bits, i.e., d=4 symbols, in the first data stream i in an arbitrary sequence. In one first data stream obtained by block interleaving, every d = 4 consecutive symbols are from v = 4 different code words, and every L2 = 136 consecutive symbols are from v = 4 different code words.

In one mode, 20 consecutive bits in each of lane data stream 2*i and lane data stream (2*i+1) are output by polling based on β bits to obtain d=4 consecutive symbols in the first data stream. Specifically, if D=40 consecutive bits in the first data stream obtained by one block interleaving operation are represented as b0 to b39, the mapping of the output by polling based on β bits can be expressed as follows: the jth bit in the 40 consecutive bits in the first data stream is the jth bit.
) lane data stream in 20 consecutive bits (
), where β may be a divisor of 20, i.e., β=1, 2, 4, 5, 10, or 20;
denotes truncation, and 0≦j<40.

Figure 54 is a schematic diagram of a specific embodiment of block interleaving according to an embodiment of the present application. The example (a) of Figure 54 represents an embodiment of block interleaving corresponding to the case where β = 10. The example (b) of Figure 54 represents an embodiment of block interleaving corresponding to the case where β = 20. The example (c) of Figure 54 represents an embodiment of block interleaving corresponding to the case where β = 1.

Embodiment 2: where n=32 is used as an example, 16 lane data streams in odd-numbered lanes among the 32 lane data streams are from the same codeword, and 16 lane data streams in even-numbered lanes among the 32 lane data streams are from the same codeword, and the data streams in odd-numbered lanes and the data streams in even-numbered lanes are from different codewords, i.e., stream 2*i , a total of 16 lane data streams are from the same codeword, and stream (2*i+1) , a total of 16 lane data streams are from the same codeword, and 0≦i<16.

Figure 55 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application. One block interleaver shown in Figure 55 is used to perform block interleaving on two lane data streams to obtain two first data streams. A total of 16 block interleavers shown in Figure 55 need to be used for block interleaving. Specifically, block interleaver i performs block interleaving on the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain the (2*i)th first data stream and the (2*i+1)th first data stream, where 0≦i<16. The specific mapping manner of block interleaving is as follows: a = 2 consecutive symbols , a total of 4 symbols, are obtained from each of lane data stream 2*i and lane data stream (2*i+1), and D = 20 bits , a total of Δ = M/s = 10/2 = 5 bits, from each symbol are selected and mapped to D = 20 consecutive bits, i.e., d = 2 symbols, in the first data stream 2*i or the second data stream (2*i+1) in an arbitrary sequence. After block interleaving, all D = 20 consecutive bits in the first data stream are from v = 4 different codewords, and further, all L2 = 68 symbols in each first data stream are from 4 different codewords.

FIG. 56 is a schematic diagram of some specific embodiments of block interleaving according to embodiments of the present application.
represents the f-th bit of the 20 consecutive bits of the first data stream (2*i+g) generated by one block interleaving operation performed by block interleaver i. The example in (a) of Figure 56 is
The first (
) among the consecutive 20 bits in the lane data stream
) bits, where 0≦f<20 and 0≦g<2. The example in Figure 56(b) shows that
The first (
) among the consecutive 20 bits in the lane data stream
) bits, indicating that 0≦f<20 and 0≦g<2.

Embodiment 3: where n=32 is used as an example, 16 lane data streams in odd-numbered lanes of the 32 lane data streams are from the same codeword, and 16 lane data streams in even-numbered lanes of the 32 lane data streams are from the same codeword, and the data streams in odd-numbered lanes and the data streams in even-numbered lanes are from different codewords, i.e., stream 2*i , a total of 16 lane data streams are from the same codeword, and stream (2*i+1) , a total of 16 lane data streams are from the same codeword, and 0≦i<16.

FIG. 57 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application. In this application scenario, block interleaving is specifically implemented in a multiplexing form. One multiplexer shown in FIG. 57 is configured to multiplex two lane data streams to obtain one first data stream. A total of 16 multiplexers shown in FIG. 57 need to be used for multiplexing. Specifically, multiplexer i multiplexes the (2*i)th lane data stream and the (2*i+1)th lane data stream to obtain one first data stream, where 0≦i<16. A specific mapping manner of multiplexing is as follows:
represents the j-th group of β consecutive bits in the (2*i)-th lane data stream,
represents the jth group of β consecutive bits in the (2*i+1)th lane data stream, j≧0;
and
are consecutive in the first data stream obtained by multiplexing. That is, after 2:1 multiplexing, the data sequence of the first data stream is
where 0≦i≦15 and β=1, 2, 4, 5, 10, or 20. For example, when β=1, it indicates that the first data stream i is obtained by using bit-mux on the (2*i)th lane data stream and the (2*i+1)th lane data stream. As another example, when β=10, it indicates that the first data stream i is obtained by using RS symbol-mux on the (2*i)th lane data stream and the (2*i+1)th lane data stream. As another example, when β=20, it indicates that the first data stream i is obtained by using 2RS symbol-mux on the (2*i)th lane data stream and the (2*i+1)th lane data stream. After 2:1 multiplexing, all d=4 consecutive symbols in the first data stream are from four different RS codewords.

Embodiment 4: n=32 is used as an example. Of the 32 lane data streams , a total of 16 lane data streams, namely lane data stream 0 to lane data stream 15, are from the same codeword, and of the 32 lane data streams, a total of 16 lane data streams, namely lane data stream 16 to lane data stream 31, are from the same codeword, and lane data stream 0 to lane data stream 15 and lane data stream 16 to lane data stream 31 are from different codewords.

Figure 58 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application. One block interleaver shown in Figure 58 is used to perform block interleaving on two lane data streams to obtain one first data stream. A total of 16 block interleavers shown in Figure 58 need to be used for block interleaving. Specifically, block interleaver i performs block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, and a total of m=16 first data streams are obtained, where 0≦i<16. The specific mapping manner in block interleaving is as follows: a total of four symbols, a=2 symbols from each of lane data stream i and lane data stream (i+16), are selected and then mapped to D=40 consecutive bits, i.e., d=4 symbols, in the first data stream i in an arbitrary sequence. In one first data stream obtained by block interleaving, every d = 4 consecutive symbols are from v = 4 different code words, and every L2 = 136 consecutive symbols are from v = 4 different code words.

In one mode, two consecutive symbols in each of lane data stream i and lane data stream (i+16) are output by polling based on β bits to obtain d=4 consecutive symbols in the first data stream. Specifically, in the first data stream obtained by one block interleaving operation, consecutive bits of D=40 bits are represented as b0 to b39. In this case, the mapping of the output by polling based on β bits can be expressed as follows: the jth bit of the 40 consecutive bits in the first data stream is represented as b0 to b39.
) within 20 consecutive bits in the lane data stream (
) bit,
represents truncation, 0≦j<40, and β is 1, 2, 4, 5, 10, or 20.

Embodiment 5: n=32 is used as an example. Of the 32 lane data streams, lane data stream 0 to lane data stream 15 are from the same codeword, for a total of 16 lane data streams , and of the 32 lane data streams, lane data stream 16 to lane data stream 31 are from the same codeword, for a total of 16 lane data streams , and lane data stream 0 to lane data stream 15 and lane data stream 16 to lane data stream 31 are from different codewords.

Figure 59 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application. One block interleaver shown in Figure 59 is used to perform block interleaving on two lane data streams to obtain two first data streams. A total of 16 block interleavers shown in Figure 59 need to be used for block interleaving. Specifically, block interleaver i performs block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain the (2*i)th first data stream and the (2*i+1)th first data stream, where 0≦i<16. The specific mapping manner of block interleaving is as follows: a = 2 RS symbols from each of lane data stream i and lane data stream (i+16) , a total of four RS symbols, are selected, and a total of D = 20 bits from each symbol, with arbitrary Δ = M/s = 10/2 = 5 bits of data, are selected and mapped to D = 20 consecutive bits, i.e., d = 2 symbols, in an arbitrary sequence in first data stream 2*i or second data stream (2*i+1). After block interleaving, all D = 20 consecutive bits in the first data stream are from v = 4 different codewords, and further, all L2 = 68 symbols in each first data stream are from 4 different codewords.

In a possible embodiment,
represents the fth bit of 20 consecutive bits in the first data stream (2*i+g) generated by the block interleaving operation performed by block interleaver i.
is the (
) lane data stream in 20 consecutive bits (
) bits, where 0≦f<20 and 0≦g<2.

In a possible embodiment,
denotes the fth bit of 20 consecutive bits of the first data stream (2*i+g) generated by the block interleaving operation performed by block interleaver i.
is the (
) lane data stream in 20 consecutive bits (
) bits, where 0≦f<20 and 0≦g<2.

Embodiment 6: n=32 is used as an example. Of the 32 lane data streams, lane data stream 0 to lane data stream 15 are from the same codeword, for a total of 16 lane data streams , and of the 32 lane data streams, lane data stream 16 to lane data stream 31 are from the same codeword, for a total of 16 lane data streams , and lane data stream 0 to lane data stream 15 and lane data stream 16 to lane data stream 31 are from different codewords.

FIG. 60 is a schematic diagram of another application scenario of block interleaving according to an embodiment of the present application. In this application scenario, block interleaving is specifically implemented in a multiplexing form. One multiplexer shown in FIG. 60 is configured to multiplex two lane data streams to obtain one first data stream. A total of 16 multiplexers shown in FIG. 60 need to be used for multiplexing. Specifically, multiplexer i multiplexes the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16. A specific mapping manner of multiplexing is as follows:
represents the jth group of β consecutive bits in the ith lane data stream,
represents the jth group of β consecutive bits in the (i+16)th lane data stream, j≧0;
and
are consecutive in the first data stream obtained by multiplexing. That is, after 2:1 multiplexing, the data sequence of the first data stream is
where 0≦i≦15 and β=1, 2, 4, 5, 10, or 20. For example, when β=1, this indicates that the first data stream i is obtained by using bit-mux on the ith lane data stream and the (i+16)th lane data stream. In another example, when β=10, this indicates that the first data stream i is obtained by using RS symbol-mux on the ith lane data stream and the (i+16)th lane data stream. In yet another example, when β=20, this indicates that the first data stream i is obtained by using 2RS symbol-mux on the ith lane data stream and the (i+16)th lane data stream. After 2:1 multiplexing, all d=4 consecutive symbols in the first data stream are from four different RS codewords.

Multiplexer i multiplexes the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream. In other words, the two input data streams of multiplexer i are the ith lane data stream and the (i+16)th lane data stream. Note that multiplexing may alternatively be implemented in another specific manner. In a specific embodiment, multiplexer i multiplexes the ith lane data stream and the (31-i)th lane data stream to obtain one first data stream. Note that any two input data streams of a multiplexer are applicable as long as the two input data streams satisfy the following constraints: one input data stream is from one of lane data streams 0 to 15, and the other input data stream is from one of lane data streams 16 to 31. This specific embodiment can be simply expanded based on the above-described embodiment. Those skilled in the art will be familiar with this specific embodiment, and the details will not be described again in this specification.

Embodiment 7: n=32 is used as an example. Of the 32 lane data streams, lane data stream 0 to lane data stream 15 , a total of 16 lane data streams , are from the same codeword, and of the 32 lane data streams, lane data stream 16 to lane data stream 31 , a total of 16 lane data streams are from the same codeword, and lane data streams 0 to lane data stream 15 and lane data streams 16 to lane data stream 31 are from different codewords. More specifically, referring to FIG. 5 for understanding, 34 symbols in each of lane data streams 0 to 15 , a total of 544 symbols , are from the same RS codeword; and 68 consecutive symbols in each of lane data streams 0 to 15 , a total of 1088 symbols , are from two RS codewords. Similarly, 34 symbols in each of lane data streams 16 to 31 , for a total of 544 symbols, are from the same RS codeword; and 68 consecutive symbols in each of lane data streams 16 to 31 , for a total of 1088 symbols , are from the other two RS codewords.

FIG. 61 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. One block interleaver shown in FIG. 61 is used to perform block interleaving on four lane data streams to obtain one first data stream. A total of eight block interleavers shown in FIG. 61 need to be used for block interleaving. In the four lane data streams, two lane data streams are from two lane data streams, lane data stream 0 to lane data stream 15, and the other two lane data streams are from two lane data streams, lane data stream 16 to lane data stream 31. The block interleaver selects a = 2 consecutive symbols from each of the four lane data streams , a total of eight symbols , and then maps the eight symbols to D = 80 consecutive bits, i.e., d = 8 symbols, in the first data stream. In the first data stream obtained by block interleaving, every d = 8 consecutive symbols are from at least v = 4 different codewords, and every L = 272 consecutive symbols are from at least v = 4 different codewords. Furthermore, in the first data stream obtained by block interleaving, every four consecutive symbols in every d = 8 consecutive symbols are from four different RS codewords, specifically, every eight consecutive symbols from the 0th symbol to the 3rd symbol are from different RS codewords, and every eight consecutive symbols from the 4th symbol to the 7th symbol are from different RS codewords. A specific embodiment is where block interleaver i performs block interleaving on the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17)th lane data stream to obtain one first data stream, resulting in a total of m=8 first data streams, where 0≦i≦7.

A specific interleaving scheme for block interleaving is that a = 2 consecutive symbols (0≦i<8) from each of the (2*i)th lane data stream, the (2*i+1)th lane data stream, the (2*i+16)th lane data stream, and the (2*i+17) th lane data stream are selected, and then interleaved into D = 80 consecutive bits, or d = 8 symbols, in the first data stream i. In a specific embodiment, of the eight consecutive symbols in the first data stream i, the 0th and 1st symbols are from the (2*i)th lane data stream, the 2nd and 3rd symbols are from the (2*i+16)th lane data stream, the 4th and 5th symbols are from the (2*i+1)th lane data stream, and the 6th and 7th symbols are from the (2*i+17)th lane data stream.

Figure 62 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. Block interleaving may alternatively be implemented by using symbol-mux, as shown in Figure 62;
represents two consecutive symbols in the j-th group in the (2*i)-th lane data stream,
represents two consecutive symbols in the j-th group in the (2*i+16)-th lane data stream,
represents two consecutive symbols in the j-th group in the (2*i+1)-th lane data stream,
represents two consecutive symbols in the j-th group in the (2*i+17)-th lane data stream, j≧0;
and
It should be noted that is continuous in the first data stream obtained by multiplexing. That is, the data sequence of the first data stream i after 4:1 symbol multiplexing is
and 0≦i≦7.

Note that 4:1 symbol multiplexing can alternatively be implemented by using multi-level symbol multiplexing. For example, first, the (2*i)-th lane data stream and the (2*i+16)-th lane data stream are multiplexed to obtain a first multiplexed data stream, and 2:1 symbol multiplexing is performed on the (2*i+1)-th lane data stream and the (2*i+17)-th lane data stream to obtain a second multiplexed data stream; then, 2:1 symbol multiplexing is performed on the first multiplexed data stream and the first multiplexed data stream to obtain a first data stream i.

Embodiment 8: Based on embodiment 7, embodiment 8 provides another specific embodiment of block interleaving.

A total of eight consecutive a = 2 symbols (0≦i<8) from each of the (2*i) th , (2*i+1)th, (2*i+16)th, and (2*i+17)th lane data streams are selected and then interleaved into D = 80 consecutive bits, or d = 8 symbols, in the first data stream i. In some specific application scenarios, the alignment of lane data is performed based on two RS symbols. In this case, the 0th symbol in the two consecutive symbols obtained from the (2*i)th lane data stream and the 0th symbol in the two consecutive symbols obtained from the (2*i+1)th lane data stream are from different RS codewords. The first symbol in two consecutive symbols obtained from the (2*i)th lane data stream and the first symbol in two consecutive symbols obtained from the (2*i+1)th lane data stream are from different RS codewords. The 0th symbol in two consecutive symbols obtained from the (2*i+16)th lane data stream and the 0th symbol in two consecutive symbols obtained from the (2*i+17)th lane data stream are from different RS codewords. The first symbol in two consecutive symbols obtained from the (2*i+16)th lane data stream and the first symbol in two consecutive symbols obtained from the (2*i+17)th lane data stream are from different RS codewords.

Figure 63 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. Referring to the aforementioned features, another specific implementation of block interleaving is as shown in the example shown in (a) of Figure 63. In eight consecutive symbols in the first data stream i, the 0th and 4th symbols are from the (2*i)th lane data stream, the 1st and 5th symbols are from the (2*i+16)th lane data stream, the 2nd and 6th symbols are from the (2*i+1)th lane data stream, and the 3rd and 7th symbols are from the (2*i+17)th lane data stream. Note that the above implementation is equivalent to the following: one symbol is taken from each of the four lane data streams, and interleaving is performed to obtain four consecutive symbols in data stream i, where, in the four consecutive symbols in the first data stream i, the 0th symbol is from the (2*i)th lane data stream, the 1st symbol is from the (2*i+16)th lane data stream, the 2nd symbol is from the (2*i+1)th lane data stream, and the 3rd symbol is from the (2*i+17)th lane data stream.

Another specific implementation of block interleaving is shown in the example in Figure 63(b). In eight consecutive symbols in the first data stream i, the 0th and 4th symbols are from the (2*i)th lane data stream, the 1st and 5th symbols are from the (2*i+1)th lane data stream, the 2nd and 6th symbols are from the (2*i+16)th lane data stream, and the 3rd and 7th symbols are from the (2*i+17)th lane data stream. Note that the above implementation is equivalent to the following: one symbol is taken from each of the four lane data streams, and interleaving is performed to obtain four consecutive symbols in data stream i, where, in the four consecutive symbols in the first data stream i, the 0th symbol is from the (2*i)th lane data stream, the 1st symbol is from the (2*i+1)th lane data stream, the 2nd symbol is from the (2*i+16)th lane data stream, and the 3rd symbol is from the (2*i+17)th lane data stream.

It should be noted that block interleaving can alternatively be implemented by using symbol-mux, in which one symbol is taken from each of the four lane data streams,
represents the j-th symbol in the (2*i)-th lane data stream,
represents the j-th symbol in the (2*i+16)-th lane data stream,
represents the j-th symbol in the (2*i+1)-th lane data stream,
represents the j-th symbol in the (2*i+17)-th lane data stream, j≧0;
, and
are consecutive in the first data stream obtained by 4:1 symbol multiplexing. That is, the data sequence of the first data stream i after 4:1 symbol multiplexing is
and 0≦i<7.
, and
are from four different RS code words. Another specific symbol multiplexing is where one symbol is taken from each of the four lane data streams, and in the first data stream obtained by 4:1 symbol multiplexing,
, and
That is, the data sequence of the first data stream i after 4:1 symbol multiplexing is
and 0≦i<7.

Embodiment 9: where n=32 is used as an example, 16 lane data streams in odd-numbered lanes of the 32 lane data streams are from the same codeword, and 16 lane data streams in even-numbered lanes of the 32 lane data streams are from the same codeword, and the data streams in odd-numbered lanes and the data streams in even-numbered lanes are from different codewords, i.e., stream 2*i , a total of 16 lane data streams are from the same codeword, and stream (2*i+1) , a total of 16 lane data streams are from the same codeword, and 0≦i<16.

Figure 64 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. One block interleaver shown in Figure 64 is used to perform block interleaving on four lane data streams to obtain one first data stream. A total of eight block interleavers shown in Figure 64 need to be used for block interleaving. In the four lane data streams, two lane data streams are from the two odd-numbered lane data streams from lane data stream 0 to lane data stream 31, and the other two lane data streams are from the two even-numbered lane data streams from lane data stream 0 to lane data stream 31. The block interleaver selects a = 2 consecutive symbols , a total of eight symbols, from each of the four lane data streams, and then maps the eight symbols to D = 80 consecutive bits, i.e., d = 8 symbols, in the first data stream. In a first data stream obtained by block interleaving, all d = 8 consecutive symbols are from at least v = 4 different codewords, and all L = 272 consecutive symbols are from at least v = 4 different codewords. Furthermore, in a first data stream obtained by block interleaving, all four consecutive symbols in all d = 8 consecutive symbols are from four different RS codewords, specifically, all eight consecutive symbols from the 0th symbol to the 3rd symbol are from different RS codewords, and all eight consecutive symbols from the 4th symbol to the 7th symbol are from different RS codewords. A specific embodiment is where block interleaver i performs block interleaving on the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream to obtain one first data stream, resulting in a total of m=8 first data streams, where 0≦i≦7.

A specific interleaving scheme for block interleaving is that a = 2 consecutive symbols (0 < i < 8) from each of the 4*i lane data stream, the (4*i+1) lane data stream, the (4*i+2) lane data stream, and the (4*i+3) lane data stream are selected, for a total of eight symbols , and then interleaved into D = 80 consecutive bits, or d = 8 symbols, in the first data stream i. In a specific embodiment, of the eight consecutive symbols in the first data stream i, the 0th and 1st symbols are from the (4*i) lane data stream, the 2nd and 3rd symbols are from the (4*i+1) lane data stream, the 4th and 5th symbols are from the (4*i+2) lane data stream, and the 6th and 7th symbols are from the (4*i+3) lane data stream.

Figure 65 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. Block interleaving may alternatively be implemented by using symbol-mux as shown in Figure 65, where
represents two consecutive symbols in the j-th group in the (4*i)-th lane data stream,
represents two consecutive symbols in the j-th group in the (4*i+1)-th lane data stream,
represents two consecutive symbols in the j-th group in the (4*i+2)-th lane data stream,
represents two consecutive symbols in the j-th group in the (4*i+3)-th lane data stream, j≧0;
, and
It should be noted that the symbols i are consecutive in the first data stream obtained by multiplexing. That is, the data sequence of the first data stream i after 4:1 symbol multiplexing is
and 0≦i≦7.

Note that 4:1 symbol multiplexing can alternatively be implemented by using multi-level symbol multiplexing. For example, first, the (4*i)-th lane data stream and the (4*i+1)-th lane data stream are multiplexed to obtain a first multiplexed data stream, and 2:1 symbol multiplexing is performed on the (4*i+2)-th lane data stream and the (4*i+3)-th lane data stream to obtain a second multiplexed data stream; then, 2:1 symbol multiplexing is performed on the first multiplexed data stream and the first multiplexed data stream to obtain a first data stream i.

Embodiment 10: Based on embodiment 9, embodiment 10 provides another specific embodiment of block interleaving.

A total of eight consecutive symbols, a = 2 symbols (0≦i<8), from each of the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, and the (4*i+3)th lane data stream are selected and then interleaved into D = 80 consecutive bits, i.e., d = 8 symbols, in the first data stream i. In some specific application scenarios, the lane data alignment is performed based on two RS symbols. In this case, the 0th symbol in the two consecutive symbols obtained from the (4*i)th lane data stream and the 0th symbol in the two consecutive symbols obtained from the (4*i+2)th lane data stream are from different RS codewords. The first symbol in the two consecutive symbols obtained from the (4*i)th lane data stream and the first symbol in the two consecutive symbols obtained from the (4*i+2)th lane data stream are from different RS codewords. The 0th symbol in two consecutive symbols taken from the (4*i+1)th lane data stream and the 0th symbol in two consecutive symbols taken from the (4*i+3)th lane data stream are from different RS codewords. The first symbol in two consecutive symbols taken from the (4*i+1)th lane data stream and the first symbol in two consecutive symbols taken from the (4*i+3)th lane data stream are from different RS codewords.

Figure 66 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. Referring to the aforementioned features, another specific implementation of block interleaving is as the example shown in (a) of Figure 66. In eight consecutive symbols in the first data stream i, the 0th and 4th symbols are from the (4*i)th lane data stream, the 1st and 5th symbols are from the (4*i+1)th lane data stream, the 2nd and 6th symbols are from the (4*i+2)th lane data stream, and the 3rd and 7th symbols are from the (4*i+3)th lane data stream. Note that the above implementation is equivalent to the following: one symbol is taken from each of the four lane data streams, and interleaving is performed to obtain four consecutive symbols in data stream i, where, in the four consecutive symbols in the first data stream i, the 0th symbol is from the (4*i)th lane data stream, the 1st symbol is from the (4*i+1)th lane data stream, the 2nd symbol is from the (4*i+2)th lane data stream, and the 3rd symbol is from the (4*i+3)th lane data stream.

Another specific implementation of block interleaving is shown in the example in Figure 66(b). In eight consecutive symbols in the first data stream i, the 0th and 4th symbols are from the (4*i)th lane data stream, the 1st and 5th symbols are from the (4*i+2)th lane data stream, the 2nd and 6th symbols are from the (4*i+1)th lane data stream, and the 3rd and 7th symbols are from the (4*i+3)th lane data stream. Note that the above implementation is equivalent to the following: one symbol is taken from each of the four lane data streams, and interleaving is performed to obtain four consecutive symbols in data stream i, where, in the four consecutive symbols in the first data stream i, the 0th symbol is from the (4*i)th lane data stream, the 1st symbol is from the (4*i+2)th lane data stream, the 2nd symbol is from the (4*i+1)th lane data stream, and the 3rd symbol is from the (4*i+3)th lane data stream.

It should be noted that block interleaving can alternatively be implemented by using symbol-mux, in which one symbol is taken from each of the four lane data streams,
represents the j-th symbol in the (4*i)-th lane data stream,
represents the j-th symbol in the (4*i+1)-th lane data stream,
represents the j-th symbol in the (4*i+2)-th lane data stream,
represents the j-th symbol in the (4*i+3)-th lane data stream, j≧0;
, and
are consecutive in the first data stream obtained by 4:1 symbol multiplexing. That is, the data sequence of the first data stream i after 4:1 symbol multiplexing is
and 0≦i≦7.
, and
are from four different RS code words. Another specific symbol multiplexing is where one symbol is taken from each of the four lane data streams, and in the first data stream obtained by 4:1 symbol multiplexing,
, and
That is, the data sequence of the first data stream i after 4:1 symbol multiplexing is
and 0≦i≦7.

Note that in some specific implementation scenarios, when the transmitting device 01 transmits 1*800GE services, after PMA 4:1 multiplexing is performed, 32 PCS lane data streams are sent to the transmitting processing module via the lane attachment unit interface AUI. During PMA 4:1 multiplexing, two of the four input data streams are from two of the 0th to 15th PCS lane data streams, and the other two are from two of the 16th to 31st PCS lane data streams. In relation to the aforementioned feature that "during PMA 4:1 multiplexing, two of the four input data streams are from two of the 0th to 15th PCS lane data streams, and the remaining two are from two of the 16th to 31st PCS lane data streams," during data processing in the transmitting processing module, first, de-mux is performed to recover the 32 PCS lane data streams, and each physical lane data stream is de-multiplexed and de-muxed to obtain four PCS lane data streams, and then alignment marker lock of the lane data streams is performed by using the known alignment markers of the PCS lanes. Next, lane reordering does not need to be performed, and the block interleaving (or symbol multiplexing) of embodiment 7, embodiment 8, embodiment 9, or embodiment 10 is directly performed on the four PCS lane data streams obtained by de-muxing the physical lane data streams, and block interleaving (or symbol multiplexing) is performed on the four lane data streams to obtain one first data stream, so that eight consecutive symbols in the first data stream are from at least four RS codewords. For specific embodiments, see Figure 61, Figure 62, Figure 63, Figure 64, Figure 65, or Figure 66. Those skilled in the art will be familiar with these specific embodiments, and the details will not be described again herein.

Embodiment 11: n=32 is used as an example. Of the 32 lane data streams, lane data stream 0 to lane data stream 15 , a total of 16 lane data streams , are from the same codeword, and of the 32 lane data streams, lane data stream 16 to lane data stream 31 , a total of 16 lane data streams are from the same codeword, and lane data streams 0 to lane data stream 15 and lane data streams 16 to lane data stream 31 are from different codewords. More specifically, referring to FIG. 5 for understanding, 34 symbols in each of lane data streams 0 to 15 , a total of 544 symbols , are from the same RS codeword; and 68 consecutive symbols in each of lane data streams 0 to 15 , a total of 1088 symbols , are from two RS codewords. Similarly, 34 symbols in each of lane data streams 16 to 31 , for a total of 544 symbols, are from the same RS codeword; and 68 consecutive symbols in each of lane data streams 16 to 31 , for a total of 1088 symbols , are from the other two RS codewords.

Figure 67 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. One block interleaver shown in Figure 67 is used to perform block interleaving on eight lane data streams to obtain one first data stream. A total of four block interleavers shown in Figure 67 need to be used for block interleaving. In the eight lane data streams, four lane data streams are four from lane data stream 0 to lane data stream 15, and the other four lane data streams are four from lane data stream 16 to lane data stream 31. The block interleaver selects a = 2 consecutive symbols , a total of 16 symbols, from each of the eight lane data streams, and then maps the 16 symbols to D = 160 consecutive bits, i.e., d = 16 symbols, in the first data stream. In a first data stream obtained by block interleaving, every d = 16 consecutive symbols are from at least v = 4 different codewords, and every L2 = 544 consecutive symbols are from at least v = 4 different codewords. Furthermore, in a first data stream obtained by block interleaving, every four consecutive symbols in every d = 16 consecutive symbols are from four different RS codewords, specifically, every sixteenth consecutive symbol is from a different RS codeword from the 0th symbol to the 3rd symbol, from the 4th symbol to the 7th symbol, from the 8th symbol to the 11th symbol, and from the 12th symbol to the 15th symbol. In a specific embodiment, block interleaver i performs block interleaving on the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream to obtain one first data stream, resulting in a total of m=4 first data streams, where 0≦i≦3.

A specific interleaving manner of block interleaving is as follows: a = 2 consecutive symbols (0≦i<3), a total of 16 symbols, from each of the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream , and the (4*i+19)th lane data stream are selected and then interleaved into 16 consecutive symbols in the first data stream i. In a specific embodiment, in 16 consecutive symbols in a first data stream i, the 0th and 1st symbols are from the (4*i)th lane data stream, the 2nd and 3rd symbols are from the (4*i+16)th lane data stream, the 4th and 5th symbols are from the (4*i+1)th lane data stream, the 6th and 7th symbols are from the (4*i+17)th lane data stream, the 8th and 9th symbols are from the (4*i+2)th lane data stream, the 10th and 11th symbols are from the (4*i+18)th lane data stream, the 12th and 13th symbols are from the (4*i+3)th lane data stream, and the 14th and 15th symbols are from the (4*i+19)th lane data stream.

Figure 68 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. Block interleaving may alternatively be implemented by using symbol-mux, as shown in Figure 68;
represents two consecutive symbols in the j-th group in the (4*i)-th lane data stream,
represents two consecutive symbols in the j-th group in the (4*i+16)-th lane data stream,
represents two consecutive symbols in the j-th group in the (4*i+1)-th lane data stream,
represents two consecutive symbols in the j-th group in the (4*i+17)-th lane data stream,
represents two consecutive symbols in the j-th group in the (4*i+2)-th lane data stream,
represents two consecutive symbols in the j-th group in the (4*i+18)-th lane data stream,
represents two consecutive symbols in the j-th group in the (4*i+3)-th lane data stream,
represents two consecutive symbols in the jth group in the 4*i+19th lane data stream, j≧0;
, and
It should be noted that, are consecutive in the first data stream i obtained by multiplexing. That is, the data sequence of the first data stream i after 8:1 symbol multiplexing is
, and
and 0≦i≦3.

Note that the 8:1 symbol-mux described above can alternatively be implemented, for example, by using three-level 2:1 symbol-mux.

Embodiment 12: Based on embodiment 11, embodiment 12 provides another specific embodiment of block interleaving.

A total of 16 consecutive a=2 symbols (0≦i<3) from each of the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream , the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream are selected and then interleaved with 16 consecutive symbols in the first data stream i. In some specific application scenarios, the lane data alignment is performed based on two RS symbols. In this case, the 0th symbol in two consecutive symbols obtained from the (4*i)th lane data stream and the 0th symbol in two consecutive symbols obtained from the (4*i+1)th lane data stream are from different RS codewords, the first symbol in two consecutive symbols obtained from the (4*i)th lane data stream and the first symbol in two consecutive symbols obtained from the (4*i+1)th lane data stream are from different RS codewords, the 0th symbol in two consecutive symbols obtained from the (4*i+2)th lane data stream and the 0th symbol in two consecutive symbols obtained from the (4*i+3)th lane data stream are from different RS codewords, and the first symbol in two consecutive symbols obtained from the (4*i+2)th lane data stream and the first symbol in two consecutive symbols obtained from the (4*i+3)th lane data stream are from different RS codewords. The 0th symbol in two consecutive symbols obtained from the (4*i+16)th lane data stream and the 0th symbol in two consecutive symbols obtained from the (4*i+17)th lane data stream are from different RS codewords, and the first symbol in two consecutive symbols obtained from the (4*i+16)th lane data stream and the first symbol in two consecutive symbols obtained from the (4*i+17)th lane data stream are from different RS codewords. The 0th symbol in two consecutive symbols obtained from the (4*i+18)th lane data stream and the 0th symbol in two consecutive symbols obtained from the (4*i+19)th lane data stream are from different RS codewords, and the first symbol in two consecutive symbols obtained from the (4*i+18)th lane data stream and the first symbol in two consecutive symbols obtained from the (4*i+19)th lane data stream are from different RS codewords.

Figure 69 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. Referring to the aforementioned features, another specific implementation of block interleaving is as shown in the example in Figure 69(a). In the 16 consecutive symbols of the first data stream i, the 0th and 8th symbols are from the (4*i)th lane data stream, the 1st and 9th symbols are from the (2*i+16)th lane data stream, the 2nd and 10th symbols are from the (4*i+1)th lane data stream, the 3rd and 11th symbols are from the (4*i+17)th lane data stream, the 4th and 12th symbols are from the (4*i+2)th lane data stream, the 5th and 13th symbols are from the (4*i+18)th lane data stream, the 6th and 14th symbols are from the (4*i+3)th lane data stream, and the 7th and 15th symbols are from the (4*i+19)th lane data stream. Note that the above implementation is equivalent to the following: one symbol is obtained from each of the eight lane data streams, and interleaving is performed to obtain eight consecutive symbols in data stream i, where, in the eight consecutive symbols in the first data stream i, the 0th symbol is from the (4*i)th lane data stream, the 1st symbol is from the (4*i+16)th lane data stream, the 2nd symbol is from the (4*i+1)th lane data stream, the 3rd symbol is from the (4*i+17)th lane data stream, the 4th symbol is from the (4*i+2)th lane data stream, the 5th symbol is from the (4*i+18)th lane data stream, the 6th symbol is from the (4*i+3)th lane data stream, and the 7th symbol is from the (4*i+19)th lane data stream.

Another specific embodiment of block interleaving is shown in (b) of Figure 69. In the 16 consecutive symbols of the first data stream i, the 0th and 8th symbols are from the (4*i)th lane data stream, the 1st and 9th symbols are from the (4*i+1)th lane data stream, the 2nd and 10th symbols are from the (4*i+16)th lane data stream, the 3rd and 11th symbols are from the (4*i+17)th lane data stream, the 4th and 12th symbols are from the (4*i+2)th lane data stream, the 5th and 13th symbols are from the (4*i+3)th lane data stream, the 6th and 14th symbols are from the (4*i+18)th lane data stream, and the 7th and 15th symbols are from the (4*i+19)th lane data stream. Note that the above implementation is equivalent to the following: one symbol is obtained from each of the eight lane data streams, and interleaving is performed to obtain eight consecutive symbols in data stream i, where the 0th symbol is from the (4*i)th lane data stream, the 1st symbol is from the (4*i+1)th lane data stream, the 2nd symbol is from the (4*i+16)th lane data stream, the 3rd symbol is from the (4*i+17)th lane data stream, the 4th symbol is from the (4*i+2)th lane data stream, the 5th symbol is from the (4*i+3)th lane data stream, the 6th symbol is from the (4*i+18)th lane data stream, and the 7th symbol is from the (4*i+19)th lane data stream.

Note that block interleaving can alternatively be implemented by using symbol-mux, in which one symbol is taken from each of the eight lane data streams.
represents the j-th symbol in the (4*i)-th lane data stream,
represents the j-th symbol in the (4*i+16)-th lane data stream,
represents the j-th symbol in the (4*i+1)-th lane data stream,
represents the j-th symbol in the (4*i+17)-th lane data stream,
represents the j-th symbol in the (4*i+2)-th lane data stream,
represents the j-th symbol in the (4*i+18)-th lane data stream,
represents the j-th symbol in the (4*i+3)-th lane data stream,
represents the j-th symbol in the (4*i+19)-th lane data stream, j≧0; and
, and
are continuous in the first data stream obtained by 8:1 symbol multiplexing. That is, the data sequence of the first data stream i after 8:1 symbol multiplexing is
and 0≦i≦3.
, and
are from four different RS codewords,
, and
are from four different RS code words. Another specific symbol multiplexing is where one symbol is taken from each of the eight lane data streams, and in the first data stream obtained by 8:1 symbol multiplexing,
, and
That is, the data sequence of the first data stream i after 8:1 symbol multiplexing is
and 0≦i≦3.

Embodiment 13: Where n=32 is used as an example, 16 lane data streams in odd-numbered lanes of the 32 lane data streams are from the same codeword, and 16 lane data streams in even-numbered lanes of the 32 lane data streams are from the same codeword, and the data streams in odd-numbered lanes and the data streams in even-numbered lanes are from different codewords, i.e., stream 2*i , a total of 16 lane data streams are from the same codeword, and stream (2*i+1) , a total of 16 lane data streams are from the same codeword, and 0≦i<16.

FIG. 70 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. One block interleaver shown in FIG. 70 is used to perform block interleaving on eight lane data streams to obtain one first data stream. A total of four block interleavers shown in FIG. 70 need to be used for block interleaving. Of the eight lane data streams, four lane data streams are from the four odd-numbered lane data streams, from lane data stream 0 to lane data stream 31, and the other four lane data streams are from the four even-numbered lane data streams, from lane data stream 0 to lane data stream 31. The block interleaver selects a=2 consecutive symbols , a total of 16 symbols, from each of the eight lane data streams, and then maps the 16 symbols to D=160 consecutive bits, i.e., d=16 symbols, in the first data stream. In a first data stream obtained by block interleaving, every d = 16 consecutive symbols are from at least v = 4 different codewords, and every L2 = 544 consecutive symbols are from at least v = 4 different codewords. Furthermore, in a first data stream obtained by block interleaving, every four consecutive symbols in every d = 16 consecutive symbols are from four different RS codewords, specifically, every sixteenth consecutive symbol is from a different RS codeword from the 0th symbol to the 3rd symbol, from the 4th symbol to the 7th symbol, from the 8th symbol to the 11th symbol, and from the 12th symbol to the 15th symbol. In a specific embodiment, block interleaver i performs block interleaving on the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream to obtain one first data stream, resulting in a total of m=4 first data streams, where 0≦i≦3.

A specific interleaving manner of block interleaving is as follows: a = 2 consecutive symbols (0≦i<3), a total of 16 symbols, from each of the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream , and the (8*i+7)th lane data stream are selected and then interleaved into 16 consecutive symbols in the first data stream i. In a specific embodiment, in 16 consecutive symbols in a first data stream i, the 0th and 1st symbols are from the (8*i)th lane data stream, the 2nd and 3rd symbols are from the (8*i+1)th lane data stream, the 4th and 5th symbols are from the (8*i+2)th lane data stream, the 6th and 7th symbols are from the (8*i+3)th lane data stream, the 8th and 9th symbols are from the (8*i+4)th lane data stream, the 10th and 11th symbols are from the (8*i+5)th lane data stream, the 12th and 13th symbols are from the (8*i+6)th lane data stream, and the 14th and 15th symbols are from the (8*i+7)th lane data stream.

Figure 71 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. Block interleaving may alternatively be implemented by using symbol-mux, as shown in Figure 71;
represents two consecutive symbols in the j-th group in the (8*i)-th lane data stream,
represents two consecutive symbols in the j-th group in the (8*i+1)-th lane data stream,
represents two consecutive symbols in the j-th group in the (8*i+2)-th lane data stream,
represents two consecutive symbols in the j-th group in the (8*i+3)-th lane data stream,
represents two consecutive symbols in the j-th group in the (8*i+4)-th lane data stream,
represents two consecutive symbols in the j-th group in the (8*i+5)-th lane data stream,
represents two consecutive symbols in the j-th group in the (8*i+6)-th lane data stream,
represents two consecutive symbols in the jth group in the 8*i+7th lane data stream, j≧0;
, and
It should be noted that, are consecutive in the first data stream i obtained by multiplexing. That is, the data sequence of the first data stream i after 8:1 symbol multiplexing is
and 0≦i≦3.

Note that the 8:1 symbol-mux described above can alternatively be implemented, for example, by using three-level 2:1 symbol-mux.

Embodiment 14: Based on embodiment 13, embodiment 14 provides another specific embodiment of block interleaving.

A total of 16 consecutive symbols, a=2 symbols (0≦i<3), from each of the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream , and the (8*i+7) th lane data stream are selected and then interleaved into 16 consecutive symbols in the first data stream i. In some specific application scenarios, the alignment of the lane data is performed based on two RS symbols. In this case, the 0th symbol in two consecutive symbols obtained from the (8*i)th lane data stream and the 0th symbol in two consecutive symbols obtained from the (8*i+2)th lane data stream are from different RS codewords, the first symbol in two consecutive symbols obtained from the (8*i)th lane data stream and the first symbol in two consecutive symbols obtained from the (8*i+2)th lane data stream are from different RS codewords, the 0th symbol in two consecutive symbols obtained from the (8*i+1)th lane data stream and the 0th symbol in two consecutive symbols obtained from the (8*i+3)th lane data stream are from different RS codewords, and the first symbol in two consecutive symbols obtained from the (8*i+1)th lane data stream and the first symbol in two consecutive symbols obtained from the (8*i+3)th lane data stream are from different RS codewords. The 0th symbol in two consecutive symbols obtained from the (8*i+4)th lane data stream and the 0th symbol in two consecutive symbols obtained from the (8*i+6)th lane data stream are from different RS codewords, the first symbol in two consecutive symbols obtained from the (8*i+4)th lane data stream and the first symbol in two consecutive symbols obtained from the (8*i+6)th lane data stream are from different RS codewords, the 0th symbol in two consecutive symbols obtained from the (8*i+5)th lane data stream and the 0th symbol in two consecutive symbols obtained from the (8*i+7)th lane data stream are from different RS codewords, and the first symbol in two consecutive symbols obtained from the (8*i+5)th lane data stream and the first symbol in two consecutive symbols obtained from the (8*i+7)th lane data stream are from different RS codewords.

Figure 72 is a schematic diagram of yet another application scenario of block interleaving according to an embodiment of the present application. Referring to the aforementioned features, another specific implementation of block interleaving is as shown in the example in Figure 72(a). In the 16 consecutive symbols of the first data stream i, the 0th and 8th symbols are from the (8*i)th lane data stream, the 1st and 9th symbols are from the (8*i+1)th lane data stream, the 2nd and 10th symbols are from the (8*i+2)th lane data stream, the 3rd and 11th symbols are from the (8*i+3)th lane data stream, the 4th and 12th symbols are from the (8*i+4)th lane data stream, the 5th and 13th symbols are from the (8*i+5)th lane data stream, the 6th and 14th symbols are from the (8*i+6)th lane data stream, and the 7th and 15th symbols are from the (8*i+7)th lane data stream. Note that the above implementation is equivalent to the following: one symbol is obtained from each of the eight lane data streams, and interleaving is performed to obtain eight consecutive symbols in data stream i, where the zeroth symbol is from the (8*i)th lane data stream, the first symbol is from the (8*i+1)th lane data stream, the second symbol is from the (8*i+2)th lane data stream, the third symbol is from the (8*i+3)th lane data stream, the fourth symbol is from the (8*i+4)th lane data stream, the fifth symbol is from the (8*i+5)th lane data stream, the sixth symbol is from the (8*i+6)th lane data stream, and the seventh symbol is from the (8*i+7)th lane data stream.

Another specific embodiment of block interleaving is shown in FIG. 72(b). In the 16 consecutive symbols of the first data stream i, the 0th and 8th symbols are from the (8*i)th lane data stream, the 1st and 9th symbols are from the (8*i+2)th lane data stream, the 2nd and 10th symbols are from the (8*i+1)th lane data stream, the 3rd and 11th symbols are from the (8*i+3)th lane data stream, the 4th and 12th symbols are from the (8*i+4)th lane data stream, the 5th and 13th symbols are from the (8*i+6)th lane data stream, the 6th and 14th symbols are from the (8*i+5)th lane data stream, and the 7th and 15th symbols are from the (8*i+7)th lane data stream. Note that the above implementation is equivalent to the following: one symbol is obtained from each of the eight lane data streams, and interleaving is performed to obtain eight consecutive symbols in data stream i, where, in the eight consecutive symbols in the first data stream i, the 0th symbol is from the (8*i)th lane data stream, the 1st symbol is from the (8*i+2)th lane data stream, the 2nd symbol is from the (8*i+1)th lane data stream, the 3rd symbol is from the (8*i+3)th lane data stream, the 4th symbol is from the (8*i+4)th lane data stream, the 5th symbol is from the (8*i+6)th lane data stream, the 6th symbol is from the (8*i+5)th lane data stream, and the 7th symbol is from the (8*i+7)th lane data stream.

Block interleaving can alternatively be implemented by using symbol-mux.
represents the j-th symbol in the (8*i)-th lane data stream,
represents the j-th symbol in the (8*i+1)-th lane data stream,
represents the j-th symbol in the (8*i+2)-th lane data stream,
represents the j-th symbol in the (8*i+3)-th lane data stream,
represents the j-th symbol in the (8*i+4)-th lane data stream,
represents the j-th symbol in the (8*i+5)-th lane data stream,
represents the j-th symbol in the (8*i+6)-th lane data stream,
represents the j-th symbol in the (8*i+7)-th lane data stream, j≧0;
, and
It should be noted that, are consecutive in the first data stream i obtained by multiplexing. That is, the data sequence of the first data stream i after 8:1 symbol multiplexing is
Another specific symbol multiplexing is where one symbol is obtained from each of the eight lane data streams, and in the first data stream obtained by 8:1 symbol multiplexing,
, and
That is, the data sequence of the first data stream i after 8:1 symbol multiplexing is
and 0≦i≦3.

Note that in some specific implementation scenarios, when the transmitting device 01 transmits 1*800GE services, after PMA 4:1 multiplexing is performed, 32 PCS lane data streams are sent to the transmitting processing module via the lane attachment unit interface AUI. During PMA 4:1 multiplexing, two of the four input data streams are from two of the 0th to 15th PCS lane data streams, and the other two are from two of the 16th to 31st PCS lane data streams. In relation to the aforementioned feature that "during PMA 4:1 multiplexing, two of the four input data streams are from two of the 0th to 15th PCS lane data streams, and the remaining two are from two of the 16th to 31st PCS lane data streams," during data processing in the transmitting processing module, first, de-mux is performed to recover the 32 PCS lane data streams, and each physical lane data stream is de-multiplexed and de-muxed to obtain four PCS lane data streams, and then alignment marker lock of the lane data streams is performed by using the known alignment markers of the PCS lanes. Next, lane reordering does not need to be performed, and the block interleaving (or symbol multiplexing) of embodiment 11, embodiment 12, embodiment 13, or embodiment 14 is directly performed on the eight PCS lane data streams obtained by de-muxing the two physical lane data streams, and block interleaving (or symbol multiplexing) is performed on the eight lane data streams to obtain one first data stream, so that 16 consecutive symbols in the first data stream are from at least four RS codewords. For specific embodiments, see Figure 67, Figure 68, Figure 69, Figure 70, Figure 71, or Figure 72. Those skilled in the art will be familiar with these specific embodiments, and the details will not be described again herein.

5102: Perform convolutional interleaving separately on the m first data streams to obtain m second data streams.

Figure 73 is a schematic diagram of a structure in which convolutional interleaving is performed separately on m first data streams according to an embodiment of the present application. As shown in Figure 73, convolutional interleaving can be performed separately on m first data streams via m convolutional interleavers. Each convolutional interleaver performs convolutional interleaving on the input first data stream in units of d symbols to obtain a second data stream in which the data sequence is irregular, and the d symbols are obtained by performing a single block interleaving operation by the block interleaver, where d = D/M.

Note that in this embodiment, each convolutional interleaver performs convolutional interleaving on the input first data stream in a similar manner. Specifically, each convolutional interleaver includes p delay lines, and each convolutional interleaver delays the input first data stream based on the p delay lines to obtain a second data stream. p is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the fewest number of storage units includes 0 storage units, and the difference in the number of storage units between all two adjacent delay lines is Q. Each storage unit is configured to store d symbols. Symbols in each lane data stream are input sequentially to the p delay lines based on their sequence numbers. Each delay line inputs d symbols once and outputs d symbols once. P*d consecutive symbols in the second data stream include d symbols output from the delay line. Q is an integer greater than or equal to 1. For example, p delay lines may each include 0 storage units, Q storage units, 2Q storage units, ..., (p-1)Q storage units, with each storage unit configured to store d symbols. In this case, each of the p delay lines corresponds to p delay values, with the delay values including 0 symbol, Q x d symbols, 2Q x d symbols, ..., (p-1)Q x d symbols. It should be understood that a greater number of symbols included in the delay line delay values indicates a longer delay (also called latency) of the data stream through the delay line. It should be understood that if a delay line does not include a storage unit, the delay of the delay line is 0 symbols; in other words, transparent transmission without delay is performed.

Note that the input switch and output switch of the convolutional interleaver are simultaneously located on the same delay line. After d symbols are input to the current delay line once and d symbols are output from the current delay line once, the switch position is updated to the next delay line, and the symbols in each lane data stream are input sequentially to the p delay lines based on their sequence numbers, ensuring that p*d consecutive symbols in the first data stream contain d symbols output from each delay line. The specific data read/write operation is as follows: d symbols are read from the storage unit closest to the output port and located on the current delay line. The d symbols stored in each storage unit on the current delay line are transferred to the next storage unit. Next, d symbols are written to the storage unit closest to the input port and located on the current delay line. Then, switching to the next delay line is performed, and the above operations are repeated; the rest can be deduced by analogy.

In a possible implementation, the structure of the convolutional interleaver is shown in Figure 12(a), where the number of storage units in the p delay lines is in descending order based on the sequence number of the p delay lines. Specifically, delay line 0 has (p-1)Q storage units, and Q storage units are sequentially reduced in each delay line, with delay line (p-1) having 0 storage units. In this example, since d(p*Q+1) ≥ L2 and L2 = t/s*L1, the d*p consecutive symbols in the second data stream r output by convolutional interleaver r are from at most v*p different codewords, where 0 ≤ r ≤ m-1.

In another possible implementation, the structure of the convolutional interleaver is shown in Figure 12(b), where the number of storage units in the p delay lines is in ascending order based on the sequence numbers of the p delay lines. Specifically, delay line 0 has 0 storage units, and Q storage units are sequentially increased in each delay line, with delay line (p-1) having (p-1)Q storage units. In this example, since d(p*Q-1) ≥ L2 and L2 = t/s*L1, the d*p consecutive symbols in the second data stream r output by convolutional interleaver r are from at most v*p different codewords, where 0 ≤ r ≤ n-1.

It should be understood that the convolutional interleaving of Figure 12(a) and the convolutional interleaving of Figure 12(b) are reciprocal operations when the same parameters p, Q, and d are used. In other words, if the transmitting processing module uses the convolutional interleaving structure shown in Figure 12(a), the corresponding convolutional deinterleaving of the receiving processing module will use the structure shown in Figure 12(b). Similarly, if the transmitting processing module uses the convolutional interleaving structure shown in Figure 12(b), the corresponding convolutional deinterleaving of the receiving processing module will use the structure shown in Figure 12(a).

It should be further understood that any one of the n convolutional interleavers may use either Figure 12(a) or Figure 12(b). In practical applications, all n convolutional interleavers may use the structure shown in Figure 12(a); all n convolutional interleavers may use the structure shown in Figure 12(b); or some convolutional interleavers may use the structure shown in Figure 12(a), and the remaining convolutional interleavers may use the structure shown in Figure 12(b).

For ease of explanation, the following embodiments of convolutional interleaving will be described using an example in which all n convolutional interleavers use the structure shown in Figure 12(a). Naturally, this example may be simply extended to the other structures mentioned above, the specific implementation of which may be known to those skilled in the art and will not be described in detail herein. Below, several specific embodiments of convolutional interleaving will be described.

Embodiment 1: The convolutional interleaving provided in embodiment 1 is performed in step 5101 based on the block interleaving provided in embodiment 1.

Figure 74 is a schematic diagram of an embodiment of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 74, the convolutional interleaver includes p = 3 delay lines. The p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 4 symbols (40 bits). That is, the delay value of delay line 0 is 8Q symbols, the delay value of delay line 1 is 4Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., no delay.

As shown in Figure 74, C _r () represents one symbol (10 bits) in the first data stream r (0≦r≦m-1). For example, C _r (12t), C _r (12t+1), C _r (12t+2), and C _r (12t+3) represent the four symbols currently input to delay line 0 from the first data stream r, C _r (12t-24Q), C _r (12t-24Q+1), C _r (12t-24Q+2), and C _r (12t-24Q+3) are the four symbols output from delay line 0; C _r (12t+4), C _r (12t+5), C _r (12t+6), and C _r (12t+7) represent the four symbols subsequently input to delay line 1 from the first data stream r, and C _r (12t-12Q+4), C _r (12t-12Q+5), C _r C r (12t-12Q+6), C _r (12t-12Q+7) represent the four symbols output from delay line 1; C _r (12t+8), C _r (12t+9), C _r (12t+10), C _r (12t+11) represent the four symbols input to delay line 2 from the first data stream r; C _r (12t+8), C _r (12t+9), C _r (12t+10), C _r (12t+11) represent the four symbols output from delay line 2; C _r (12t+12), C _r (12t+13), C _r (12t+14), C _r (12t+15) represent the four symbols subsequently input to delay line 0 from the first data stream r _; (12t-24Q+12), C _r (12t-24Q+13), C _r (12t-24Q+14), C _r (12t-24Q+15) are the four symbols output from delay line 0; and so on. Referring to the RS distribution rule in the first data stream, when d(pQ+1)≧136, i.e., Q≧11, a total of 12 symbols _Cr (12t-24Q), _Cr (12t-24Q+1), Cr(12t-24Q+2), _Cr (12t-24Q+3), _Cr (12t-12Q+4), _Cr (12t-12Q+5), _Cr (12t-12Q+6), _Cr (12t-12Q+7), _Cr (12t+8), _Cr (12t+9), _Cr (12t+10), and _Cr (12t+11) output by convolutional _interleaving are from 12 different RS codewords.

In a possible implementation, Figure 75 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 75, based on the embodiment shown in Figure 74, its Q = 11 is selected, and the corresponding interleaving latency is approximately 22 * 4 * 3/2 = 132 RS symbols, which is equivalent to a total interleaving and deinterleaving latency of 50 ns for 1 * 800GE service.

Embodiment 2: In this embodiment, a newly designed convolutional interleaver based on embodiment 1 is used to obtain a solution with lower latency but with the second-optimal error correction performance.

Figure 76 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 76, the convolutional interleaver includes p = 2 delay lines. Each of the p = 2 delay lines includes Q storage units and 0 storage units, and each storage unit is configured to store d = 4 symbols (40 bits). That is, the delay value of delay line 0 is 4Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

As shown in Figure 76, C _r () represents one symbol (10 bits) in the first data stream r (0≦r≦m-1). For example, C _r (8t), C _r (8t+1), C _r (8t+2), and C _r (8t+3) represent the four symbols (40 bits) currently input to delay line 0 from the first data stream r, C _r (8t-8Q), C _r (8t-8Q+1), C _r (8t-8Q+2), and C _r (8t-8Q+3) are the four symbols output from delay line 0; C _r (8t+4), C _r (8t+5), C _r (8t+6), and C _r (8t+7) represent the four symbols subsequently input to delay line 1 from the first data stream r, and C _r (8t+4), C _r (8t+5), C _r (8t+6), and C _r (8t+7) is the RS symbol output from delay line 1. _Cr (8t+8), _Cr (8t+9), _Cr (8t+10), and _Cr (8t+11) represent the four symbols subsequently input to delay line 0 from the first data stream r, _Cr (8t-8Q+8), _Cr (8t-8Q+9), _Cr (8t-8Q+10), and _Cr (8t-8Q+11) are the four RS symbols output from delay line 0; and so on. Referring to the RS distribution rule in the first data stream, when d(pQ+1)≧136, i.e., Q≧17, a total of eight symbols C _r (8t-8Q), C _r (8t-8Q+1), C _r (8t-8Q+2), C _r (8t-8Q+3), C _r (8t+4), C _r (8t+5), C _r (8t+6), C _r (8t+7) output through convolutional interleaving are from eight different RS codewords.

In a possible implementation, Figure 77 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 77, based on the embodiment shown in Figure 76, its Q = 17 is selected, and the corresponding interleaving latency is approximately 17 * 4 * 2 / 2 = 68 RS symbols, which is equivalent to a total interleaving and deinterleaving latency of 26 ns for 1 * 800GE service.

Embodiment 3: The convolutional interleaving provided in embodiment 3 is performed in step 5101 based on the block interleaving provided in embodiment 2.

Figure 78 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 78, the convolutional interleaver includes p = 3 delay lines. The p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., no delay.

As shown in Figure 78, _Sr () represents two consecutive symbols in the first data stream r (0≦r≦m-1) , which is 20 bits in total , and the 20 bits are obtained by performing one block interleaving operation by the block interleaving module provided in this embodiment. The convolutional interleaving process is as follows: _Sr (3t) represents the two symbols currently input to delay line 0 from the first data stream r, and _Sr (3t-6Q) are the two RS symbols output from delay line 0; _Sr (3t+1) represents the two symbols currently input to delay line 1 from the first data stream r, and Sr(3t-3Q+1) are the two symbols output from delay line 1; _Sr (3t+2) represents the two symbols currently input to delay line 2 from the first data stream r, and _Sr (3t+2) are the two symbols output from delay line 2; _Sr (3t+3) represents the two symbols currently input to delay line 0 from the first data stream r, and _Sr (3t-6Q+3) are the two symbols output from delay line 0; and so on. Referring to the RS distribution rule in the first data stream, when d(pQ+1)≧68, i.e., Q≧11, a total of 12 symbols, _Sr (3t-6Q), _Sr (3t-3Q+1), Sr(3t+2), _Sr (3t-6Q+3), _Sr (3t-3Q+4), and _Sr (3t+5), successively output through _{convolutional} interleaving are from 12 different RS code words.

In a possible implementation, Figure 79 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 79, based on the embodiment shown in Figure 78, its Q = 11 is selected, and the corresponding interleaving latency is approximately 22 * 2 * 3 / 2 = 66 RS symbols, which is equivalent to a total interleaving and deinterleaving latency of 50 ns for 1 * 800GE service.

Embodiment 4: In this embodiment, a newly designed convolutional interleaver based on embodiment 2 is used.

Figure 80 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 80, the convolutional interleaver includes p = 6 delay lines. The p = 6 delay lines include 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 2 symbols (20 bits). That is, delay line 0 has a delay value of 10Q symbols, delay line 1 has a delay value of 8Q symbols, delay line 2 has a delay value of 6Q symbols, delay line 3 has a delay value of 4Q symbols, delay line 4 has a delay value of 2Q symbols, and delay line 5 has a delay value of 0 symbol, i.e., no delay.

As shown in Figure 80, _Sr () represents two consecutive symbols in the first data stream r (0≦r≦m−1) , which is a total of 20 bits , and the 20 bits are obtained by performing one block interleaving operation by the block interleaving module provided in this embodiment. The convolutional interleaving process is as follows: _Sr (6t) represents the two symbols currently input to delay line 0 from the first data stream r, and _Sr (6t-30Q) are the two RS symbols output from delay line 0; _Sr (6t+1) represents the two symbols currently input to delay line 1 from the first data stream r, and _Sr (6t-24Q+1) are the two symbols output from delay line 1; _Sr (6t+2) represents the two symbols currently input to delay line 2 from the first data stream r, and _Sr (6t-18Q+2) are the two symbols output from delay line 2; _Sr (6t+3) represents the two symbols currently input to delay line 3 from the first data stream r, and _Sr (6t-12Q+3) are the two symbols output from delay line 3; _Sr (6t+4) represents the two symbols currently input to delay line 4 from the first data stream r, and _Sr (6t-6Q+4) are the two symbols output from delay line 4; _Sr (6t+5) represents the two symbols currently input to delay line 5 from the first data stream r, and _Sr (6t+5) are the two symbols output from delay line 5; _Sr (6t+6) represents the two symbols currently input to delay line 0 from the first data stream r, and _Sr (6t-30Q+6) are the two symbols output from delay line 0; and so on. Referring to the RS distribution rule in the first data stream, when d(2pQ+1)≧68, i.e., Q≧3, a total of 12 symbols, _Sr (6t-30Q), _Sr (6t-24Q+1), _Sr (6t-18Q+2), _Sr (6t-12Q+3), _Sr (6t-6Q+4), and _Sr (6t+5), successively output through convolutional interleaving are from 12 different RS code words.

Figure 81 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 81, based on the embodiment shown in Figure 80, its Q = 3 is selected, and the corresponding interleaving latency is approximately 15 * 2 * 6 / 2 = 90 RS symbols, which is equivalent to a total interleaving and deinterleaving latency of 67 ns for 1 * 800GE service.

Embodiment 5: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 1, 3, 4, or 5. The convolutional interleaver includes p = 4 delay lines. The p = 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store d = 4 symbols (40 bits). Referring to the RS distribution rule in the first data stream, when d(p * Q + 1) ≥ 136, i.e., Q ≥ 9, or when v(p * Q - 1) ≥ 136, i.e., Q ≥ 9, the 16 symbols output from the four delay lines of the convolutional interleaver in one polling are from 16 different RS code words.

It should be noted that the block interleaving provided in embodiments 3, 4, and 6 of step 5101 may be implemented based on the convolutional interleaving provided in embodiments 1 and 2 of step 5102. The block interleaving provided in embodiment 5 of step 5101 may be implemented based on the convolutional interleaving provided in embodiments 3 and 4 of step 5102.

Note that all d consecutive symbols in each first data stream obtained by block interleaving are from at least v different code words, and all L2 consecutive symbols in each first data stream are from at least v different code words. In some implementation scenarios, for example, implementations 7 to 10 of step 5101, v<d. In specific embodiments, each convolutional interleaver performs convolutional interleaving on the input first data stream in units of v symbols to obtain a second data stream in which the data sequence is irregular. Note that each storage unit in the convolutional interleaver stores v symbols. Two specific implementations of convolutional interleaving are described below.

Embodiment 6: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 7, 8, 9, or 10. Based on embodiment 1, and referring to Figure 72 and the RS distribution rule in the first data stream, when v(p*Q+1)≥272, in other words, 12*Q+4≥272, i.e., Q≥23, a total of 12 symbols _Cr (12t-24Q), _Cr (12t-24Q+1), _Cr (12t-24Q+2), Cr(12t-24Q+3), _Cr (12t-12Q+4), _Cr (12t-12Q+5), _Cr (12t-12Q+6), _Cr (12t-12Q+7), _Cr (12t+8), _Cr (12t+9), _Cr (12t+10), and _Cr (12t+11) output by _{convolutional} interleaving are from 12 different RS codewords.

Figure 82 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application. In a possible implementation, Q = 23 is selected based on the embodiment shown in Figure 74. The specific convolutional interleaver shown in Figure 82 has a corresponding interleave latency of approximately 2 * 23 * 4 * 3 / 2 = 276 RS symbols, which is equivalent to a total interleave and deinterleave latency of 52 ns for 1 * 800GE service.

Embodiment 7: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 11, 12, 13, or 14. Based on embodiment 1, and referring to Figure 74 and the RS distribution rule in the first data stream, when v(p*Q+1)≥544, in other words, 12*Q+4≥544, i.e., Q≥45, a total of 12 symbols _Cr (12t-24Q), _Cr (12t-24Q+1), _Cr (12t-24Q+2), Cr(12t-24Q+3), _Cr (12t-12Q+4), _Cr (12t-12Q+5), _Cr (12t-12Q+6), _Cr (12t-12Q+7), _Cr (12t+8), _Cr (12t+9), _Cr (12t+10), and _Cr (12t+11) output by _{convolutional} interleaving are from 12 different RS codewords.

Figure 83 is a schematic diagram of another embodiment of a convolutional interleaver according to an embodiment of the present application. In a possible implementation, Q=45 is selected based on the embodiment shown in Figure 74. The specific convolutional interleaver shown in Figure 83 has a corresponding interleaving latency of approximately 2*45*4*3/2 = 540 RS symbols, which is equivalent to a total interleaving and deinterleaving latency of 51 ns for 1*800GE service.

Embodiment 8: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 7, 8, 9, or 10. The convolutional interleaver includes p = 4 delay lines. The p = 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store v = 4 symbols (40 bits). Referring to the RS distribution rule in the first data stream, when v(p * Q + 1) ≥ 272, i.e., Q ≥ 17, or when v(p * Q - 1) ≥ 272, i.e., Q ≥ 18, the 16 symbols output from the four delay lines of the convolutional interleaver in one polling are from 16 different RS code words.

Embodiment 9: The convolutional interleaving provided in this embodiment is implemented in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 11, 12, 13, or 14. The convolutional interleaver includes p = 4 delay lines. The p = 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store v = 4 symbols (40 bits). Referring to the RS distribution rule in the first data stream, when v(p * Q + 1) ≥ 544, i.e., Q ≥ 34, or when v(p * Q - 1) ≥ 272, i.e., Q ≥ 35, the 16 symbols output from the four delay lines of the convolutional interleaver in one polling are from 16 different RS code words.

Note that in the nine embodiments described above, each storage unit stores an integer number of RS symbols. If the information length of the codeword of the inner code is an integer number of RS symbols and is also an integer multiple of v*p, the receiving-side processing module can automatically perform convolutional deinterleaving synchronization after inner code synchronization. For cases where the information length of the inner code is not an integer number of RS symbols, a convolutional interleaving solution is provided that facilitates the receiving-side processing module in performing convolutional deinterleaving synchronization. Eight specific embodiments of convolutional interleaving are described below.

Embodiment 10: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 1, 3, 4, or 6. The convolutional interleaver includes p = 4 delay lines. The p = 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store v = 34 bits. Referring to the RS distribution rule in the first data stream, when the convolutional interleaver shown in Figure 12(a) is used and v(p * Q + 1) ≥ 1360, i.e., Q ≥ 10, or when the convolutional interleaver shown in Figure 12(b) is used and v(p * Q - 1) ≥ 1360, i.e., Q ≥ 11, the 136 bits output from the four delay lines of the convolutional interleaver, for which one polling is performed, are from 16 different RS code words. For Q = 10, the corresponding convolution and deconvolution latency is approximately 75 ns.

Embodiment 11: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 1, 3, 4, or 6. The convolutional interleaver includes p = 2 delay lines. The p = 2 delay lines each include Q storage units and 0 storage units, and each storage unit is configured to store v = 68 bits. Referring to the RS distribution rule in the first data stream, when the convolutional interleaver shown in Figure 12(a) is used and v(p * Q + 1) ≥ 1360, i.e., Q ≥ 10, or when the convolutional interleaver shown in Figure 12(b) is used and v(p * Q - 1) ≥ 1360, i.e., Q ≥ 11, the 136 bits of the convolutional interleaver output from the two delay lines and polled once are from at least 8 different RS code words. For Q = 10, the corresponding convolution and deconvolution latency is approximately 26 ns.

Embodiment 12: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 2 or 5. The convolutional interleaver includes p = 4 delay lines. The p = 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store v = 34 bits. Referring to the RS distribution rule in the first data stream, when the convolutional interleaver shown in Figure 12(a) is used and v(p * Q + 1) ≥ 680, i.e., Q ≥ 5, or when the convolutional interleaver shown in Figure 12(b) is used and v(p * Q - 1) ≥ 680, i.e., Q ≥ 6, the 136 bits output from the four delay lines of the convolutional interleaver, for which one polling is performed, are from 16 different RS code words. For Q = 5, the corresponding convolution and deconvolution latency is approximately 75ns.

Embodiment 13: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 2 or 4. The convolutional interleaver includes p = 2 delay lines. Each of the p = 2 delay lines includes Q storage units and 0 storage units, and each storage unit is configured to store v = 68 bits. Referring to the RS distribution rule in the first data stream, when the convolutional interleaver shown in Figure 12(a) is used and v(p * Q + 1) ≥ 680, i.e., Q ≥ 5, or when the convolutional interleaver shown in Figure 12(b) is used and v(p * Q - 1 ≥ 680), i.e., Q ≥ 6, the 136 bits of the convolutional interleaver output from the two delay lines and polled once are from at least 8 different RS code words. For Q = 5, the corresponding convolution and deconvolution latency is approximately 26 ns.

Embodiment 14: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiments 7, 8, 9, or 10. The convolutional interleaver includes p = 4 delay lines. The p = 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store v = 34 bits. Referring to the RS distribution rule in the first data stream, when the convolutional interleaver shown in Figure 12(a) is used and v(p * Q + 1) ≥ 2720, i.e., Q ≥ 20, or when the convolutional interleaver shown in Figure 12(b) is used and v(p * Q - 1) ≥ 2720, i.e., Q ≥ 21, the 136 bits output from the four delay lines of the convolutional interleaver, for which one polling is performed, are from 16 different RS code words. For Q = 20, the corresponding convolution and deconvolution latency is approximately 75 ns.

Embodiment 15: The convolutional interleaving provided in this embodiment is implemented in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiment 7, 8, 9, or 10. The convolutional interleaver includes p = 2 delay lines. The p = 2 delay lines each include Q storage units and 0 storage units, and each storage unit is configured to store v = 68 bits. Referring to the RS distribution rule in the first data stream, when v(p * Q + 1) ≥ 2720, i.e., Q ≥ 20, or when v(p * Q - 1) ≥ 2720, i.e., Q ≥ 21, the 136 bits of the convolutional interleaver output from the two delay lines and polled once are from at least 8 different RS code words. When Q = 40, the corresponding convolutional and deconvolutional latency is approximately 26 ns.

Embodiment 16: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiments 11, 12, 13, or 14. The convolutional interleaver includes p = 4 delay lines. The p = 4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is configured to store v = 34 bits. Referring to the RS distribution rules within the first data stream, when the convolutional interleaver shown in Figure 12(a) is used and v(p*Q+1) ≥ 5440, i.e., Q ≥ 40, or when the convolutional interleaver shown in Figure 12(b) is used and v(p*Q-1) ≥ 5440, i.e., Q ≥ 41, the 136 bits output from the four delay lines of the convolutional interleaver with one polling run are from 16 different RS codewords. When Q = 40, the corresponding convolutional and deconvolutional latency is approximately 75 ns.

Embodiment 17: The convolutional interleaving provided in this embodiment is performed in step 5101 based on the block interleaving (or symbol multiplexing) provided in embodiments 11, 12, 13, or 14. The convolutional interleaver includes p = 2 delay lines. The p = 4 delay lines each include Q storage units and 0 storage units, and each storage unit is configured to store v = 68 bits. Referring to the RS distribution rule in the first data stream, when the convolutional interleaver shown in Figure 12(a) is used and v(p * Q + 1) ≥ 5440, i.e., Q ≥ 40, or when the convolutional interleaver shown in Figure 12(b) is used and v(p * Q - 1) ≥ 5440, i.e., Q ≥ 41, the 136 bits of the convolutional interleaver output from the two delay lines and polled once are from at least 8 different RS code words. For Q = 40, the corresponding convolution and deconvolution latency is approximately 26 ns.

5103: Separately perform second FEC encoding on the m second data streams to obtain m encoded data streams.

An embodiment of the second FEC encoding is specifically shown in FIG. 15. The second FEC encoding, i.e., the inner code encoding described above, is performed separately on m second data streams. Every K consecutive symbols in each second data stream are mapped to information data of the codeword of the inner code to obtain an encoded data stream, and redundant data is added by the inner code encoding. For the convolutional interleaver shown in FIG. 12(a) or 12(b), the information data of the inner code having a length of K symbols comes from up to K different RS codewords, where K≧pd, and the K symbols are output from p delay lines. K/pd polling operations are performed. After data processing is performed on the encoded data stream, the processed data stream is transmitted to a channel transmission medium for transmission. The data processing may include channel interleaving, modulation, and mapping to improve the system's ability to tolerate burst errors.

In some implementation scenarios, for example, in implementations 7 to 10 of step 5101, v<d. In a specific embodiment, every K consecutive symbols in each second data stream are mapped to information data of a codeword of an inner code to obtain an encoded data stream, and redundant data is added by inner code encoding. The information data of the inner code of the convolutional interleaver, which has a length of K symbols, is from up to K different RS codewords, where K≧pv, and the K symbols are K symbols output from p delay lines, and K/pv polling is performed.

Inner code encoding is performed separately on 16, 8, or 4 second data streams, resulting in an information bit length of 120 bits for the inner code encoding. Specifically, the inner code encoder adds redundancy separately to a total of 120 bits in 12 consecutive symbols in the second data stream to obtain a codeword data stream of the inner code. The embodiments shown in Figures 74 and 75 are used as examples. The 12 symbols are 12 consecutive symbols output from three delay lines of a convolutional interleaver for which one polling is performed. This format can facilitate the receiver processing module shown in Figure 3(h) when performing convolutional deinterleave synchronization after completing inner code synchronization. In a possible implementation, inner code encoding is performed using Hamming (128, 120) to obtain a 128-bit codeword, and 8 bits of redundancy are added to a total of 120 bits in 12 consecutive symbols in each second data stream.

Based on the convolutional interleaving provided in any embodiment of step 5102, inner code encoding is separately performed on the m second data streams, and the information bit length of the inner code encoding is 136 bits. Specifically, the inner code encoder separately adds redundancy to 136 consecutive bits in the second data streams to obtain codeword data streams of the inner code. In a possible embodiment, inner code encoding is performed using Hamming (144, 136) to obtain 144-bit codewords, and 8 bits of redundancy are added to 136 consecutive bits in each second data stream.

Based on the convolutional interleaving of embodiments 10 to 17 provided in step 5102, inner code encoding is performed separately on the m second data streams, and the information bit length of the inner code encoding is 136 bits. Specifically, the 136-bit data output from p=4 or two delay lines of the convolutional interleaver and polled once is used as inner code information data, and then 8 bits of parity data are added to obtain an inner code codeword with a length of 144 bits. In this way, the receiving-side processing module can automatically complete convolutional deinterleaving synchronization after completing inner code synchronization.

FIG. 84 is a schematic diagram of an implementation of inner code encoding according to an embodiment of the present application. As shown in FIG. 84, in a possible implementation, inner code encoding is performed by using Hamming (144, 136), which is obtained by shortening Hamming (255, 247) generated by using Galois field GF(2^8) by 111 bits. Another possible implementation is shown in FIG. 84. The 136-bit data to be encoded is represented as B[135:0]. Bitwise XOR is performed on every two consecutive bits of the 136-bit data to be encoded to obtain one-bit data C[i], and a total of 68-bit data is obtained, which is represented as C[67:0], where C[i] = B[2*i]^B[2*i+1], and 0≦i≦67. Then, Hamming (76, 68) encoding is performed by using C[67:0] as information data to obtain 8-bit parity data represented as P[7:0]. Finally, a total of 144 bits B[135:0] and P[7:0] are concatenated with the output of the inner code encoding, resulting in 144-bit data represented as O[143:0]. O[135:0] is from B[135:0], and O[143:136] is from P[7:0]. Hamming(76,68) is obtained by shortening the extended Hamming(128,120) by 52 bits with a 1-bit CRC generated using the Galois field GF(2^7). Finally, PAM4 Gray mapping is performed on every two consecutive bits in O[143:0] to obtain 72 PAM4 symbols represented as S[71:0].

After data processing is performed on the inner-code-encoded data stream, the data-processed data stream is transmitted to a channel transmission medium for transmission. Data processing may include modulation and mapping, channel interleaving, etc. For example, channel interleaving may be performed on the inner-code-encoded data stream to improve the system's ability to tolerate burst errors. The embodiments shown in Figures 74 and 75 are used as examples. When the transmitting device 01 transmits 1*800GE service, the concatenated code of KP4 RS(544,514)+Hamming(128,120) is used under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.8E-3, which is close to the optimal performance of the concatenated FEC scheme, and the interleaver latency is only 55 ns. The embodiments shown in Figures 76 and 77 are used as examples. When the transmitting device 01 transmits a 1*800GE service, the concatenated code of KP4 RS(544,514)+Hamming(128,120) is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 3.8E-3, and the latency of the interleaver is only 26 ns. The embodiments shown in Figures 78 and 79 are used as examples. When the transmitting device 01 transmits a 1*800GE service, the concatenated code of KP4 RS(544,514)+Hamming(128,120) is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 4.8E-3, and the performance is close to the optimal performance of the concatenated FEC scheme, and the latency of the interleaver is only 50 ns. The embodiments shown in Figures 80 and 81 are used as examples. When the transmitting device 01 transmits a 1*800GE service, the concatenated code of KP4 RS(544,514)+Hamming(128,120) is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 4.8E-3, the performance is close to the optimal performance of the concatenated FEC scheme, and the latency of the interleaver is only 67 ns. The block interleaving (symbol multiplexing) in embodiment 7 or 8 in step 5101 and the convolutional interleaving in embodiment 5 in step 5102 are used as an example. When the transmitting device 01 transmits a 1*800GE service, the concatenated code of KP4 RS(544,514)+Hamming(128,120) is under AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is about 4.8E-3, the performance is close to the optimal performance of the concatenated FEC scheme, and the latency of the interleaver is only 52 ns. The block interleaving (symbol multiplexing) in embodiment 9 or 10 in step 5101 and the convolutional interleaving in embodiment 6 in step 5102 are used as an example. When the transmitting device 01 transmits 1*800GE services, the concatenated code of KP4 RS(544,514)+Hamming(128,120) is used in AWGN, and the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.8E-3, which is close to the optimal performance of the concatenated FEC scheme, and the interleaver latency is only 52ns.

In a possible embodiment, when transmitting device 01 transmits 2*400GE services, the format of the data streams on the 32 PCS lanes in the transmitting device is shown in Figure 6, where PCS lane data streams 0 to 15 and PCS lane data streams 16 to 32 belong to two different 400GE services. The PMA unit of the transmitting processing module restores the 32 PCS lane data streams by performing de-mux on the lane attachment unit interface AUI. Then, alignment marker lock is performed on the lane data streams using the known alignment markers of the PCS lanes. Next, lane reordering is performed on the n = 32 PCS lane data streams based on the alignment markers, so that the data on the n = 32 PCS lanes can be arranged in a specified sequence. In a specific arrangement, lane data streams 0 to 15 belong to the same 400GE service, and lane data streams 16 to 31 belong to another 400GE service. The sorted 32 lane data streams are sent to the block interleaving provided in embodiments 1, 2, and 3 of step 5101 and the convolutional interleaving provided in step 5102, after which Hamming (128, 120) is used for inner code encoding. In another specific arrangement, lane data streams 0 to 7 and lane data streams 16 to 23 belong to the same 400GE service, and lane data streams 8 to 15 and lane data streams 24 to 31 belong to another 400GE service. The sorted 32 lane data streams are sent to the block interleaving provided in embodiments 4, 5, and 6 of step 5101 and the convolutional interleaving provided in step 5102, after which Hamming (128, 120) is used for inner code encoding.

In this scenario, the embodiments shown in Figures 74 and 75 are used as an example, where the 12 symbols of each inner code are from six different RS codewords, the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 3.5E-3, and the interleaver latency is still maintained at only 50 ns. The embodiments shown in Figures 78 and 79 are used as an example, where the 12 symbols of each inner code are from six different RS codewords, the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 3.5E-3, and the interleaver latency is still maintained at only 50 ns. The embodiments shown in Figures 80 and 81 are used as an example, where the 12 symbols of each inner code are from six different RS codewords, the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 3.4E-3, and the interleaver latency is still maintained at only 50 ns. Alternatively, in this embodiment, block interleaving and convolutional interleaving are used, and the parameters in convolutional interleaving are set as Q≧6, so that the 12 symbols of information data for each inner code can come from 12 different RS codewords. The corresponding pre-FEC bit error rate (BER) to achieve a post-FEC BER of 1E-15 is approximately 4.8E-3, and the interleaver latency is increased to 135 ns.

In another possible embodiment, when transmitting device 01 transmits 4*200GE services, the format of the data streams on the 32 PCS lanes in the transmitting device is shown in FIG. 7, where PCS lane data streams 0 to 7, PCS lane data streams 8 to 15, PCS lane data streams 16 to 23, and PCS lane data streams 24 to 31 belong to four different 200GE services, respectively. The PMA unit of the transmitting processing module recovers the 32 PCS lane data streams by performing de-mux on the data received via the lane attachment unit interface AUI. Then, alignment marker lock is performed on the lane data streams using known alignment markers of the PCS lanes. Next, lane reordering is performed on the n=32 PCS lane data streams based on the alignment markers, so that the data on the n=32 PCS lanes can be arranged in a specified sequence. In a specific arrangement, lane data streams 0 to 7, lane data streams 8 to 15, lane data streams 16 to 23, and lane data streams 24 to 32 belong to four different 200GE services, respectively. The sorted 32 lane data streams are sent to the block interleaving provided in embodiments 1, 2, and 3 in step 5101 and convolutional interleaving in step 5102, after which Hamming (128, 120) is used for inner code encoding. Another specific arrangement is as follows: lane data streams 0 to 3 and lane data streams 16 to 19, lane data streams 4 to 7 and lane data streams 20 to 23, lane data streams 8 to 11 and lane data streams 24 to 28, and lane data streams 12 to 15 and lane data streams 28 to 31 belong to four different 200GE services, respectively. The sorted 32 lane data stream is sent to the block interleaving provided in embodiments 3, 4, and 5 in step 5101, and to the convolutional interleaving in step 5102, after which Hamming (128, 120) is used for inner code encoding.

In this scenario, the embodiments shown in Figures 74 and 75 are used as an example, where the 12 symbols of each inner code are from four different RS codewords, the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 2.8E-3, and the interleaver latency is still maintained at only 50 ns. The embodiments shown in Figures 78 and 79 are used as an example, where the 12 symbols of each inner code are from four different RS codewords, the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 2.8E-3, and the interleaver latency is still maintained at only 50 ns. The embodiments shown in Figures 80 and 81 are used as an example, where the 12 symbols of each inner code are from four different RS codewords, the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 2.8E-3, and the interleaver latency is still maintained at only 50 ns. Alternatively, block interleaving and convolutional interleaving are used in this embodiment, with the parameters for convolutional interleaving set as Q≧6, so that the 12 symbol information data for each inner code can come from six RS codewords, the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 3.4E-3, and the interleaver latency is increased to 135 ns. Alternatively, block interleaving and convolutional interleaving are used in this embodiment, with the parameters for convolutional interleaving set as Q≧12, so that the 12 symbol information data for each inner code can come from 12 RS codewords, the corresponding pre-FEC BER to achieve a post-FEC bit error rate BER of 1E-15 is approximately 4.8E-3, and the interleaver latency is increased to 270 ns.

In the present invention, a data interleaving and encoding method, including block interleaving and convolutional interleaving, is designed for the concatenated FEC transmission solution, resulting in an overall concatenated FEC solution with good performance and extremely low latency. In this way, the cascaded FEC transmission solution can be applied to multiple transmission scenarios, and is particularly applicable to transmission scenarios requiring low transmission latency, such as low-latency data center interconnection scenarios. Compared with conventional technologies, the overall concatenated FEC solution can provide shorter latency when processing 1*800GE services with the same error correction capability, and can obtain suboptimal error correction performance and better latency using the same interleaving solution for 2*400GE or 4*200GE services. Therefore, this solution may be fully applicable to latency-sensitive scenarios such as internal interconnection networks in data centers.

The following describes the data processing device provided in an embodiment of the present application.

Figure 85 is a schematic diagram of the structure of a data processing apparatus according to an embodiment of the present application. As shown in Figure 85, the data processing apparatus includes a block interleaver 501 and a convolutional interleaver 502. The block interleaver 501 is configured to perform the operation of step 5101. The convolutional interleaver 502 is configured to perform the operation of step 5102. For details, please refer to the relevant descriptions of the block interleaving operation and the convolutional interleaving operation in the aforementioned data processing method. The details will not be described again in this specification.

It should be understood that the devices provided in this application may alternatively be implemented in other ways. For example, the unit divisions of the devices described above are merely logical functional divisions, and other divisions may be used in actual implementations. For example, multiple units or components may be combined or integrated into another system. In addition, functional units in the embodiments of this application may be integrated into a single processing unit, or may be separate physical units, or two or more functional units may be integrated into a single processing unit. Integrated units may be implemented in the form of hardware or software functional units.

It should be noted that in addition to the data processing method described in the above embodiment, the present application also provides another data processing method. Specific processing steps of the data processing method may be shown in FIG. 3(i). In some specific implementation scenarios, when the transmitting device 01 transmits 1*800GE services, for 32 PCS lane data streams, 32/n PCS lane data streams are multiplexed into one data stream (PMA lane data stream) by PMA (32:n) processing. Among the 32/n multiplexed PCS lane data streams, half of the PCS lane data streams are from PCS lane data streams 0 to 15, and the other half are from PCS lane data streams 16 to 32. Therefore, the data of each PMA lane data stream is obtained by interleaving four RS codewords. The Physical Medium Attachment (PMA) sublayer of the transmitting processing module processes data from the AUI-n interface to obtain n lane data streams. The PMA sublayer herein only needs to perform signal recovery operations such as clock data recovery (CDR) and PAM4 symbol demodulation on data from each physical lane of the AUI-n interface to obtain one lane data stream, without needing to perform other complex operations such as AM lock, lane deskew, and lane reordering. Next, convolutional interleaving is performed on each first data stream to obtain n first data stream convolutional interleaves. Finally, inner code encoding is performed on the n first data streams to obtain n second data streams.

Figure 86 is a schematic flowchart of a data processing method according to an embodiment of the present application.

8601: Perform convolutional interleaving separately on the n lane data streams to obtain n first data streams.

Specifically, n lane data streams are separately delayed based on p delay lines to obtain n first data streams. A first FEC encoding is performed on each lane data stream, in other words, an outer code encoding is performed on each lane data stream. It should be understood that the convolutional interleaving scheme used in this embodiment is similar to the convolutional interleaving scheme used in the embodiment shown in FIG. 51. For details, please refer to the related description in the embodiment shown in FIG. 51.

In the example, when n = 8, the corresponding convolutional interleaver may use embodiment 6 provided in step 5102. The inner code encoding scheme uses 120 bits of data output from p = 3 delay lines after one polling of the convolutional interleaver as inner code information data, to which 8 bits of parity data are added to obtain an inner code codeword having a length of 128 bits. Alternatively, the corresponding convolutional interleaver may use embodiment 8 provided in step 5102. The inner code encoding scheme uses 160 bits of data output from p = 4 delay lines after one polling of the convolutional interleaver as inner code information data, to which 10 bits of parity data are added to obtain an inner code codeword having a length of 170 bits, or to which 16 bits of parity data are added to obtain an inner code codeword having a length of 176 bits. Alternatively, the corresponding convolutional interleaver may use embodiments 14 and 15 provided in step 5102. The inner code encoding method uses the 136 bits of data output from p = 2 or 4 delay lines after one polling of the convolutional interleaver as the inner code information data, and 8 bits of parity data are added to obtain a codeword with a code length of 144 bits.

In another example, when n = 4, the corresponding convolutional interleaver can use embodiment 7 provided in step 5102. The inner code encoding scheme uses 120 bits of data output from p = 3 delay lines after one polling of the convolutional interleaver as inner code information data, to which 8 bits of parity data are added to obtain an inner code codeword having a length of 128 bits. Alternatively, the corresponding convolutional interleaver can use embodiment 9 provided in step 5102. The inner code encoding scheme uses 160 bits of data output from p = 4 delay lines after one polling of the convolutional interleaver as inner code information data, to which 10 bits of parity data are added to obtain an inner code codeword having a length of 170 bits, or to which 16 bits of parity data are added to obtain an inner code codeword having a length of 176 bits. Alternatively, the corresponding convolutional interleaver can use embodiments 16 and 17 provided in step 5102. The inner code encoding method uses the 136 bits of data output from p = 2 or 4 delay lines after one polling of the convolutional interleaver as the inner code information data, and 8 bits of parity data are added to obtain a codeword with a code length of 144 bits.

8602: Separately perform a second FEC encoding on the n first data streams to obtain n second data streams.

It should be understood that the second FEC encoding in this embodiment is the inner code encoding described above. By using both convolutional interleaving and inner code encoding methods, the length of the information data of the codeword of the inner code can be equal to p*U, where p is the number of delay lines of the convolutional interleaver and U is the number of bits stored in each storage unit of the convolutional interleaver. In this way, the information data of the codeword of the inner code is aligned with the p*U bits output from the p delay lines of the convolutional interleaver, which are polled once. Therefore, if a synchronization header sequence is not additionally added to the encoded data stream, the receiving module can automatically complete convolutional deinterleaving synchronization after completing inner code self-synchronization by using the codeword of the inner code, thereby solving the problem of convolutional interleaver synchronization.

The present application further provides a data processing device corresponding to the embodiment shown in FIG. 86.

Figure 87 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application. As shown in Figure 87, the data processing device includes a convolutional interleaver 601 and an encoder 602. The convolutional interleaver 601 is configured to perform the operation of step 8601. The encoder 602 is configured to perform the operation of step 8602. For details, please refer to the relevant descriptions of the block interleaving operation and the convolutional interleaving operation in the aforementioned data processing method. The details will not be described again in this specification.

It should be understood that the devices provided in this application may alternatively be implemented in other ways. For example, the unit divisions of the devices described above are merely logical functional divisions, and other divisions may be used in actual implementations. For example, multiple units or components may be combined or integrated into another system. In addition, functional units in the embodiments of this application may be integrated into a single processing unit, or may be separate physical units, or two or more functional units may be integrated into a single processing unit. Integrated units may be implemented in the form of hardware or software functional units.

88 is a schematic diagram of another structure of a data processing device according to an embodiment of the present application. As shown in FIG. 88, the data processing device includes a processor 201, a memory 202, and a transceiver 203. The processor 201, the memory 202, and the transceiver 203 are interconnected via lines. The memory 202 is configured to store program instructions and data. Specifically, the transceiver 203 is configured to receive n lane data streams. The processor 201 is configured to perform operations in a data processing method. In a possible implementation, the processor 201 may include the convolutional interleaver 101 and multiplexer 201 shown in FIG. 33. In another possible implementation, the processor 201 may include the interleaving module 301 and the encoder 302 shown in FIG. 50(a). In yet another possible implementation, the processor 201 may include the interleaving module 401 and the encoder 402 shown in FIG. 50(b). In yet another possible implementation, the processor 201 may include a block interleaver 501 and a convolutional interleaver 502 as shown in FIG. 85. In yet another possible implementation, the processor 201 may include a convolutional interleaver 601 and an encoder 602 as shown in FIG. 87.

Note that the processor shown in FIG. 88 can be a general-purpose central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The memory shown in FIG. 88 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this application are implemented using software or firmware, the program code used to implement the technical solutions provided in the embodiments of this application is stored in the memory and executed by the processor. In an embodiment, the processor may include a memory therein. In another embodiment, the processor and the memory are two independent structures.

It should be clearly understood by those skilled in the art that for the sake of convenience and conciseness, the detailed operating processes of the aforementioned systems, devices, and units should be referred to the corresponding processes in the aforementioned method embodiments, and the details will not be described again in this specification.

Those skilled in the art can understand that all or part of the steps in the above-described embodiments can be implemented by hardware or a program instructing related hardware. The program may be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a random access memory, etc. Whether a function is performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but the implementation should not be considered to go beyond the scope of this application.

When software is used to implement the functions, all or some of the method steps described in the above embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded into a computer and executed, the procedures or functions according to the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored on a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, or digital subscriber line (DSL)) or wireless (e.g., infrared, radio, or microwave) transmission. The computer-readable storage medium may be any available medium accessible by a computer, or may be a data storage device, such as a server or data center, incorporating one or more available media. Usable media may include magnetic media (e.g., floppy disks, hard disks, or magnetic tapes), optical media (e.g., DVDs), and semiconductor media (e.g., solid-state drives (SSDs)).

01 Sender device, sending device
02 Sending side processing module
03 Channel Transmission Medium
04 Receiver processing module
05 Receiving device
101 Convolutional Interleaver
102 Multiplexer
201 Multiplexer
201 processor
202 memory
203 Transceiver
301 Interleave Module
302 Encoder
401 Interleave Module
402 Encoder
501 Block Interleaver
502 Convolutional Interleaver
601 Convolutional Interleaver
602 Encoder
3011 Convolutional Interleaver
3012 Block Interleaver
4011 First Block Interleaver
4012 Convolutional Interleaver
4013 Second Block Interleaver

Claims (38)

1. A data processing method comprising:
performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams to obtain a total of m first data streams, where n=q*t and m=q*s, where n is an integer greater than 1, n is exactly divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 2 , and s is an integer greater than or equal to 1; performing first forward error correction (FEC) encoding on all of the n lane data streams, where every a codeword obtained by the first FEC encoding is distributed among b lane data streams, where a≦b≦n, n is exactly divisible by b, and a is an integer greater than or equal to 2; wherein every a consecutive symbols in each lane data stream are from a different codeword, and every L1 consecutive symbols in each lane data stream are from at least a different codewords, where L1 = N*a/b, and N represents the length of the codeword, and the t lane data streams comprise a total of t*a symbols , where the a consecutive symbols in each lane data stream are, and the t*a symbols comprise a total of D bits , for Δ bits in each symbol, and D = Δ*t*a, and the D bits are consecutive in any one of the s first data streams, and Δ = M/s, and M represents the number of bits comprised in a symbol;
separately performing convolutional interleaving on the m first data streams to obtain m second data streams;
A data processing method comprising: 2. The data processing method of claim 1, wherein all d consecutive symbols in each first data stream are from v different codewords, every L2 consecutive symbols in each first data stream are from at least v different codewords, v is exactly divisible by a, L2 = t/s * L1, and d = D/M. The method of claim 1, wherein n=32, 16 lane data streams within odd-numbered lanes of the n lane data streams are from the same codeword, 16 lane data streams within even-numbered lanes of the n lane data streams are from the same codeword, and the data streams within the odd-numbered lanes of the n lane data streams and the data streams within the even-numbered lanes of the n lane data streams are from different codewords. t=8, s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes:
performing block interleaving on a total of eight lane data streams, namely, the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream , to obtain one first data stream, wherein 0≦i≦3, and in the first data stream obtained by block interleaving , a total of 16 consecutive symbols are two consecutive symbols in each of the eight lane data streams, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; 4. The method of claim 3, comprising: every 544 consecutive symbols are from at least four different codewords; the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords. t=8, s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes:
performing block interleaving on a total of eight lane data streams, namely, an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3; a total of 16 symbols are consecutive in the first data stream obtained by block interleaving , which are j-th two consecutive symbol groups in each of the eight lane data streams, and the j-th two consecutive symbol groups in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; 4. The method of claim 3, comprising: every 544 consecutive symbols are from at least four different codewords; the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords. t=8, s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain the s first data streams includes:
performing block interleaving on a total of eight lane data streams, namely, the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and a total of eight symbols, which is a jth symbol included in each of the eight lane data streams, are interleaved by the block interleaving. 4. The method of claim 3, comprising: j>0, wherein every eighth consecutive symbols in the first data stream obtained by block interleaving are from four different codewords, j>0, j>0, and j>0, and wherein a zeroth symbol, a first symbol, a second symbol, and a third symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and a fourth symbol, a fifth symbol, a sixth symbol, and a seventh symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords. 2. The method of claim 1, wherein n=32, 16 consecutive lane data streams sorted at the front of the n lane data streams are from the same codeword, 16 consecutive lane data streams sorted at the back of the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted at the front of the n lane data streams and the 16 consecutive lane data streams sorted at the back of the n lane data streams are from different codewords. where t=2 and s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes:
8. The method of claim 7, comprising: performing block interleaving on an ith lane data stream and an (i+16)th lane data stream to obtain one first data stream, wherein 0≦i<16, two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream are consecutive in the first data stream obtained by the block interleaving, and every fourth consecutive symbol in the first data stream obtained by the block interleaving is from four different codewords. where t=2 and s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes:
8. The method of claim 7, comprising: performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, wherein 0≦i<16, a jth group of consecutive β bits in the ith lane data stream and a jth group of consecutive β bits in the (i+16)th lane data stream are consecutive in the first data stream obtained by block interleaving, j≧0, β is 1, 2, 4, 5, 10, or 20, and every fourth consecutive symbols in the first data stream obtained by block interleaving are from four different codewords. where t=2 and s=2, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes:
performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain a (2*i)th first data stream and a (2*i+1)th first data stream, wherein 0≦i<16, in the (2*i)th first data stream : four consecutive symbols : five bits in each of two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream, for a total of 20 consecutive bits , and every 20 consecutive bits in the (2*i)th first data stream are from four different codewords; and in the (2*i+1)th first data stream : four consecutive symbols : two consecutive symbols in the ith lane data stream and another five bits in each of two consecutive symbols in the (i+16)th lane data stream, for a total of 20 consecutive bits , and every 20 consecutive bits in the (2*i+1)th first data stream are from four different codewords. The method of claim 7, comprising: t=8, s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes:
performing block interleaving on a total of eight lane data streams, namely, the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream , to obtain one first data stream, wherein 0≦i≦3, and in the first data stream obtained by block interleaving , a total of 16 consecutive symbols are two consecutive symbols comprised in each of the eight lane data streams, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; 8. The method of claim 7, comprising: every 544 consecutive symbols are from at least four different codewords; the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords. t=8, s=1, and performing block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams includes:
performing block interleaving on a total of eight lane data streams, namely, a (4*i)th lane data stream, a (4*i+1)th lane data stream, a (4*i+2)th lane data stream, a (4*i+3)th lane data stream, a (4*i+16)th lane data stream, a (4*i+17)th lane data stream, a (4*i+18)th lane data stream, and a (4*i+19)th lane data stream, to obtain one first data stream, where 0≦i≦3; a total of 16 symbols are consecutive in the first data stream obtained by block interleaving , which are j-th two consecutive symbol groups in each of the eight lane data streams, and the j-th two consecutive symbol groups in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; 8. The method of claim 7, comprising: every 544 consecutive symbols are from at least four different codewords; the 0th, 1st, 2nd, and 3rd symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; the 4th, 5th, 6th, and 7th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; the 8th, 9th, 10th, and 11th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords; and the 12th, 13th, 14th, and 15th symbols of every 16 consecutive symbols in the first data stream obtained by the block interleaving are from different codewords. t=8, s=1, and the step of performing block interleaving on every t lane data streams of the n lane data streams to obtain the s first data streams includes:
performing block interleaving on a total of eight lane data streams, namely, the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream, to obtain one first data stream, wherein 0≦i≦3, and a total of eight symbols, which are j-th symbols included in each of the eight lane data streams, are interleaved with the first data stream obtained by the block interleaving; 8. The method of claim 7, comprising: j>0, wherein every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, wherein a zeroth symbol, a first symbol, a second symbol, and a third symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and a fourth symbol, a fifth symbol, a sixth symbol, and a seventh symbol of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords. performing convolutional interleaving on a first data stream to obtain a second data stream;
2. The method of claim 1, comprising: delaying one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, each delay line has a different number of storage units, the delay line with the fewest number of storage units has 0 storage units, the difference in the number of storage units between every two adjacent delay lines is Q, each storage unit is configured to store d symbols, symbols in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, each delay line inputs d symbols once and outputs d symbols once, p*d consecutive symbols in the second data stream comprise the d symbols output from the delay lines, and Q is an integer greater than or equal to 1. performing convolutional interleaving on a first data stream to obtain a second data stream;
2. The method of claim 1, comprising: delaying one first data stream through p delay lines to obtain one second data stream, where p is an integer greater than 1, each delay line has a different number of storage units, and the delay line with the fewest number of storage units has 0 storage units; the difference in the number of storage units between every two adjacent delay lines is Q, and each storage unit is configured to store 4 symbols; symbols in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, each delay line inputs 4 symbols once and outputs 4 symbols once; p*4 consecutive symbols in the second data stream comprise the 4 symbols output from the delay line, and Q satisfies 4(p*Q-1)≧272, 4(p*Q + 1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544. After the step of separately performing convolutional interleaving on the m first data streams to obtain m second data streams, the method further comprises:
16. The method of claim 15, further comprising: separately performing second FEC encoding on the m second data streams to obtain m coded data streams, wherein information data of length K symbols in each of the coded data streams is from up to K different codewords, where K≧p*4. performing convolutional interleaving on a first data stream to obtain a second data stream;
delaying one first data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and the number of storage units provided in each delay line is different, the delay line with the fewest number of storage units has 0 storage units, and the difference in the number of storage units between every two adjacent delay lines is Q;
2. The method of claim 1, wherein each storage unit is configured to store 34 bits, and bits in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, with 34 bits input to each delay line once and 34 bits output from each delay line once, and p*34 consecutive bits in one second data stream comprising the 34 bits output from the delay lines; or wherein each storage unit is configured to store 68 bits, and bits in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, with 68 bits input to each delay line once and 68 bits output from each delay line once, and p*68 consecutive bits in one second data stream comprising the 68 bits output from the delay lines. 2. The method of claim 1, wherein t is 2, 4, or 8. 2. The method of claim 1, wherein s is 1. 1. A data processing apparatus comprising a block interleaver and a convolutional interleaver,
the block interleaver is configured to perform block interleaving on every t lane data streams of the n lane data streams to obtain s first data streams, to obtain a total of m first data streams, where n=q*t and m=q*s, where n is an integer greater than 1 and n is exactly divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 2 , and s is an integer greater than or equal to 1; first forward error correction (FEC) encoding is performed on all the n lane data streams, and every a codeword obtained by the first FEC encoding is distributed among b lane data streams, where a≦b≦n, and n is exactly divisible by b; a is an integer greater than or equal to 2 , every a consecutive symbols in each lane data stream are from a different codeword, and every L1 consecutive symbols in each lane data stream are from at least a different codewords, where L1 = N*a/b, and N represents the length of the codeword, the t lane data streams comprise a total of t*a symbols, where the a consecutive symbols in each lane data stream are, the t *a symbols comprise a total of D bits , for Δ bits in each symbol, and D = Δ*t*a, and the D bits are consecutive in any one of the s first data streams, where Δ = M/s, and M represents the number of bits comprised in a symbol; and
A data processing apparatus configured to separately perform a convolutional interleaver on the m first data streams to obtain the m second data streams. 21. The data processing apparatus of claim 20, wherein every d consecutive symbols in each first data stream are from v different codewords, and every L2 consecutive symbols in each first data stream are from at least v different codewords, where v is exactly divisible by a, L2 = t/s * L1, and d = D/M. 21. The data processing device of claim 20, wherein n=32, 16 lane data streams in odd-numbered lanes of the n lane data streams are from the same codeword, 16 lane data streams in even-numbered lanes of the n lane data streams are from the same codeword, and the data streams in the odd-numbered lanes of the n lane data streams and the data streams in the even-numbered lanes of the n lane data streams are from different codewords. t=8, s=1, and the block interleaver is
performing block interleaving on a total of eight lane data streams, namely, the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream , to obtain one first data stream, wherein 0≦i≦3; in the first data stream obtained by block interleaving , two consecutive symbols comprised in each of the eight lane data streams are 16 consecutive symbols in total , and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords.
23. A data processing apparatus according to claim 22 , specifically configured to: t=8, s=1, and the block interleaver is
To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: an (8*i)th lane data stream, an (8*i+1)th lane data stream, an (8*i+2)th lane data stream, an (8*i+3)th lane data stream, an (8*i+4)th lane data stream, an (8*i+5)th lane data stream, an (8*i+6)th lane data stream, and an (8*i+7)th lane data stream, where 0≦i≦3, and In the first data stream , a total of 16 symbols are consecutive, which are j-th two consecutive symbol groups in each of the eight lane data streams, and the j-th two consecutive symbol groups in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords.
23. A data processing apparatus according to claim 22 , specifically configured to: t=8, s=1, and the block interleaver is
To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (8*i)th lane data stream, the (8*i+1)th lane data stream, the (8*i+2)th lane data stream, the (8*i+3)th lane data stream, the (8*i+4)th lane data stream, the (8*i+5)th lane data stream, the (8*i+6)th lane data stream, and the (8*i+7)th lane data stream; and a total of eight symbols, where 0≦i≦3 and j- th symbols included in each of the eight lane data streams, are used as the first data stream obtained by the block interleaving. j≧0, wherein every eighth consecutive symbols in the first data stream obtained by block interleaving are from four different codewords, and the 0th, 1st, 2nd, and 3rd symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 4th, 5th, 6th, and 7th symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords.
23. A data processing apparatus according to claim 22 , specifically configured to: 21. The data processing apparatus of claim 20, wherein n=32, 16 consecutive lane data streams sorted at the front of the n lane data streams are from the same codeword, 16 consecutive lane data streams sorted at the back of the n lane data streams are from the same codeword, and the 16 consecutive lane data streams sorted at the front of the n lane data streams and the 16 consecutive lane data streams sorted at the back of the n lane data streams are from different codewords. t=2, s=1, and the block interleaver is
performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16, and two consecutive symbols in the ith lane data stream and two consecutive symbols in the (i+16)th lane data stream are consecutive in the first data stream obtained by the block interleaving, and every fourth consecutive symbol in the first data stream obtained by the block interleaving is from four different codewords;
27. A data processing apparatus according to claim 26 , specifically adapted to: t=2, s=1, and the block interleaver is
performing block interleaving on the ith lane data stream and the (i+16)th lane data stream to obtain one first data stream, where 0≦i<16, a jth group of consecutive β bits in the ith lane data stream and a jth group of consecutive β bits in the (i+16)th lane data stream are consecutive in the first data stream obtained by block interleaving, j≧0, β is 1, 2, 4, 5, 10, or 20, and every fourth consecutive symbol in the first data stream obtained by block interleaving is from four different codewords;
27. A data processing apparatus according to claim 26 , specifically adapted to: t=2, s=2, and the block interleaver is
performing block interleaving on the i-th lane data stream and the (i+16)-th lane data stream to obtain a (2*i)-th first data stream and a (2*i+1)-th first data stream, where 0≦i<16; four symbols : five bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits, are consecutive in the (2*i)-th first data stream, and every 20 consecutive bits in the (2*i)-th first data stream are from four different codewords; four symbols : another five bits in each of two consecutive symbols in the i-th lane data stream and two consecutive symbols in the (i+16)-th lane data stream, for a total of 20 bits, are consecutive in the (2*i+1)-th first data stream, and every 20 consecutive bits in the (2*i+1)-th first data stream are from four different codewords;
27. A data processing apparatus according to claim 26 , specifically adapted to: t=8, s=1, and the block interleaver is
performing block interleaving on a total of eight lane data streams, namely, the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream, to obtain one first data stream , wherein 0≦i≦3; in the first data stream obtained by block interleaving , two consecutive symbols comprised in each of the eight lane data streams are 16 consecutive symbols in total , and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords.
27. A data processing apparatus according to claim 26 , specifically adapted to: t=8, s=1, and the block interleaver is
To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: a (4*i)-th lane data stream, a (4*i+1)-th lane data stream, a (4*i+2)-th lane data stream, a (4*i+3)-th lane data stream, a (4*i+16)-th lane data stream, a (4*i+17)-th lane data stream, a (4*i+18)-th lane data stream, and a (4*i+19)-th lane data stream, where 0≦i≦3, and a total of 16 symbols are consecutive in the first data stream obtained by block interleaving, which are j -th two consecutive symbol groups in each of the eight lane data streams, and the j-th two consecutive symbol groups in each of the eight lane data streams are consecutive in the first data stream obtained by block interleaving, j≧0, and every 16 consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords; every 544 consecutive symbols are from at least four different codewords, the 0th, 1st, 2nd, and 3rd symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 4th, 5th, 6th, and 7th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, the 8th, 9th, 10th, and 11th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 12th, 13th, 14th, and 15th symbols of every 16th consecutive symbols in the first data stream obtained by block interleaving are from different codewords.
27. A data processing apparatus according to claim 26 , specifically adapted to: t=8, s=1, and the block interleaver is
To obtain one first data stream, block interleaving is performed on a total of eight lane data streams: the (4*i)th lane data stream, the (4*i+1)th lane data stream, the (4*i+2)th lane data stream, the (4*i+3)th lane data stream, the (4*i+16)th lane data stream, the (4*i+17)th lane data stream, the (4*i+18)th lane data stream, and the (4*i+19)th lane data stream; and a total of eight symbols, where 0≦i≦3 and jth symbols included in each of the eight lane data streams, are used as the first data stream obtained by the block interleaving. and j≧0, wherein every eighth consecutive symbols in the first data stream obtained by block interleaving are from at least four different codewords, and the 0th, 1st, 2nd, and 3rd symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords, and the 4th, 5th, 6th, and 7th symbols of every eighth consecutive symbols in the first data stream obtained by block interleaving are from different codewords.
27. A data processing apparatus according to claim 26 , specifically adapted to: The convolutional interleaver comprises:
21. The data processing apparatus of claim 20, specifically configured to: delay one first lane data stream based on p delay lines to obtain one second data stream, p being an integer greater than 1; each delay line having a different number of storage units, with the delay line having the fewest number of storage units having 0 storage units; a difference in the number of storage units between every two adjacent delay lines being Q; each storage unit being configured to store d symbols; symbols in each lane data stream being input to the p delay lines sequentially based on sequence numbers of the p delay lines, with d symbols being input to each delay line once and d symbols being output from the delay lines once; p* d consecutive symbols in the second data stream comprising the d symbols being output from the delay lines, and Q being an integer greater than or equal to 1. The convolutional interleaver comprises:
delaying one first lane data stream based on p delay lines to obtain one second data stream, where p is an integer greater than 1, and the number of storage units included in each delay line is different, and the delay line with the fewest number of storage units includes 0 storage units; the difference in the number of storage units between every two adjacent delay lines is Q, and each storage unit is configured to store 4 symbols; the symbols in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, and 4 symbols are input to each delay line once and 4 symbols are output from the delay line once; p*4 consecutive symbols in the second data stream include the 4 symbols output from the delay line, and Q satisfies 4(p*Q-1)≧272, 4(p*Q+1)≧272, 4(p*Q-1)≧544, or 4(p*Q+1)≧544;
21. A data processing apparatus according to claim 20 , configured to: The data processing apparatus further comprises an encoder, wherein after the m second data streams are obtained, the encoder
separately performing second FEC encoding on the m second data streams to obtain m coded data streams, wherein the information data having a length of K symbols in each of the coded data streams is from up to K different codewords, where K≧p*4;
35. A data processing apparatus according to claim 34 , configured to: The convolutional interleaver comprises:
A first data stream is delayed based on p delay lines to obtain a second data stream, where p is an integer greater than 1, and the number of storage units provided in each delay line is different, and the delay line with the smallest number of storage units has 0 storage units, and the difference in the number of storage units between every two adjacent delay lines is Q;
21. The data processing apparatus of claim 20, wherein each storage unit is configured to store 34 bits, and bits in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, with 34 bits input to each delay line once and 34 bits output from each delay line once, and p*34 consecutive bits in one second data stream comprising the 34 bits output from the delay lines; or wherein each storage unit is configured to store 68 bits, and bits in each lane data stream are input to the p delay lines sequentially based on sequence numbers of the p delay lines, with 68 bits input to each delay line once and 68 bits output from each delay line once, and p*68 consecutive bits in one second data stream comprising the 68 bits output from the delay lines. 21. The data processing device of claim 20, wherein t is 2, 4, or 8. 21. The data processing apparatus of claim 20, wherein s is 1.