JPWO2020162346A1 - Method for manufacturing group III nitride semiconductor substrate and group III nitride semiconductor substrate - Google Patents

Abstract

In order to solve the above problems, the present invention is composed of a group III nitride semiconductor, the main surface is a semipolar surface, and the surface roughness RMS measured in an area of 5 μm × 5 μm square on the main surface is 0.05 nm or more. A group III nitride semiconductor substrate having a diameter of 1.50 nm or less is provided. Further, the present invention can further provide a group III nitride semiconductor substrate having a dark spot density of 5 × 106 cm-2 or less in the CL image of the main surface. By forming the device on the group III nitride semiconductor substrate provided by the present invention, the quality of the device can be improved.

Description

The present invention relates to a group III nitride semiconductor substrate and a method for manufacturing a group III nitride semiconductor substrate.

Related techniques are disclosed in Patent Document 1 and Patent Document 2. As disclosed in Patent Document 1 and Patent Document 2, when a device (eg, optical device, electronic device, etc.) is formed on the c-plane of a group III nitride semiconductor crystal, the internal quantum is caused by the piezo electric field. Efficiency is reduced. Therefore, attempts have been made to form the device on a so-called semi-polar surface (a surface different from the polar surface and the non-polar surface).

Further, related techniques are disclosed in Patent Document 3 and Patent Document 4. As disclosed in Patent Documents 3 and 4, a crystal piece having a semipolar surface as a main surface is cut out from a bulk group III nitride semiconductor crystal, and the crystal pieces are joined to form a semipolar surface. Attempts have been made to manufacture group III nitride semiconductor crystals with the above as the main surface.

Further, the related technique is disclosed in Patent Document 5. As disclosed in Patent Document 5, an attempt has been made to manufacture a GaN-based semiconductor optical device having a (20-21) plane, which is a semi-polar plane inclined in the m-axis direction from the c plane, as a main plane. ..

Japanese Unexamined Patent Publication No. 2012-160755 Japanese Unexamined Patent Publication No. 2016-12717 Japanese Unexamined Patent Publication No. 2010-13298 Japanese Unexamined Patent Publication No. 2013-82628 Japanese Unexamined Patent Publication No. 2012-15555

The conventional group III nitride semiconductor substrate having a semi-polar surface as the main surface has a relatively large surface roughness on the main surface. If the surface roughness of the main surface of the substrate is large, the quality of the devices (eg, optical devices, electronic devices, etc.) formed on the surface of the substrate deteriorates.

An object of the present invention is to improve the quality of a device formed on a group III nitride semiconductor substrate having a semi-polar surface as a main surface.

According to the present invention
It is composed of a group III nitride semiconductor, the main surface is a semipolar surface, and the surface roughness RMS measured in an area of 5 μm × 5 μm square of the main surface is 0.05 nm or more and 1.50 nm or less. A physical semiconductor substrate is provided.

Further, according to the present invention,
The preparatory process for preparing the base board and
A group III nitride semiconductor layer forming step of epitaxially growing a group III nitride semiconductor on the main surface of the base substrate by the HVPE method to form a group III nitride semiconductor layer.
A cutting process for cutting out a group III nitride semiconductor substrate from the group III nitride semiconductor layer, and
The processing process for processing the surface of the group III nitride semiconductor substrate and
Have,
The base substrate is
Includes a first layer composed of group III nitride semiconductors
The main surface of the first layer becomes the main surface of the base substrate.
The main surface of the first layer is represented by the Miller index (hkml), where l is a semi-polar surface less than 0.
X-rays were incident parallel to the main surface of the first layer in parallel with the m-axis of the group III nitride semiconductor crystal, and the angle formed by the incident direction of the X-rays and the main surface was scanned and measured {11-22. } A method for manufacturing a group III nitride semiconductor substrate is provided in which the half price width of the XRC (X-ray Rocking Curve) with respect to the plane is 500 arcsec or less.

According to the present invention, it is possible to improve the quality of a device formed on a group III nitride semiconductor substrate having a semi-polar surface as a main surface.

The above-mentioned objectives and other objectives, features and advantages are further clarified by the preferred embodiments described below and the accompanying drawings below.

It is a flowchart which shows an example of the process flow of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a process drawing which shows an example of the process flow of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a flowchart which shows an example of the process flow of the preparation process S10 of this embodiment. It is a flowchart which shows an example of the process flow of the group III nitride semiconductor layer formation step S20 of this embodiment. It is a process diagram which shows an example of the process flow of the group III nitride semiconductor layer formation step S20 of this embodiment. It is a figure which shows the feature of the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the characteristic of the group III nitride semiconductor substrate of the Example of this Embodiment. It is a figure which shows the feature of the group III nitride semiconductor substrate of the comparative example. It is a figure which shows the characteristic of the group III nitride semiconductor substrate of the Example of this Embodiment. It is a figure which shows the feature of the group III nitride semiconductor substrate of the comparative example.

<Prerequisites>
Hereinafter, embodiments of the group III nitride semiconductor substrate of the present invention and the method for manufacturing the group III nitride semiconductor substrate will be described with reference to the drawings. It should be noted that the figure is merely a schematic diagram for explaining the configuration of the invention, and the size, shape, number, ratio of different member sizes, etc. of each member are not limited to those shown.

In the present embodiment, a "semipolar surface represented by the Miller index (hkml) and in which l exceeds 0" may be referred to as a "semipolar surface on the Ga polar side". Further, a "semipolar surface represented by the Miller index (hkml) and having l less than 0" may be referred to as a "semipolar surface on the N-polar side".

<Overview>
First, the outline of the present embodiment will be described. In the present embodiment, it is composed of a group III nitride semiconductor, the main surface is a semipolar surface, and the surface roughness RMS measured in an area of 5 μm × 5 μm square on the main surface is 0.05 nm or more and 1.50 nm or less. A group III nitride semiconductor substrate is provided. By forming a device (eg, optical device, electronic device, etc.) on a group III nitride semiconductor substrate having a relatively small surface roughness of the main surface in this way, the conventional surface roughness of the main surface is relatively large. The quality of the device is improved as compared with the case where the device is formed on the group III nitride semiconductor substrate.

In this embodiment, "the main surface, which is an exposed surface, is a semipolar surface on the N-polar side, and a group III nitride semiconductor is epitaxially grown on a base substrate including a group III nitride semiconductor layer having good crystallinity. , "The substrate is manufactured with the {11-2X} surface represented by the mirror index or the surface having an off angle within 1 ° with respect to the {11-2X} surface as the main surface (X is an integer of 1 or more). ) ”({11-2X} surface is preferable, but an off angle of about 1 ° or less is allowed). A group III nitride semiconductor substrate having a good surface roughness is realized.

<Manufacturing method of group III nitride semiconductor substrate>
Next, an example of the method for manufacturing the group III nitride semiconductor substrate of the present embodiment will be described in detail.

As shown in FIG. 1, the method for manufacturing a group III nitride semiconductor substrate of the present embodiment includes a preparation step S10, a group III nitride semiconductor layer forming step S20, a cutting step S30, and a processing step S40. ..

The outline of each process will be described. In the preparation step S10, the base substrate 1 is prepared as shown in FIG. 2 (1). In the group III nitride semiconductor layer forming step S20, the group III nitride semiconductor layer 2 is formed on the base substrate 1 as shown in FIG. 2 (2). In the cutting step S30, a part or all of the group III nitride semiconductor layer 2 is cut out as a group III nitride semiconductor substrate. In the processing step S40, the surface of the group III nitride semiconductor substrate cut out in the cutting step S30 is processed. Hereinafter, each step will be described in detail.

"Preparation process S10"
In the preparation step S10, a base substrate in which a group III nitride semiconductor layer and another layer (eg, a buffer layer, a sapphire substrate, etc.) are laminated or a base substrate composed of a single layer of the group III nitride semiconductor layer is prepared. ..

In the group III nitride semiconductor layer included in the base substrate, the main surface, which is an exposed surface, is a semi-polar surface on the N-polar side. The group III nitride semiconductor layer has good crystallinity. Specifically, X-rays are incident on the main surface of the group III nitride semiconductor layer parallel to the m-axis of the group III nitride semiconductor crystal, and the angle formed by the incident direction of the X-rays and the main surface is scanned. The half-price range of XRC with respect to the measured {11-22} plane is 500 arcsec or less.

Further, X-rays are incident on the main surface of the group III nitride semiconductor layer in parallel with the projection axis obtained by projecting the c-axis of the group III nitride semiconductor crystal onto the main surface, and the incident direction of the X-rays and the main surface thereof. The half-value width of XRC with respect to the {11-22} plane measured by scanning the angle formed is 500 arcsec or less.

The maximum diameter of the group III nitride semiconductor layer is, for example, Φ50 mm or more and Φ6 inch or less. The thickness of the group III nitride semiconductor layer is, for example, 50 nm or more and 500 μm or less.

Here, a method for manufacturing a base substrate having the above-mentioned characteristics will be described. The flowchart of FIG. 3 shows an example of the processing flow of the preparation step S10. As shown in the figure, the preparation step S10 includes a substrate preparation step S11, a heat treatment step S12, a prelude step S13, a buffer layer forming step S14, and a growth step S15.

In the substrate preparation step S11, a sapphire substrate is prepared. The diameter of the sapphire substrate is, for example, 1 inch or more. The thickness of the sapphire substrate is, for example, 250 μm or more.

The plane orientation of the main surface of the sapphire substrate is one of a plurality of elements that control the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the plane orientation. The relationship between this element and the plane orientation of the growth surface of the group III nitride semiconductor layer is shown in the following examples. In the substrate preparation step S11, a sapphire substrate whose main surface has a desired plane orientation is prepared.

The main surface of the sapphire substrate is, for example, a {10-10} surface or a surface in which the {10-10} surface is inclined by a predetermined angle in a predetermined direction.

A surface in which the {10-10} plane is tilted in a predetermined direction by a predetermined angle is, for example, tilted in any direction in any direction from 0 ° to 0.5 ° or less. It may be a surface.

Further, the surface in which the {10-10} plane is tilted by a predetermined angle in a predetermined direction is any one of those larger than 0 ° and less than 10.5 ° in the direction in which the {10-10} plane is parallel to the a plane. It may be a surface inclined at an angle. Alternatively, the surface in which the {10-10} plane is tilted by a predetermined angle in a predetermined direction is any one of those greater than 0 ° and 10.5 ° or less in the direction in which the {10-10} plane is parallel to the a plane. It may be a surface inclined at an angle. For example, a surface in which the {10-10} plane is tilted by a predetermined angle in a predetermined direction is 0.5 ° or more and 1.5 ° or less, 1.5 ° in a direction in which the {10-10} plane is parallel to the a plane. A surface inclined at any of the following angles: 2.5 ° or more, 4.5 ° or more and 5.5 ° or less, 6.5 ° or more and 7.5 ° or less, and 9.5 ° or more and 10.5 ° or less. May be.

The heat treatment step S12 is performed after the substrate preparation step S11. In the heat treatment step S12, the sapphire substrate is heat-treated under the following conditions.

Temperature: 800 ° C. or higher 930 ° C. or less pressure: 30 torr or more 760torr following heat treatment time: 5 minutes or more 20 minutes or less carrier gas: _{H 2,} or, _{H 2} and _N 2 _{(H 2} ratio 0% to 100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (However, this is not limited to this because the supply amount varies depending on the size of the growth device).

The heat treatment for the sapphire substrate may be performed while performing the nitriding treatment or may be performed without performing the nitriding treatment. When the heat treatment is performed while performing the nitriding treatment, for example, NH _{3 of} 0.5 slm or more and 20 slm or less is supplied onto the sapphire substrate (however, the supply amount varies depending on the size of the growth apparatus and is not limited to this). .. Further, when the heat treatment is performed without performing the nitriding treatment, NH ₃ is not supplied during the heat treatment.

The presence or absence of nitriding treatment during the heat treatment may be one of a plurality of factors that control the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate. The relationship between this element and the plane orientation of the growth surface of the group III nitride semiconductor layer is shown in the following examples.

The temperature at the time of heat treatment of 800 ° C. or higher and 930 ° C. or lower is a temperature condition for forming a group III nitride semiconductor layer having a main surface (growth surface) of a semi-polar surface on the N-polar side and having good crystallinity. ..

The pre-flow step S13 is performed after the heat treatment step S12. In the pre-flow step S13, the metal-containing gas is supplied onto the main surface of the sapphire substrate under the following conditions. The pre-flow step S13 may be performed, for example, in a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus.

Temperature: 500 ° C or more and 1000 ° C or less Pressure: 30 torr or more and 200 torr or less Trimethylaluminum supply amount, supply time: 20 cm or more and 500 ccm or less, 1 second or more and 60 seconds or less Carrier gas: H ₂ or H ₂ and N ₂ (H ₂ ratio) 0-100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (However, the gas supply amount is not limited to this because it varies depending on the size and configuration of the growth device).

The above conditions are for supplying trimethylaluminum and triethylaluminum, which are organic metal raw materials, as the metal-containing gas. In this step, a metal-containing gas containing another metal is supplied instead of trimethylaluminum triethylaluminum, and another metal film such as a titanium film, a vanadium film or a copper film is used instead of the aluminum film on the main surface of the sapphire substrate. It may be formed on top. In addition, other hydrocarbon films such as aluminum carbide, titanium carbide, vanadium carbide and copper carbide, which are reaction films with hydrocarbon compounds such as methane, ethylene and ethane produced from organic metal raw materials, are placed on the main surface of the sapphire substrate. It may be formed.

By the pre-flow step S13, a metal film and a metal carbide film are formed on the main surface of the sapphire substrate. The presence of the metal film is a condition for reversing the polarity of the crystals grown on it. That is, in the implementation of the pre-flow step S13, among a plurality of elements for setting the surface orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate to be the semi-polar surface on the N-polar side. It is one of.

The buffer layer forming step S14 is performed after the pre-flow step S13. In the buffer layer forming step S14, the buffer layer is formed on the main surface of the sapphire substrate. The thickness of the buffer layer is, for example, 20 nm or more and 300 nm or less.

The buffer layer is, for example, an AlN layer. For example, an AlN crystal may be epitaxially grown under the following conditions to form a buffer layer.

Growth method: MOCVD method Growth temperature: 800 ° C or more and 950 ° C or less Pressure: 30 torr or more and 200 torr or less Trimethylaluminum supply amount: 20 cm cm or more and 500 cm or less NH ₃ supply amount: 0.5 slm or more and 10 slm or less Carrier gas: H ₂ or H ₂ And N ₂ (H ₂ ratio 0-100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (However, the gas supply amount is not limited to this because it varies depending on the size and configuration of the growth device).

The growth condition of the buffer layer forming step S14 may be one of a plurality of elements that control the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate. The relationship between this element and the plane orientation of the growth surface of the group III nitride semiconductor layer is shown in the following examples.

Further, the growth conditions in the buffer layer forming step S14 (relatively low predetermined growth temperature, specifically 800 to 950 ° C., and relatively low pressure) are for growing AlN while maintaining the N-polar side. It becomes a condition. That is, the growth conditions in the buffer layer forming step S14 are a plurality of elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate to be the semi-polar surface on the N-polar side. It is one of them.

The growth step S15 is performed after the buffer layer forming step S14. In the growth step S15, a group III nitride semiconductor crystal (eg, GaN crystal) is epitaxially grown on the buffer layer under the following growth conditions, and the growth plane becomes a predetermined plane orientation (semipolar plane on the N polar side). It forms a group III nitride semiconductor layer. The thickness of the group III nitride semiconductor layer is, for example, 1 μm or more and 20 μm or less.

Growth method: MOCVD method Growth temperature: 800 ° C or higher and 1025 ° C or lower
Pressure: 30 torr or more and 200 torr or less TMGa supply amount: 25 sccm or more and 1000 sccm or less NH3 supply amount: 1 slm or more and 20 slm or less Carrier gas: H ₂ or H ₂ and N ₂ (H ₂ ratio 0 to 100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (However, the gas supply amount is not limited to this because it varies depending on the size and configuration of the growth device).
Growth rate: 10 μm / h or more

The growth conditions (relatively low growth temperature, relatively low pressure, relatively fast growth rate) in the growth step S15 are conditions for growing GaN while maintaining the N-polar side. That is, the growth condition in the growth step S15 is among a plurality of elements for setting the plane orientation of the growth plane of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate to be the semipolar plane on the N-polar side. It is one of.

By the preparation step S10 having the substrate preparation step S11, the heat treatment step S12, the preflow step S13, the buffer layer forming step S14, and the growth step S15 described above, the base substrate having the above-mentioned characteristics, specifically, group III nitride. A base substrate in which a physical semiconductor layer and another layer (eg, a buffer layer, a sapphire substrate, etc.) are laminated can be obtained. Then, by removing the other layer from the laminated body, a base substrate made of a single layer of the group III nitride semiconductor layer can be obtained.

The means for removing the other layers is not particularly limited. For example, the stress caused by the difference in the coefficient of linear expansion between the sapphire substrate and the group III nitride semiconductor layer may be used to separate them. Then, the buffer layer may be removed by polishing, etching or the like.

As another example of removal, a release layer may be formed between the sapphire substrate and the buffer layer. For example, a carbon layer in which carbides (aluminum carbide, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide or tantalum carbide) are dispersed, and carbides (aluminum carbide, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide or tantalum carbide). After forming the laminate of the layers on the sapphire substrate, the layer subjected to the carbide treatment may be formed as a release layer.

After forming the buffer layer and the group III nitride semiconductor layer on such a peeling layer, when the laminate is heated at a temperature higher than the heating temperature at which the group III nitride semiconductor layer is formed, the peeling layer is formed. It can be separated into a portion on the sapphire substrate side and a portion on the group III nitride semiconductor layer side with the portion of Then, the buffer layer or the like may be removed from the portion on the side of the group III nitride semiconductor layer by polishing, etching or the like.

As shown in the following examples, when a group III nitride semiconductor is epitaxially grown on a semi-polar plane on the Ga polar side, the crystallinity deteriorates as the thickness of the group III nitride semiconductor layer increases. As a result, the thicker the III-nitride semiconductor layer, the larger the half-value width of XRC with respect to the {11-22} plane. Therefore, when a group III nitride semiconductor is epitaxially grown on a semi-polar plane on the Ga polar side, it is difficult to produce a group III nitride semiconductor layer having good crystallinity and a thick film.

On the other hand, as shown in the following examples, when the group III nitride semiconductor is epitaxially grown on the semi-polar plane on the N-polar side, the crystallinity hardly changes even if the thickness of the group III nitride semiconductor layer is increased. Therefore, in the case of the present embodiment in which the group III nitride semiconductor is epitaxially grown on the semi-polar plane on the N-polar side, the crystallinity is good as described above and the thick film (eg, 100 μm or more) is formed in the group III nitride. A physical semiconductor layer can be manufactured.

As another example of the method for manufacturing a base substrate composed of a single layer of a group III nitride semiconductor layer, a laminate in which a sapphire substrate, a buffer layer and a group III nitride semiconductor layer are laminated in this order was manufactured by the flow shown in FIG. Later, the group III nitride semiconductor may be grown into a thick film on the laminate (on the group III nitride semiconductor layer), for example, by the HVPE (Hydride Vapor Phase Epitaxy) method to form the HVPE layer. As a result, an HVPE layer of a group III nitride semiconductor having an exposed surface as a semi-polar surface on the N-polar side is obtained on the laminated body. The growth conditions for epitaxially growing a group III nitride semiconductor by the HVPE method are not particularly limited. Can be made to. Then, a base substrate made of a single layer of the group III nitride semiconductor layer may be obtained by slicing from the HVPE layer.

"Group III nitride semiconductor layer forming step S20"
Returning to FIG. 1, in the group III nitride semiconductor layer forming step S20, the group III nitride semiconductor is epitaxially grown on the main surface of the base substrate by the HVPE method to form the group III nitride semiconductor layer. The flowchart of FIG. 4 shows an example of the processing flow of the group III nitride semiconductor layer forming step S20. As shown in the figure, the group III nitride semiconductor layer forming step S20 includes a fixing step S21, a first growth step S22, a cooling step S23, and a second growth step S24.

In the fixing step S21, the base substrate is fixed to the susceptor. For example, the base substrate 10 as shown in FIG. 5 (1) is fixed to the susceptor 20 as shown in FIG. 5 (2). The illustrated base substrate 10 is a laminate including a group III nitride semiconductor layer 12 and another layer 11. The other layer 11 includes a sapphire substrate, a buffer layer, and the like. The base substrate 10 may be a single layer of the group III nitride semiconductor layer 12.

The susceptor 20 has a property of not being deformed by the warping force of the base substrate 10 which can be warped by heating in the first growth step S22 and the second growth step S24. Examples of such a susceptor 20 include, but are not limited to, a carbon susceptor, a silicon carbide coated carbon susceptor, a boron nitride coated carbon susceptor, a quartz susceptor, and the like.

Next, a method of fixing the base substrate 10 to the susceptor 20 will be described. In this embodiment, as shown in FIG. 5 (2), the back surface of the base substrate 10 (exposed surface of the other layer 11) is fixed to the surface of the susceptor 20. This suppresses the deformation of the base substrate 10. As a method of fixing, a method of not peeling due to heating in the first growth step S22 or the second growth step S24, the warping force of the base substrate 10 which can be warped by the heating, or the like is required. For example, a method of fixing using an adhesive such as alumina-based, carbon-based, zirconia-based, silica-based, and nitride-based is exemplified.

Returning to FIG. 4, in the first growth step S22, as shown in FIG. 5 (3), the HVPE method is performed on the main surface of the group III nitride semiconductor layer 12 with the base substrate 10 fixed to the susceptor 20. The group III nitride semiconductor is grown in. As a result, the first growth layer 30 made of a single crystal group III nitride semiconductor is formed. For example, GaN is epitaxially grown under the following growth conditions to form a GaN layer (first growth layer 30).

Growth temperature: 900 ° C to 1100 ° C
Growth time: 1h-50h
V / III ratio: 1 to 20
Growth film thickness: 100 μm to 10 mm

In the first growth step S22, a polycrystalline group III nitride semiconductor is formed along the side surface of the laminate including the susceptor 20, the base substrate 10, and the first growth layer 30. The polycrystalline group III nitride semiconductor adheres to all or most of the side surfaces of the laminate. The attached polycrystalline group III nitride semiconductors are connected to each other to form an annular shape. Then, the laminate is held inside the cyclic polycrystal III-nitride semiconductor.

In the first growth step S22, a polycrystalline group III nitride semiconductor may be formed on the back surface of the susceptor 20 in addition to the side surface of the laminate. The polycrystalline group III nitride semiconductor adheres to all or most of the side surface of the laminate and the back surface of the susceptor 20. The attached polycrystalline group III nitride semiconductors are connected to each other to form a cup-like shape. Then, the laminate is held inside the cup-shaped polycrystalline group III nitride semiconductor.

Returning to FIG. 4, in the cooling step S23, the laminate including the susceptor 20, the base substrate 10, and the first growth layer 30 is cooled. The purpose of cooling here is to generate cracks in the first growth layer 30 by utilizing the strain (stress) generated due to the difference in linear expansion coefficient between the first growth layer 30 and the sapphire substrate 11. So, it is to relieve the stress. It is desired that the stress be relaxed before the second growth step S24. If the purpose can be achieved, the cooling method is not particularly limited. For example, after the first growth step S22, the laminate may be taken out of the HVPE apparatus and cooled to room temperature.

As shown in FIG. 5 (3), cracks (cracks, cracks, etc.) 31 are present in the first growth layer 30 after the cooling step S23. The crack 31 may be present on the surface of the first growth layer 30, as shown. The crack 31 may be generated during the first growth step S22 or may be generated during the cooling step S23.

Returning to FIG. 4, in the second growth step S24, as shown in FIG. 5 (4), the base substrate 10 is fixed to the susceptor 20 and is placed on the first growth layer 30 by the HVPE method III. Grow group nitride semiconductors. As a result, a second growth layer 40 composed of a single crystal group III nitride semiconductor is formed. For example, GaN is epitaxially grown under the following growth conditions to form a GaN layer (second growth layer 40). The growth conditions for forming the first growth layer 30 and the growth conditions for forming the second growth layer 40 may be the same or different.

Growth temperature: 900 ° C to 1100 ° C
Growth time: 1h-50h
V / III ratio: 1 to 20
Growth film thickness: 100 μm to 10 mm

In the second growth step S24, the second growth layer 40 is placed on the first growth layer 30 in a state where the cyclic polycrystalline group III nitride semiconductor formed in the first growth step S22 remains. Form. The purpose of leaving the cyclic polycrystalline group III nitride semiconductor is to suppress the separation by holding the first growth layer 30 which can be separated into a plurality of portions due to the crack 31 from the outer periphery. .. If the first growth layer 30 is separated into a plurality of portions, the plane orientation deviation, handleability, workability, and the like of each of the plurality of portions deteriorate. In addition, some parts may be lost or shattered, which may make it impossible to reproduce the original shape. According to the present embodiment, the plane orientation deviation and separation can be suppressed, so that the inconvenience can be suppressed.

The polycrystalline group III nitride semiconductor formed in the first growth step S22 may be left as it is, but it is sufficient if the above object can be achieved, and the polycrystal formed in the first growth step S22 is not always present. It is not necessary to leave all of the crystalline group III nitride semiconductors. That is, a part of the polycrystalline group III nitride semiconductor may be removed.

Also in the second growth step S24, a polycrystalline group III nitride semiconductor is formed. The polycrystalline group III nitride semiconductor can be formed along the side surface of the laminate including the susceptor 20, the base substrate 10, the first growth layer 30 and the second growth layer 40, and the back surface of the susceptor 20.

Further, in the second growth step S24, the group III nitride semiconductor is grown on the surface of the first growth layer 30 in which the crack 31 is present by the HVPE method to form the second growth layer 40. In this case, the growth surface (the surface of the first growth layer 30) becomes discontinuous at the crack 31 portion. The group III nitride semiconductors grown from each of the first surface region and the second surface region separated from each other with the crack 31 as a boundary are joined to each other and integrated as the growth progresses.

"Cutout process S30"
Returning to FIG. 1, in the cutting step S30, the group III nitride semiconductor substrate is cut out from the group III nitride semiconductor layer (second growth layer 40) formed in the group III nitride semiconductor layer forming step S20. In the cutting step S30, a group III nitride semiconductor substrate whose main surface is a {11-2X} surface or a surface having an off angle within 1 ° with respect to the {11-2X} surface is cut out (X is 1 or more). Integer). The main surface on the opposite side of the group III nitride semiconductor substrate is a {-112-X} surface or a surface having an off angle within 1 ° with respect to the {-1-12-X} surface.

For example, as shown in FIG. 5 (5), a laminate including the susceptor 20, the base substrate 10, the first growth layer 30 and the second growth layer 40 is sliced and at least a part of the second growth layer 40. May be separated from the susceptor 20 to form a group III nitride semiconductor substrate. A plurality of group III nitride semiconductor substrates may be obtained by slicing at least a part of the second growth layer 40 separated from the susceptor 20. Further, in addition to slicing, at least a part of the second growth layer 40 may be separated from the susceptor 20 by using a method such as grinding, polishing, burning, decomposition, and melting.

"Processing process S40"
Returning to FIG. 1, in the processing step S40, the surface of the group III nitride semiconductor substrate cut out in the cutting step S30 is processed. For example, the surface of a group III nitride semiconductor substrate is flattened by using a surface flattening technique such as CMP (chemical mechanical polishing).

<Structure of group III nitride semiconductor substrate>
Next, the configuration of the group III nitride semiconductor substrate (hereinafter, referred to as “the group III nitride semiconductor substrate of the present embodiment”) manufactured by the method for manufacturing the group III nitride semiconductor substrate will be described.

The group III nitride semiconductor substrate of the present embodiment is composed of a group III nitride semiconductor. The main surface of the group III nitride semiconductor substrate of the present embodiment is a semi-polar surface, which is a surface having an off angle within 1 ° with respect to the {11-2X} surface or the {11-2X} surface (X). Is an integer greater than or equal to 1). The other main surface, which has a front-to-back relationship with the main surface, is a {-112-X} surface or a surface having an off angle within 1 ° with respect to the {-112-X} surface. Become. Hereinafter, the main surface having an off angle within 1 ° with respect to the {11-2X} surface or the {11-2X} surface is referred to as a “main surface on the Ga polar side”.

The group III nitride semiconductor substrate of the present embodiment has a diameter of 10 mm or more and 6 inches or less, and a thickness of 250 μm or more and 2 mm or less.

The group III nitride semiconductor substrate of the present embodiment is characterized in that the surface roughness of the main surface on the Ga polar side is smaller than the surface roughness of the main surface of the conventional semi-polar substrate.

Specifically, the surface roughness RMS of the main surface on the Ga polar side has a measurement result of 0.05 nm or more and 1.50 nm or less in an area of 5 μm × 5 μm square at the center of the main surface, and the central portion of the main surface. The measurement result in the area of 1 μm × 1 μm square is 0.05 nm or more and 1.50 nm or less. The method for measuring RMS is an atomic force microscope (AFM).

Further, the surface roughness Ra of the main surface on the Ga polar side is 0.05 nm or more and 1.20 nm or less in the area of the central portion of the main surface of 5 μm × 5 μm square, and the central portion of the main surface is 1 μm × 1 μm. The measurement result in the corner area is 0.05 nm or more and 1.20 nm or less. The method for measuring Ra is AFM.

The surface roughness Rv of the main surface on the Ga polar side is -10.0 nm or more and -0.05 nm or less in the area of 5 μm × 5 μm square in the center of the main surface, and 1 μm in the center of the main surface. The measurement result in the area of × 1 μm square is −6.0 nm or more and −0.05 nm or less. The method for measuring Rv is AFM.

Further, the surface roughness Rp of the main surface on the Ga polar side is 0.05 nm or more and 5.0 nm or less in the area of the central portion of the main surface of 5 μm × 5 μm square, and the central portion of the main surface is 1 μm × 1 μm. The measurement result in the corner area is 0.05 nm or more and 5.0 nm or less. The method for measuring Rp is AFM.

Also, the dark spot density in CL (Cathodoluminescence) image of the main surface of the Ga-polar side is 5 × 10 ⁶ or less. Dark spots indicate defects. That is, the surface defects of the group III nitride semiconductor substrate of the present embodiment are sufficiently reduced in this way. The density of dark spots in an area of 50 μm × 50 μm square at the center of the main surface was calculated.

<First evaluation>
In the first evaluation, the group III is satisfied by satisfying all of the above-mentioned "multiple elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer of the base substrate to be the semi-polar surface on the N-polar side". It is shown that the plane orientation of the growth plane of the nitride semiconductor layer can be set to the semi-polar plane on the N-polar side. Further, when at least one of the above-mentioned "multiple elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer to be the semi-polar surface on the N-polar side" is not satisfied, the group III nitride It is shown that the plane orientation of the growth plane of the semiconductor layer is the semi-polar plane on the Ga polar side.

First, a sapphire substrate was prepared, which is a surface inclined by 2 ° in a direction in which the surface orientation of the main surface is parallel to the a surface from the m surface ((10-10) surface). The sapphire substrate had a thickness of 430 μm and a diameter of 2 inches.

Then, the heat treatment step S12 was carried out on the prepared sapphire substrate under the following conditions.

Temperature: 1000-1050 ° C
Pressure: 100torr
Carrier gas: H ₂ , N ₂
Heat treatment time: 10 minutes or 15 minutes Carrier gas supply: 15 slm

In the heat treatment step S12, 20 slm of NH ₃ was supplied and nitriding treatment was performed.

Then, the pre-emption step S13 was performed under the following conditions.

Temperature: 800-930 ° C
Pressure: 100torr
Trimethylaluminum supply amount, supply time: 90 sccm, 10 seconds Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

Then, the buffer layer forming step S14 was performed under the following conditions to form an AlN layer.

Growth method: MOCVD method Growth temperature: 800 to 930 ° C.
Pressure: 100torr
Trimethylaluminum supply: 90sccm
NH ₃ supply amount: 5 slm
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

Then, the growth step S15 was carried out under the following conditions to form a group III nitride semiconductor layer.

Growth method: MOCVD method Pressure: 100torr
TMGa supply: 50-500sccm (continuous change)
NH ₃ supply amount: 5 to 10 slm (continuous change)
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm
Growth rate: 10 μm / h or more

The growth temperature of the first sample was controlled to 900 ° C. ± 25 ° C., and the growth temperature of the second sample was controlled to 1050 ° C. ± 25 ° C. That is, the first sample is a sample that satisfies all of the above-mentioned "a plurality of elements for making the plane orientation of the growth plane of the group III nitride semiconductor layer a semi-polar plane on the N-polar side". The second sample is a part of the above-mentioned "multiple elements for making the plane orientation of the growth surface of the group III nitride semiconductor layer a semi-polar surface on the N-polar side" (growth temperature in the growth step S15). ) Is not satisfied.

The plane orientation of the growth plane of the group III nitride semiconductor layer of the first sample is 5.0 ° in the −a plane direction from the (-1-12-4) plane and in the direction parallel to the m plane. The surface was inclined by 5 ° or less. On the other hand, the plane orientation of the growth plane of the group III nitride semiconductor layer of the second sample is 5.0 ° in the a-plane direction and 8.5 ° in the direction parallel to the m-plane from the (11-24) plane. It was an inclined surface below. That is, depending on whether or not the above-mentioned "multiple elements for making the plane orientation of the growth surface of the group III nitride semiconductor layer a semi-polar plane on the N-polar side" is satisfied, the plane orientation of the growth surface is Ga polarity. It can be seen that it is possible to adjust whether it becomes N-polarity or N-polarity.

It should be noted that the present inventors do not satisfy the other part of the above-mentioned "plurality of elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer to the semi-polar plane on the N-polar side". In this case, and even when all of them are not satisfied, it is confirmed that the plane orientation of the growth surface has Ga polarity.

<Second evaluation>
In the second evaluation, the plane orientation of the growth surface of the group III nitride semiconductor layer is adjusted by adjusting the above-mentioned "multiple elements for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer". Show that you can.

First, we prepared a plurality of sapphire substrates with various surface orientations. The sapphire substrate had a thickness of 430 μm and a diameter of 2 inches.

Then, the heat treatment step S12 was performed on each of the prepared sapphire substrates under the following conditions.

Temperature: 1000-1050 ° C
Pressure: 200torr
Heat treatment time: 10 minutes Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

Samples were prepared with different presence or absence of nitriding treatment during heat treatment. _{Specifically, both a sample in which 20 slm of NH 3} was supplied during the heat treatment and subjected to the nitriding treatment and a sample in which NH ₃ was not supplied during the heat treatment and the nitriding treatment was not performed were prepared.

Then, the pre-emption step S13 was performed under the following conditions.

Temperature: 880-930 ° C
Pressure: 100torr
Trimethylaluminum supply amount, supply time: 90 sccm, 10 seconds Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

In addition, both a sample in which the pre-emption step S13 was performed and a sample in which the pre-flow step S13 was not performed were prepared.

Then, a buffer layer (AlN buffer layer) having a thickness of about 150 nm was formed on the main surface (exposed surface) of the sapphire substrate under the following conditions.

Growth method: MOCVD method Pressure: 100torr
V / III ratio: 5184
TMAl supply amount: 90ccm
NH ₃ supply amount: 5 slm
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

The growth temperature was different for each sample in the range of 700 ° C. or higher and 1110 ° C. or lower.

Then, a group III nitride semiconductor layer (GaN layer) having a thickness of about 15 μm was formed on the buffer layer under the following conditions.

Growth method: MOCVD method Growth temperature: 900 to 1100 ° C
Pressure: 100torr
V / III ratio: 321
TMGa supply amount: 50-500ccm (ramp up)
NH ₃ supply amount: 5 to 10 slm (ramp up)
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

As described above, the group III nitride semiconductor substrate 1 in which the sapphire substrate, the buffer layer, and the group III nitride semiconductor layer are laminated in this order was manufactured.

Tables 1 to 7 show the relationship between "a plurality of elements for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer" and the plane orientation of the growth surface of the group III nitride semiconductor layer.

In the column of "sapphire main surface" in the table, the surface orientation of the main surface of the sapphire substrate is shown. In the column of "nitriding treatment at the time of temperature rise", the presence / absence (“presence” or “without”) of the nitriding treatment at the time of temperature rise in the heat treatment step 1S0 is indicated. In the column of "presence / absence of trimethylaluminum pre-leading process", the presence / absence ("presence" or "absence") of the trimethylaluminum pre-leading process is indicated. In the column of "AlN buffer growth temperature", the growth temperature in the buffer layer forming step is shown. In the column of "GaN growth temperature", the growth temperature in the GaN layer forming step is shown. In the column of "growth surface of group III nitride semiconductor layer", the plane orientation of the growth surface of the group III nitride semiconductor layer is shown.

According to the result, by adjusting the above-mentioned "multiple elements for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer", the growth surface of the group III nitride semiconductor layer can be set on the Ga polar side. It can be seen that it can be adjusted in the semi-polar plane. Then, based on the result of the first evaluation and the result of the second evaluation, "a plurality of elements for setting the plane orientation of the growth plane of the group III nitride semiconductor layer to the semipolar plane on the N-polar side". By adjusting "multiple factors for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer" after satisfying all of the above, the growth surface of the group III nitride semiconductor layer can be set to the N-polar side. It can be seen that it can be adjusted in the semi-polar plane.

<Third evaluation>
The crystallinity of the sample (group III nitride semiconductor layer of the base substrate) prepared by this method was evaluated. Three types of samples were prepared. Sample A was produced by the production method of the present embodiment (see the flow in FIG. 3), and was grown with the {-1-12-3} plane as the growth plane. Samples B and C are comparative samples, and sample B is grown with the {10-10} plane as the growth plane. Further, the sample C was grown with the {11-22} plane as the growth plane.

FIG. 6 shows the XRC half width with respect to the {11-22} plane when X-rays are incident parallel to the projection axis of the c-axis of the group III nitride semiconductor crystal at various GaN film thicknesses for each sample. However, in the sample C whose main surface is the {11-23} surface, X-ray diffraction of the {11-23} surface cannot be obtained due to the extinction rule, so the XRC half width of the {11-22} surface was measured.

From FIG. 6, it can be seen that in sample A, the XRC half-value width hardly changes even if the film thickness of the GaN layer increases. On the other hand, in Samples B and C, it can be read that the XRC half-value width tends to increase as the film thickness of the GaN layer increases.

<Fourth evaluation>
The crystallinity of the sample prepared by this method was evaluated. Sample D (Example) was produced by the production method of this embodiment (see the flow of FIG. 3), and the details thereof are as follows.

First, a sapphire substrate was prepared, which is a surface inclined by 2 ° in a direction in which the surface orientation of the main surface is parallel to the a surface from the m surface ((10-10) surface). The sapphire substrate had a thickness of 430 μm and a diameter of 2 inches.

Then, the heat treatment step S12 was carried out on the prepared sapphire substrate under the following conditions.

Temperature: 800-930 ° C
Pressure: 100torr
Carrier gas: H ₂ , N ₂
Heat treatment time: 10 minutes Carrier gas supply: 4 slm

In the heat treatment step S12, 2 slm of NH ₃ was supplied and nitriding treatment was performed.

Then, the pre-emption step S13 was performed under the following conditions.

Temperature: 800-930 ° C
Pressure: 100torr
Trimethylaluminum supply amount, supply time: 50 sccm, 10 seconds Carrier gas: H ₂ , N ₂
Carrier gas supply: 4 slm

Then, the buffer layer forming step S14 was performed under the following conditions to form an AlN layer.

Growth method: MOCVD method Growth temperature: 800 to 930 ° C.
Pressure: 100torr
Trimethylaluminum supply: 50 sccm
NH ₃ supply amount: 2 slm
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

Then, the growth step S15 was carried out under the following conditions to form a group III nitride semiconductor layer.

Growth method: MOCVD method Growth temperature: 900 ° C ± 25 ° C
Pressure: 100torr
TMGa supply: 50-500sccm (continuous change)
NH ₃ supply amount: 5 to 10 slm (continuous change)
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm
Growth rate: 10 μm / h or more

Sample E (comparative example) was prepared by the same method as sample D, but differs in the following points.

In the heat treatment step S12, the heat treatment temperature was 1000 ° C. to 1050 ° C., and the carrier gas flow rate was 15 slm. The NH ₃ supply amount was set to 20 slm.

In the prelude step S13, the trimethylaluminum supply amount was 90 sccm and the carrier gas flow rate was 15 slm.

In the buffer layer forming step S14, the supply amount of trimethylaluminum was 90 sccm, and the _{supply amount of NH 3} was 5 slm.

X-ray pole figures were measured for each of Sample D and Sample E. As a result of the measurement, it was confirmed that both the main surface of the sample D and the main surface of the sample E had an off angle within 10 ° from the {-1-12-4} surface.

Then, for each of Sample D and Sample E, the half width of XRC with respect to the {11-22} plane was measured. Specifically, it was measured by the following procedure.

(1) The central portion of the prototype base substrate (sample D and sample E, respectively) is irradiated with X-rays, and (000-2) surface diffraction XRC is measured. Specifically, the substrate is set in the X-ray diffractometer, and the detector and the substrate are set at a theoretical angle at which diffraction of the (000-2) plane can be obtained with respect to the incident X-rays. Then, the substrate is tilted in the vertical direction at an angle of 40 ° or more and 50 ° or less. Further, the base substrate is rotated in the in-plane direction (000-2), and the rotation angle at which the plane diffraction peak is obtained is searched for. Finally, the measurement is performed by adjusting various angles other than the in-plane rotation direction of the substrate so that the (000-2) plane diffraction peak can be obtained best. When the substrate is measured by the above procedure, the (000-2) plane diffraction peak is obtained only when X-rays are incident parallel to the m-axis. That is, this measurement also serves as axis alignment in the m-axis direction.

(2) Measure the m-axis incident XRC. Specifically, at the portion where the (000-2) plane XRC is measured (the central part of the base substrate), the {11-22} plane is axial (to obtain the best diffraction, other than the in-plane rotation direction of the substrate). Adjust various angles). After that, the {11-22} plane XRC is measured at a total of three points, that is, the central portion and two points separated from the central portion by 20 mm in the m-axis direction.

(3) c Measure the projection axis incident XRC. Specifically, after the measurement described in (2) is completed, the base substrate is rotated by 90 ° in the in-plane direction. As a result, the X-rays are incident on the c-projection axis (the projection axis in which the c-axis is projected onto the main surface). After that, the {11-22} plane is axially erected at the center, and the {11-22} plane XRC is measured for a total of three points, the center and two points 20 mm away from the center in the c projection axis direction. I do.

The measurement result of the sample D is shown in FIG. 7, and the measurement result of the sample E is shown in FIG. The value corresponding to (m) is the half width of XRC with respect to the {11-22} plane measured by incident X-rays parallel to the m-axis of the group III nitride semiconductor crystal, and corresponds to "m-axis incident". The value to be measured is the average value of three measurement points. The value corresponding to (c) is the half width of XRC with respect to the {11-22} plane measured by incidenting the X-ray parallel to the projection axis obtained by projecting the c-axis of the group III nitride semiconductor crystal onto the main plane. , The value corresponding to "c-axis projection axis incident" is the average value of three measurement points. The outline of the measurement points is as shown in the figure.

From FIG. 7, in the group III nitride semiconductor layer of the base substrate manufactured by the manufacturing method of the present embodiment, X-rays are incident on the main surface in parallel with the m-axis of the group III nitride semiconductor crystal, and the X-rays are incident. It can be seen that the half-price width of XRC with respect to the {11-22} plane measured by scanning the direction and the angle formed by the main plane is 500 arcsec or less. Further, X-rays are incident on the main surface of the group III nitride semiconductor layer in parallel with the projection axis obtained by projecting the c-axis of the group III nitride semiconductor crystal onto the main surface, and the incident direction of the X-rays and the main surface form the X-rays. It can be seen that the half-value width of XRC with respect to the {11-22} plane measured by scanning the angle is also 500 arcsec or less.

Further, "X-rays were incident on the main surface of the group III nitride semiconductor layer parallel to the m-axis of the group III nitride semiconductor crystal, and the angle formed by the incident direction of the X-rays and the main surface was scanned and measured {11. -22} Half-value width of XRC with respect to the plane, measured values at three points separated by 20 mm in the m-axis direction "and" Group III nitride X-rays with respect to the main surface of the semiconductor layer of group III nitride. It is the half-value width of XRC with respect to the {11-22} plane measured by scanning the angle formed by the incident direction of the X-ray and the main plane, incident parallel to the projection axis projected on the main plane of the c-axis of the semiconductor crystal. The difference between the maximum value and the minimum value in "measured values at three points separated by 20 mm in the direction of the projection axis projected on the main surface of the c-axis" is 50 arcsec. It turns out that it is within. That is, it can be seen that the anisotropy between the two is small.

On the other hand, as shown in FIG. 8, in the group III nitride semiconductor layer of the base substrate not produced by the manufacturing method of the present embodiment, X-rays are incident on the main surface in parallel with the m-axis of the group III nitride semiconductor crystal. It can be seen that the half-value width of XRC with respect to the {11-22} plane measured by scanning the angle formed by the incident direction of the X-ray and the main surface exceeds 500 arcsec. Further, X-rays are incident on the main surface of the group III nitride semiconductor layer in parallel with the projection axis obtained by projecting the c-axis of the group III nitride semiconductor crystal onto the main surface, and the incident direction of the X-rays and the main surface form the X-rays. It can be seen that the half-value width of XRC with respect to the {11-22} plane measured by scanning the angle also exceeds 500 arcsec.

It is known that when a nitride semiconductor is crystal-grown on an m-plane sapphire substrate, the growth plane, crystallinity, and crystal axis orientation of the nitride semiconductor differ depending on the presence or absence of nitride, the nitride temperature, and the film formation temperature. ing. Since the film formation temperature of the buffer layer is the same in the examples and the comparative examples, it is considered that the temperature of the heat treatment step S12 has the greatest influence on the production conditions.

From the results of the examples, it can be seen that by adjusting the temperature of the heat treatment step S12 to 800 ° C. or higher and 930 ° C. or lower, the half width of XRC with respect to the {11-22} plane becomes good. It can be seen that the temperature of the heat treatment step S12 has a great influence on the crystallinity of the buffer layer and the group III nitride semiconductor crystal and the orientation of the crystal axis.

<Fifth evaluation>
The characteristics of the group III nitride semiconductor substrate produced by the manufacturing method of this embodiment (see the flow in FIG. 1) are evaluated.

"Method of manufacturing a sample of an example"
A method for producing a sample of an example will be described. First, a base substrate having a group III nitride semiconductor layer (GaN layer) formed by the MOCVD method on a sapphire substrate having a diameter of Φ4 inch and a main surface orientation of m was prepared via a buffer layer. .. The film forming conditions at this time were the same as those of sample D. The plane orientation of the main surface of the group III nitride semiconductor layer was (-1-12-3), the maximum diameter was Φ4 inch, and the thickness was 15 μm.

Next, the base substrate was fixed to the carbon susceptor. Specifically, the back surface of the sapphire substrate was bonded to the main surface of the carbon susceptor using an alumina-based adhesive.

Next, a group III nitride semiconductor (GaN) was grown on the main surface of the group III nitride semiconductor layer by the HVPE method with the base substrate fixed to the carbon susceptor. As a result, a first growth layer (GaN layer) composed of a single crystal group III nitride semiconductor was formed. The growth conditions are as follows.

Growth temperature: 1040 ° C
Growth time: 15 hours V / III ratio: 10
Growth film thickness: 4.4 mm

Next, the laminate containing the carbon susceptor, the base substrate and the first growth layer was taken out from the HVPE apparatus and cooled to room temperature. There were cracks on the surface of the first growth layer after the cooling.

Next, a group III nitride semiconductor (GaN) was grown on the main surface of the first growth layer in which cracks were present by the HVPE method. As a result, a second growth layer (GaN layer) composed of a single crystal group III nitride semiconductor was formed. The growth conditions are as follows.

Growth temperature: 1040 ° C
Growth time: 14 hours V / III ratio: 10
Growth film thickness: 3.0 mm (total film thickness of the first growth layer 30 and the second growth layer 40 is 7.4 mm)

The maximum diameter of the second growth layer was about Φ4 inch. The maximum diameter of the surface including the second growth layer and the polycrystalline group III nitride semiconductor along the outer periphery thereof was about 130 mm. Moreover, no crack was generated in the second growth layer.

Next, the second growth layer was sliced, and the group III nitride semiconductor substrate was taken out so that the {11-23} plane and the {-1-12-3} plane became the main planes. After that, the main surface of the group III nitride semiconductor substrate was polished by mechanical polishing and chemical mechanical polishing (CMP). The {11-23} surface and the {-1-12-3} surface were sliced and polished so as to be the main surface, but the main surface of the group III nitride semiconductor substrate actually obtained after these processing was performed. May be a surface having an off angle within 1 ° from the {11-23} surface and a surface having an off angle within 1 ° from the {-1-12-3} surface.

A plurality of bulk crystals were prepared by the same method, and a substrate was prepared from each bulk.

"Manufacturing method of comparative sample"
In the sample of the comparative example, the base substrate was formed under the same film formation conditions as that of the sample E at the time of film formation of the group III nitride semiconductor layer by the MOCVD method. The diameter of the sapphire substrate was φ2 inch.

GaN crystals were grown on the obtained substrate by the HVPE method under the following conditions. After growth, the thick film was peeled off from the sapphire substrate by thermal stress when cooled to room temperature to obtain a group III nitride semiconductor self-supporting thick film having a diameter of 2 inches and a half size (semicircular shape).

Growth temperature: 1040 ° C
Growth time: 18 hours V / III ratio: 10

GaN crystal growth was performed twice on the obtained self-supporting thick film by the HVPE method using the following conditions to obtain a group III nitride semiconductor bulk crystal.

Growth temperature: 1040 ° C
Growth time: 12 hours + 11.5 hours V / III ratio: 10

The obtained bulk crystal was sliced, and a group III nitride semiconductor substrate having a {11-23} plane and a {-1-12-3} plane as main planes was taken out. After that, the main surface of the group III nitride semiconductor substrate was polished by mechanical polishing and chemical mechanical polishing (CMP).

"Evaluation result (Example)"
In the example, three group III nitride semiconductor substrates were manufactured by the above method. The RMS measured in an area of 1 μm × 1 μm square for each substrate was 1.14 nm, 1.13 nm, and 1.07 nm. The RMS measured in an area of 5 μm × 5 μm square was 1.41 nm, 0.99 nm, and 0.91 nm.

The Ra measured in the area of 1 μm × 1 μm square was 0.84 nm, 0.89 nm, and 0.85 nm. Ra measured in an area of 5 μm × 5 μm square was 1.03 nm, 0.78 nm, and 0.72 nm.

The Rv measured in the area of 1 μm × 1 μm square was -4.60 nm, −5.03 nm, and -4.35 nm. The Rv measured in the area of 5 μm × 5 μm square was −7.09 nm, -4.43 nm, and -3.49 nm.

The Rp measured in an area of 1 μm × 1 μm square was 9.18 nm, 4.06 nm, and 4.23 nm. The Rp measured in an area of 5 μm × 5 μm square was 2.70 nm, 4.92 nm, and 4.36 nm.

Next, each of FIGS. 9 (1) to 9 (3) shows a CL image of an area of 50 μm × 50 μm square at the center of each of the plurality of group III nitride semiconductor substrates. The scotoma density of the sample of FIG. 9 (1) is 1.3 × 10 ⁶ cm- ² , and the scotoma density of the sample of FIG. 9 (2) is 0.88 × 10 ⁶ cm- ² . (3) dark spot density of the sample was 1.20 × ¹⁰ 6 ^{cm -2.}

"Evaluation result (comparative example)"
In the comparative example, the RMS measured in an area of 1 μm × 1 μm square was 2.53 nm and 2.62 nm. The RMS measured in an area of 5 μm × 5 μm square was 3.10 nm and 3.12 nm.

Ra measured in an area of 1 μm × 1 μm square was 2.01 nm and 2.05 nm. The Ra measured in an area of 5 μm × 5 μm square was 2.27 nm and 2.39 nm.

The Rv measured in the area of 1 μm × 1 μm square was −8.12 nm and −7.95 nm. The Rv measured in an area of 5 μm × 5 μm square was −9.1 nm and −9.838 nm.

The Rp measured in the area of 1 μm × 1 μm square was 1.25 nm and 1.14 nm. The Rp measured in an area of 5 μm × 5 μm square was 3.61 nm and 2.41 nm.

Next, FIGS. 10 (1) to 10 (2) show CL images of an area of 50 μm × 50 μm square in the group III nitride semiconductor substrate. The scotoma density of the sample of FIG. 10 (1) was 8.12 × 10 ⁶ cm- ² , and the scotoma density of the sample of FIG. 10 (2) was 5.24 × 10 ⁶ cm- ² . The sample of the comparative example contained a large number of dark spots, that is, crystal defects, as compared with the sample of the example.

As can be seen by comparing the examples and the comparative examples, a certain correlation is observed between the surface roughness and the crystallinity of the self-standing substrate. Further, it can be seen that the crystallinity of the self-supporting substrate has a correlation with the crystallinity of the MOCVD base substrate, and that the surface roughness of the self-supporting substrate is improved by improving the crystallinity of the MOCVD base substrate.

Hereinafter, an example of the reference form will be added.
1. 1. It is composed of a group III nitride semiconductor, the main surface is a semipolar surface, and the surface roughness RMS measured in an area of 5 μm × 5 μm square of the main surface is 0.05 nm or more and 1.50 nm or less. Material semiconductor substrate.
2. 2. In the group III nitride semiconductor substrate according to 1.
A group III nitride semiconductor substrate having a surface roughness Ra measured in an area of 5 μm × 5 μm square on the main surface of 0.05 nm or more and 1.20 nm or less.
3. 3. In the group III nitride semiconductor substrate according to 1 or 2.
A group III nitride semiconductor substrate having a surface roughness Rv measured in an area of 5 μm × 5 μm square on the main surface of -10.0 nm or more and −0.05 nm or less.
4. In the group III nitride semiconductor substrate according to any one of 1 to 3.
A group III nitride semiconductor substrate having a surface roughness Rp of 0.05 nm or more and 5.0 nm or less measured in an area of 5 μm × 5 μm square on the main surface.
5. In the group III nitride semiconductor substrate according to any one of 1 to 4.
A group III nitride semiconductor substrate having a dark spot density of 5 × 10 ⁶ cm- ^{2 or less in the CL image of the main surface.}
6. In the group III nitride semiconductor substrate according to any one of 1 to 5.
The main surface is a group III nitride semiconductor substrate which is a {11-2X} surface or a surface having an off angle within 1 ° with respect to the {11-2X} surface (X is an integer of 1 or more).
7. The preparatory process for preparing the base board and
A group III nitride semiconductor layer forming step of epitaxially growing a group III nitride semiconductor on the main surface of the base substrate by the HVPE method to form a group III nitride semiconductor layer.
A cutting process for cutting out a group III nitride semiconductor substrate from the group III nitride semiconductor layer, and
The processing process for processing the surface of the group III nitride semiconductor substrate and
Have,
The base substrate is
Includes a first layer composed of group III nitride semiconductors
The main surface of the first layer becomes the main surface of the base substrate.
The main surface of the first layer is represented by the Miller index (hkml), where l is a semi-polar surface less than 0.
X-rays were incident parallel to the main surface of the first layer in parallel with the m-axis of the group III nitride semiconductor crystal, and the angle formed by the incident direction of the X-rays and the main surface was scanned and measured {11-22. } A method for manufacturing a group III nitride semiconductor substrate, wherein the half price width of the XRC (X-ray Rocking Curve) with respect to the plane is 500 arcsec or less.
8. In the method for manufacturing a group III nitride semiconductor substrate according to 7.
In the cutting step, the group III nitride whose main surface is a {11-2X} surface or a surface having an off angle within 1 ° with respect to the {11-2X} surface (X is an integer of 1 or more). A method for manufacturing a group III nitride semiconductor substrate by cutting out a semiconductor substrate.

This application claims priority on the basis of Japanese application Japanese Patent Application No. 2019-020502 filed on February 7, 2019, the entire disclosure of which is incorporated herein by reference.

Claims (8)

It is composed of a group III nitride semiconductor, the main surface is a semipolar surface, and the surface roughness RMS measured in an area of 5 μm × 5 μm square of the main surface is 0.05 nm or more and 1.50 nm or less. Material semiconductor substrate. In the group III nitride semiconductor substrate according to claim 1,
A group III nitride semiconductor substrate having a surface roughness Ra measured in an area of 5 μm × 5 μm square on the main surface of 0.05 nm or more and 1.20 nm or less. In the group III nitride semiconductor substrate according to claim 1 or 2.
A group III nitride semiconductor substrate having a surface roughness Rv measured in an area of 5 μm × 5 μm square on the main surface of -10.0 nm or more and −0.05 nm or less. In the group III nitride semiconductor substrate according to any one of claims 1 to 3.
A group III nitride semiconductor substrate having a surface roughness Rp of 0.05 nm or more and 5.0 nm or less measured in an area of 5 μm × 5 μm square on the main surface. In the group III nitride semiconductor substrate according to any one of claims 1 to 4.
A group III nitride semiconductor substrate having a ^{dark spot density of 5 × 10 6} cm- ² or less in the CL (Cathodoluminescence) image of the main surface. In the group III nitride semiconductor substrate according to any one of claims 1 to 5.
The main surface is a group III nitride semiconductor substrate which is a {11-2X} surface or a surface having an off angle within 1 ° with respect to the {11-2X} surface (X is an integer of 1 or more). The preparatory process for preparing the base board and
A group III nitride semiconductor layer forming step of epitaxially growing a group III nitride semiconductor on the main surface of the base substrate by the HVPE method to form a group III nitride semiconductor layer.
A cutting process for cutting out a group III nitride semiconductor substrate from the group III nitride semiconductor layer, and
The processing process for processing the surface of the group III nitride semiconductor substrate and
Have,
The base substrate is
Includes a first layer composed of group III nitride semiconductors
The main surface of the first layer becomes the main surface of the base substrate.
The main surface of the first layer is represented by the Miller index (hkml), where l is a semi-polar surface less than 0.
X-rays were incident parallel to the main surface of the first layer in parallel with the m-axis of the group III nitride semiconductor crystal, and the angle formed by the incident direction of the X-rays and the main surface was scanned and measured {11-22. } A method for manufacturing a group III nitride semiconductor substrate, wherein the half price width of the XRC (X-ray Rocking Curve) with respect to the plane is 500 arcsec or less. In the method for manufacturing a group III nitride semiconductor substrate according to claim 7.
In the cutting step, the group III nitride whose main surface is a {11-2X} surface or a surface having an off angle within 1 ° with respect to the {11-2X} surface (X is an integer of 1 or more). A method for manufacturing a group III nitride semiconductor substrate by cutting out a semiconductor substrate.

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